mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
24 lines
421 B
Verilog
24 lines
421 B
Verilog
module gold (input clock, ctrl, din, output reg dout);
|
|
always @(posedge clock) begin
|
|
if (1'b1) begin
|
|
if (1'b0) begin end else begin
|
|
dout <= 0;
|
|
end
|
|
if (ctrl)
|
|
dout <= din;
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
module gate (input clock, ctrl, din, output reg dout);
|
|
always @(posedge clock) begin
|
|
if (1'b1) begin
|
|
if (1'b0) begin end else begin
|
|
dout <= 0;
|
|
end
|
|
end
|
|
if (ctrl)
|
|
dout <= din;
|
|
end
|
|
endmodule
|