mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-27 21:48:58 +00:00
const: represent string constants as string, assert not accessed as bits
This commit is contained in:
parent
960bca0196
commit
498e0498c5
81 changed files with 764 additions and 690 deletions
|
@ -1564,6 +1564,12 @@ parameter IDLE = 4'd0,
|
|||
RD_S2 = 4'd12;
|
||||
endmodule
|
||||
|
||||
module DCS (...);
|
||||
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
|
||||
input [3:0] CLKSEL;
|
||||
output CLKOUT;
|
||||
endmodule
|
||||
|
||||
module DQCE (...);
|
||||
input CLKIN;
|
||||
input CE;
|
||||
|
@ -1681,6 +1687,10 @@ endmodule
|
|||
module ADC (...);
|
||||
endmodule
|
||||
|
||||
module BANDGAP (...);
|
||||
input BGEN;
|
||||
endmodule
|
||||
|
||||
module CLKDIV2 (...);
|
||||
parameter GSREN = "false";
|
||||
input HCLKIN, RESETN;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue