From 498e0498c56c7b8f78871359f4e70a4f43483d2b Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 29 Jul 2024 16:38:32 +0200 Subject: [PATCH] const: represent string constants as string, assert not accessed as bits --- .gitcommit | 2 +- Makefile | 9 +- abc | 2 +- backends/blif/blif.cc | 2 +- backends/btor/btor.cc | 6 +- backends/cxxrtl/cxxrtl_backend.cc | 10 +- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +- backends/edif/edif.cc | 14 +- backends/firrtl/firrtl.cc | 6 +- backends/intersynth/intersynth.cc | 8 +- backends/jny/jny.cc | 2 +- backends/rtlil/rtlil_backend.cc | 12 +- backends/simplec/simplec.cc | 2 +- backends/smt2/smt2.cc | 2 +- backends/verilog/verilog_backend.cc | 24 +- .../interactive_investigation.rst | 2 +- frontends/ast/ast.cc | 49 ++- frontends/ast/ast.h | 4 +- frontends/ast/genrtlil.cc | 10 +- frontends/ast/simplify.cc | 66 ++-- frontends/blif/blifparse.cc | 20 +- frontends/rtlil/rtlil_parser.y | 2 +- frontends/verific/verific.cc | 26 +- kernel/bitpattern.h | 2 +- kernel/calc.cc | 164 +++++----- kernel/cellaigs.cc | 5 +- kernel/celltypes.h | 16 +- kernel/consteval.h | 14 +- kernel/ff.cc | 8 +- kernel/ffinit.h | 2 +- kernel/ffmerge.cc | 24 +- kernel/macc.h | 4 +- kernel/mem.cc | 30 +- kernel/rtlil.cc | 290 +++++++++++------- kernel/rtlil.h | 55 ++-- kernel/satgen.cc | 4 +- kernel/yosys.cc | 59 ++-- kernel/yw.cc | 4 +- passes/cmds/bugpoint.cc | 2 +- passes/cmds/clean_zerowidth.cc | 2 +- passes/cmds/dft_tag.cc | 2 +- passes/cmds/printattrs.cc | 4 +- passes/cmds/setundef.cc | 8 +- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_extract.cc | 4 +- passes/fsm/fsm_map.cc | 30 +- passes/fsm/fsm_opt.cc | 22 +- passes/fsm/fsm_recode.cc | 6 +- passes/fsm/fsmdata.h | 26 +- passes/hierarchy/submod.cc | 2 +- passes/memory/memory_libmap.cc | 11 +- passes/opt/opt_clean.cc | 8 +- passes/opt/opt_dff.cc | 8 +- passes/opt/opt_expr.cc | 92 +++--- passes/opt/opt_ffinv.cc | 8 +- passes/opt/opt_mem.cc | 12 +- passes/opt/opt_merge.cc | 9 +- passes/opt/pmux2shiftx.cc | 6 +- passes/opt/share.cc | 22 +- passes/opt/wreduce.cc | 4 +- passes/pmgen/xilinx_dsp.cc | 4 +- passes/pmgen/xilinx_dsp.pmg | 2 +- passes/proc/proc_init.cc | 6 +- passes/proc/proc_rom.cc | 20 +- passes/sat/eval.cc | 8 +- passes/sat/expose.cc | 2 +- passes/sat/formalff.cc | 4 +- passes/sat/sat.cc | 16 +- passes/sat/sim.cc | 28 +- passes/sat/synthprop.cc | 26 +- passes/techmap/abc9_ops.cc | 2 +- passes/techmap/dffinit.cc | 8 +- passes/techmap/techmap.cc | 4 +- passes/techmap/zinit.cc | 6 +- passes/tests/test_cell.cc | 4 +- techlibs/gowin/cells_sim.v | 17 +- techlibs/gowin/cells_xtra.py | 2 +- techlibs/gowin/cells_xtra.v | 10 + techlibs/greenpak4/greenpak4_dffinv.cc | 16 +- techlibs/quicklogic/ql_dsp_simd.cc | 8 +- techlibs/xilinx/xilinx_dffopt.cc | 8 +- 81 files changed, 764 insertions(+), 690 deletions(-) diff --git a/.gitcommit b/.gitcommit index 6828f88dc..46b7856fb 100644 --- a/.gitcommit +++ b/.gitcommit @@ -1 +1 @@ -$Format:%H$ +$Format:%h$ diff --git a/Makefile b/Makefile index 456aa2a40..66e6c91ae 100644 --- a/Makefile +++ b/Makefile @@ -148,14 +148,14 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.43+34 +YOSYS_VER := 0.43+11 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo # will have this file in its unexpanded form tough, in which case we fall # back to calling git directly. TARBALL_GIT_REV := $(shell cat $(YOSYS_SRC)/.gitcommit) -ifneq ($(findstring Format:,$(TARBALL_GIT_REV)),) +ifeq ($(TARBALL_GIT_REV),$$Format:%h$$) GIT_REV := $(shell GIT_DIR=$(YOSYS_SRC)/.git git rev-parse --short=9 HEAD || echo UNKNOWN) else GIT_REV := $(TARBALL_GIT_REV) @@ -579,7 +579,6 @@ S = endif $(eval $(call add_include_file,kernel/binding.h)) -$(eval $(call add_include_file,kernel/bitpattern.h)) $(eval $(call add_include_file,kernel/cellaigs.h)) $(eval $(call add_include_file,kernel/celledges.h)) $(eval $(call add_include_file,kernel/celltypes.h)) @@ -779,10 +778,10 @@ check-git-abc: exit 1; \ elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \ exit 0; \ - elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%[hH]\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \ + elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \ echo "'abc' comes from a tarball. Continuing."; \ exit 0; \ - elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%[hH]\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \ + elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \ echo "Error: 'abc' is not configured as a git submodule."; \ echo "To resolve this:"; \ echo "1. Back up your changes: Save any modifications from the 'abc' directory to another location."; \ diff --git a/abc b/abc index 28d955ca9..237d81397 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 28d955ca97a1c4be3aed4062aec0241a734fac5d +Subproject commit 237d81397fcc85dd3894bf1a449d2955cd3df02d diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 788b7f951..7b321b152 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -387,7 +387,7 @@ struct BlifDumper auto &inputs = cell->getPort(ID::A); auto width = cell->parameters.at(ID::WIDTH).as_int(); auto depth = cell->parameters.at(ID::DEPTH).as_int(); - vector table = cell->parameters.at(ID::TABLE).bits; + vector table = cell->parameters.at(ID::TABLE).bits(); while (GetSize(table) < 2*width*depth) table.push_back(State::S0); log_assert(inputs.size() == width); diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 9cfd967e5..c3637bc8f 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -711,9 +711,9 @@ struct BtorWorker Const initval; for (int i = 0; i < GetSize(sig_q); i++) if (initbits.count(sig_q[i])) - initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0); + initval.bits().push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0); else - initval.bits.push_back(State::Sx); + initval.bits().push_back(State::Sx); int nid_init_val = -1; @@ -1042,7 +1042,7 @@ struct BtorWorker Const c(bit.data); while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr) - c.bits.push_back(sig[i+GetSize(c)].data); + c.bits().push_back(sig[i+GetSize(c)].data); if (consts.count(c) == 0) { int sid = get_bv_sid(GetSize(c)); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 8dc14863d..3ac113ae0 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -864,7 +864,7 @@ struct CxxrtlWorker { if (!module->has_attribute(ID(cxxrtl_template))) return {}; - if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING) + if (!(module->attributes.at(ID(cxxrtl_template)).flags & RTLIL::CONST_FLAG_STRING)) log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module)); std::vector param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t"); @@ -1665,15 +1665,15 @@ struct CxxrtlWorker { switch (bit) { case RTLIL::S0: case RTLIL::S1: - compare_mask.bits.push_back(RTLIL::S1); - compare_value.bits.push_back(bit); + compare_mask.bits().push_back(RTLIL::S1); + compare_value.bits().push_back(bit); break; case RTLIL::Sx: case RTLIL::Sz: case RTLIL::Sa: - compare_mask.bits.push_back(RTLIL::S0); - compare_value.bits.push_back(RTLIL::S0); + compare_mask.bits().push_back(RTLIL::S0); + compare_value.bits().push_back(RTLIL::S0); break; default: diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index d1d6bd8dc..b84693f3f 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -750,7 +750,7 @@ std::ostream &operator<<(std::ostream &os, const value &val) { auto old_flags = os.flags(std::ios::right); auto old_width = os.width(0); auto old_fill = os.fill('0'); - os << val.bits << '\'' << std::hex; + os << val.bits() << '\'' << std::hex; for (size_t n = val.chunks - 1; n != (size_t)-1; n--) { if (n == val.chunks - 1 && Bits % value::chunk::bits != 0) os.width((Bits % value::chunk::bits + 3) / 4); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 553eb23d6..0e3d9559c 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -334,20 +334,20 @@ struct EdifBackend : public Backend { auto add_prop = [&](IdString name, Const val) { if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0) *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str()); - else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def()) + else if (val.size() <= 32 && RTLIL::SigSpec(val).is_fully_def()) *f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int()); else { std::string hex_string = ""; - for (size_t i = 0; i < val.bits.size(); i += 4) { + for (size_t i = 0; i < val.size(); i += 4) { int digit_value = 0; - if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1; - if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2; - if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4; - if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8; + if (i+0 < val.size() && val.bits().at(i+0) == RTLIL::State::S1) digit_value |= 1; + if (i+1 < val.size() && val.bits().at(i+1) == RTLIL::State::S1) digit_value |= 2; + if (i+2 < val.size() && val.bits().at(i+2) == RTLIL::State::S1) digit_value |= 4; + if (i+3 < val.size() && val.bits().at(i+3) == RTLIL::State::S1) digit_value |= 8; char digit_str[2] = { "0123456789abcdef"[digit_value], 0 }; hex_string = std::string(digit_str) + hex_string; } - *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str()); + *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits()), hex_string.c_str()); } }; for (auto module : sorted_modules) diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index dc76dbeec..f95a00ae5 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -149,7 +149,7 @@ std::string dump_const(const RTLIL::Const &data) // Numeric (non-real) parameter. else { - int width = data.bits.size(); + int width = data.size(); // If a standard 32-bit int, then emit standard int value like "56" or // "-56". Firrtl supports negative-valued int literals. @@ -163,7 +163,7 @@ std::string dump_const(const RTLIL::Const &data) for (int i = 0; i < width; i++) { - switch (data.bits[i]) + switch (data.bits()[i]) { case State::S0: break; case State::S1: int_val |= (1 << i); break; @@ -205,7 +205,7 @@ std::string dump_const(const RTLIL::Const &data) for (int i = width - 1; i >= 0; i--) { log_assert(i < width); - switch (data.bits[i]) + switch (data.bits()[i]) { case State::S0: res_str += "0"; break; case State::S1: res_str += "1"; break; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 59173c4a2..35e20ee8b 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -176,11 +176,11 @@ struct IntersynthBackend : public Backend { } } for (auto ¶m : cell->parameters) { - celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first)); - if (param.second.bits.size() != 32) { + celltype_code += stringf(" cfg:%d %s", int(param.second.size()), log_id(param.first)); + if (param.second.size() != 32) { node_code += stringf(" %s '", log_id(param.first)); - for (int i = param.second.bits.size()-1; i >= 0; i--) - node_code += param.second.bits[i] == State::S1 ? "1" : "0"; + for (int i = param.second.size()-1; i >= 0; i--) + node_code += param.second.bits()[i] == State::S1 ? "1" : "0"; } else node_code += stringf(" %s 0x%x", log_id(param.first), param.second.as_int()); } diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index 1c163dba5..eb33565a8 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -334,7 +334,7 @@ struct JnyWriter f << "\"" << escape_string(str) << "\""; } else if ((v.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) == RTLIL::ConstFlags::CONST_FLAG_SIGNED) { - f << stringf("\"%dsd %d\"", v.size(), v.as_int(true)); + f << stringf("\"%zusd %d\"", v.size(), v.as_int(true)); } else if ((v.flags & RTLIL::ConstFlags::CONST_FLAG_REAL) == RTLIL::ConstFlags::CONST_FLAG_REAL) { } else { diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 574eb3aaa..66304647c 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -33,13 +33,13 @@ YOSYS_NAMESPACE_BEGIN void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) { if (width < 0) - width = data.bits.size() - offset; - if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) { + width = data.size() - offset; + if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.size()) { if (width == 32 && autoint) { int32_t val = 0; for (int i = 0; i < width; i++) { - log_assert(offset+i < (int)data.bits.size()); - switch (data.bits[offset+i]) { + log_assert(offset+i < (int)data.size()); + switch (data.bits()[offset+i]) { case State::S0: break; case State::S1: val |= 1 << i; break; default: val = -1; break; @@ -55,8 +55,8 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi f << "x"; } else { for (int i = offset+width-1; i >= offset; i--) { - log_assert(i < (int)data.bits.size()); - switch (data.bits[i]) { + log_assert(i < (int)data.size()); + switch (data.bits()[i]) { case State::S0: f << stringf("0"); break; case State::S1: f << stringf("1"); break; case RTLIL::Sx: f << stringf("x"); break; diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index e283dcf7c..e70c62a71 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -657,7 +657,7 @@ struct SimplecWorker { SigSpec sig = sigmaps.at(module)(w); Const val = w->attributes.at(ID::init); - val.bits.resize(GetSize(sig), State::Sx); + val.bits().resize(GetSize(sig), State::Sx); for (int i = 0; i < GetSize(sig); i++) if (val[i] == State::S0 || val[i] == State::S1) { diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index c702d5e7e..2587696f2 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1077,7 +1077,7 @@ struct Smt2Worker RTLIL::SigSpec sig = sigmap(wire); Const val = wire->attributes.at(ID::init); - val.bits.resize(GetSize(sig), State::Sx); + val.bits().resize(GetSize(sig), State::Sx); if (bvmode && GetSize(sig) > 1) { Const mask(State::S1, GetSize(sig)); bool use_mask = false; diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 31bbc996f..fafc7389e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -191,7 +191,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o { bool set_signed = (data.flags & RTLIL::CONST_FLAG_SIGNED) != 0; if (width < 0) - width = data.bits.size() - offset; + width = data.size() - offset; if (width == 0) { // See IEEE 1364-2005 Clause 5.1.14. f << "{0{1'b0}}"; @@ -199,14 +199,14 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o } if (nostr) goto dump_hex; - if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) { + if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.size()) { if (width == 32 && !no_decimal && !nodec) { int32_t val = 0; for (int i = offset+width-1; i >= offset; i--) { - log_assert(i < (int)data.bits.size()); - if (data.bits[i] != State::S0 && data.bits[i] != State::S1) + log_assert(i < (int)data.size()); + if (data.bits()[i] != State::S0 && data.bits()[i] != State::S1) goto dump_hex; - if (data.bits[i] == State::S1) + if (data.bits()[i] == State::S1) val |= 1 << (i - offset); } if (decimal) @@ -221,8 +221,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o goto dump_bin; vector bin_digits, hex_digits; for (int i = offset; i < offset+width; i++) { - log_assert(i < (int)data.bits.size()); - switch (data.bits[i]) { + log_assert(i < (int)data.size()); + switch (data.bits()[i]) { case State::S0: bin_digits.push_back('0'); break; case State::S1: bin_digits.push_back('1'); break; case RTLIL::Sx: bin_digits.push_back('x'); break; @@ -275,8 +275,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o if (width == 0) f << stringf("0"); for (int i = offset+width-1; i >= offset; i--) { - log_assert(i < (int)data.bits.size()); - switch (data.bits[i]) { + log_assert(i < (int)data.size()); + switch (data.bits()[i]) { case State::S0: f << stringf("0"); break; case State::S1: f << stringf("1"); break; case RTLIL::Sx: f << stringf("x"); break; @@ -318,10 +318,10 @@ void dump_reg_init(std::ostream &f, SigSpec sig) for (auto bit : active_sigmap(sig)) { if (active_initdata.count(bit)) { - initval.bits.push_back(active_initdata.at(bit)); + initval.bits().push_back(active_initdata.at(bit)); gotinit = true; } else { - initval.bits.push_back(State::Sx); + initval.bits().push_back(State::Sx); } } @@ -751,7 +751,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) if (port.wide_log2) { Const addr_lo; for (int i = 0; i < port.wide_log2; i++) - addr_lo.bits.push_back(State(sub >> i & 1)); + addr_lo.bits().push_back(State(sub >> i & 1)); os << "{"; os << temp_id; os << ", "; diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index 03a1faefa..db34f041b 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -115,7 +115,7 @@ leads us to the third diagram: Output of the third :cmd:ref:`show` command in :ref:`example_ys` -Here we see that the :cmd:ref:`opt` command not only has removed the artifacts +Here we see that the :cmd:ref:`proc` command not only has removed the artifacts left behind by :cmd:ref:`proc`, but also determined correctly that it can remove the first ``$mux`` cell without changing the behavior of the circuit. diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index d21b8f02d..9b7434478 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -20,10 +20,10 @@ * * This is the AST frontend library. * - * The AST frontend library is not a frontend on its own but provides an - * abstract syntax tree (AST) abstraction for the open source Verilog frontend - * at frontends/verilog. - * + * The AST frontend library is not a frontend on it's own but provides a + * generic abstract syntax tree (AST) abstraction for HDL code and can be + * used by HDL frontends. See "ast.h" for an overview of the API and the + * Verilog frontend for an usage example. * */ @@ -933,15 +933,7 @@ RTLIL::Const AstNode::asAttrConst() const { log_assert(type == AST_CONSTANT); - RTLIL::Const val; - val.bits = bits; - - if (is_string) { - val.flags |= RTLIL::CONST_FLAG_STRING; - log_assert(val.decode_string() == str); - } - - return val; + return is_string ? RTLIL::Const(str) : RTLIL::Const(bits); } RTLIL::Const AstNode::asParaConst() const @@ -987,7 +979,7 @@ uint64_t AstNode::asInt(bool is_signed) uint64_t ret = 0; for (int i = 0; i < 64; i++) - if (v.bits.at(i) == RTLIL::State::S1) + if (v.bits().at(i) == RTLIL::State::S1) ret |= uint64_t(1) << i; return ret; @@ -1005,15 +997,15 @@ double AstNode::asReal(bool is_signed) { RTLIL::Const val(bits); - bool is_negative = is_signed && !val.bits.empty() && val.bits.back() == RTLIL::State::S1; + bool is_negative = is_signed && !val.bits().empty() && val.bits().back() == RTLIL::State::S1; if (is_negative) - val = const_neg(val, val, false, false, val.bits.size()); + val = const_neg(val, val, false, false, val.size()); double v = 0; - for (size_t i = 0; i < val.bits.size(); i++) + for (size_t i = 0; i < val.size(); i++) // IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in // the net or the variable shall be treated as zero upon conversion. - if (val.bits.at(i) == RTLIL::State::S1) + if (val.bits().at(i) == RTLIL::State::S1) v += exp2(i); if (is_negative) v *= -1; @@ -1036,15 +1028,15 @@ RTLIL::Const AstNode::realAsConst(int width) #else if (!std::isfinite(v)) { #endif - result.bits = std::vector(width, RTLIL::State::Sx); + result.bits() = std::vector(width, RTLIL::State::Sx); } else { bool is_negative = v < 0; if (is_negative) v *= -1; for (int i = 0; i < width; i++, v /= 2) - result.bits.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0); + result.bits().push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0); if (is_negative) - result = const_neg(result, result, false, false, result.bits.size()); + result = const_neg(result, result, false, false, result.size()); } return result; } @@ -1741,8 +1733,15 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict= 0; i--) { - switch (val.bits[i]) { + switch (val.bits()[i]) { case RTLIL::State::S0: res.push_back('0'); break; case RTLIL::State::S1: res.push_back('1'); break; case RTLIL::State::Sx: res.push_back('x'); break; @@ -1850,7 +1849,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictsecond.flags & RTLIL::CONST_FLAG_STRING) != 0) child->children[0] = AstNode::mkconst_str(it->second.decode_string()); else - child->children[0] = AstNode::mkconst_bits(it->second.bits, (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); + child->children[0] = AstNode::mkconst_bits(it->second.bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); rewritten.insert(it->first); } @@ -1863,7 +1862,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictchildren.push_back(AstNode::mkconst_str(param.second.decode_string())); else - defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); + defparam->children.push_back(AstNode::mkconst_bits(param.second.bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); new_ast->children.push_back(defparam); } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 6c4a1e15a..59a393e08 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -17,9 +17,7 @@ * * --- * - * The AST frontend library is not a frontend on its own but provides an - * abstract syntax tree (AST) abstraction for the open source Verilog frontend - * at frontends/verilog. + * This is support code for the Verilog frontend at frontends/verilog * */ diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 3d47bd3c0..aa0e6602a 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -735,10 +735,10 @@ struct AST_INTERNAL::ProcessGenerator for (auto sync : proc->syncs) { if (sync->type == RTLIL::STp) { triggers.append(sync->signal); - polarity.bits.push_back(RTLIL::S1); + polarity.bits().push_back(RTLIL::S1); } else if (sync->type == RTLIL::STn) { triggers.append(sync->signal); - polarity.bits.push_back(RTLIL::S0); + polarity.bits().push_back(RTLIL::S0); } } @@ -832,10 +832,10 @@ struct AST_INTERNAL::ProcessGenerator for (auto sync : proc->syncs) { if (sync->type == RTLIL::STp) { triggers.append(sync->signal); - polarity.bits.push_back(RTLIL::S1); + polarity.bits().push_back(RTLIL::S1); } else if (sync->type == RTLIL::STn) { triggers.append(sync->signal); - polarity.bits.push_back(RTLIL::S0); + polarity.bits().push_back(RTLIL::S0); } } @@ -892,7 +892,7 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx); for (int i = 0; i < portid; i++) { int new_bit = port_map[std::make_pair(memid, i)]; - priority_mask.bits[new_bit] = orig_priority_mask.bits[i]; + priority_mask.bits()[new_bit] = orig_priority_mask.bits()[i]; } action.priority_mask = priority_mask; sync->mem_write_actions.push_back(action); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3d8478ef1..017091aff 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1660,8 +1660,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (v->type == AST_CONSTANT && v->bits_only_01()) { RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint); RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1); - log_assert(match.bits.size() == 1); - if (match.bits.front() == RTLIL::State::S1) { + log_assert(match.size() == 1); + if (match.bits().front() == RTLIL::State::S1) { while (i+1 < GetSize(children)) delete children[++i]; goto keep_const_cond; @@ -1963,7 +1963,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (children[1]->type != AST_CONSTANT) input_error("Right operand of to_bits expression is not constant!\n"); RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed); - newNode = mkconst_bits(new_value.bits, children[1]->is_signed); + newNode = mkconst_bits(new_value.bits(), children[1]->is_signed); goto apply_newNode; } @@ -2126,7 +2126,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n", children[0]->realvalue, log_signal(constvalue)); delete children[0]; - children[0] = mkconst_bits(constvalue.bits, sign_hint); + children[0] = mkconst_bits(constvalue.bits(), sign_hint); fixup_hierarchy_flags(); did_something = true; } @@ -2135,7 +2135,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin RTLIL::SigSpec sig(children[0]->bits); sig.extend_u0(width, children[0]->is_signed); AstNode *old_child_0 = children[0]; - children[0] = mkconst_bits(sig.as_const().bits, is_signed); + children[0] = mkconst_bits(sig.as_const().bits(), is_signed); delete old_child_0; fixup_hierarchy_flags(); } @@ -3435,8 +3435,8 @@ skip_dynamic_range_lvalue_expansion:; delete buf; uint32_t result = 0; - for (size_t i = 0; i < arg_value.bits.size(); i++) - if (arg_value.bits.at(i) == RTLIL::State::S1) + for (size_t i = 0; i < arg_value.size(); i++) + if (arg_value.bits().at(i) == RTLIL::State::S1) result = i + 1; newNode = mkconst_int(result, true); @@ -4115,14 +4115,14 @@ replace_fcall_later:; case AST_BIT_NOT: if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = RTLIL::const_not(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.bits(), sign_hint); } break; case AST_TO_SIGNED: case AST_TO_UNSIGNED: if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = children[0]->bitsAsConst(width_hint, sign_hint); - newNode = mkconst_bits(y.bits, type == AST_TO_SIGNED); + newNode = mkconst_bits(y.bits(), type == AST_TO_SIGNED); } break; if (0) { case AST_BIT_AND: const_func = RTLIL::const_and; } @@ -4132,7 +4132,7 @@ replace_fcall_later:; if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.bits(), sign_hint); } break; if (0) { case AST_REDUCE_AND: const_func = RTLIL::const_reduce_and; } @@ -4142,13 +4142,13 @@ replace_fcall_later:; if (0) { case AST_REDUCE_BOOL: const_func = RTLIL::const_reduce_bool; } if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, false, false, -1); - newNode = mkconst_bits(y.bits, false); + newNode = mkconst_bits(y.bits(), false); } break; case AST_LOGIC_NOT: if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = RTLIL::const_logic_not(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1); - newNode = mkconst_bits(y.bits, false); + newNode = mkconst_bits(y.bits(), false); } else if (children[0]->isConst()) { newNode = mkconst_int(children[0]->asReal(sign_hint) == 0, false, 1); @@ -4159,7 +4159,7 @@ replace_fcall_later:; if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), RTLIL::Const(children[1]->bits), children[0]->is_signed, children[1]->is_signed, -1); - newNode = mkconst_bits(y.bits, false); + newNode = mkconst_bits(y.bits(), false); } else if (children[0]->isConst() && children[1]->isConst()) { if (type == AST_LOGIC_AND) @@ -4176,7 +4176,7 @@ replace_fcall_later:; if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.bits(), sign_hint); } else if (type == AST_POW && children[0]->isConst() && children[1]->isConst()) { newNode = new AstNode(AST_REALVALUE); @@ -4196,7 +4196,7 @@ replace_fcall_later:; bool cmp_signed = children[0]->is_signed && children[1]->is_signed; RTLIL::Const y = const_func(children[0]->bitsAsConst(cmp_width, cmp_signed), children[1]->bitsAsConst(cmp_width, cmp_signed), cmp_signed, cmp_signed, 1); - newNode = mkconst_bits(y.bits, false); + newNode = mkconst_bits(y.bits(), false); } else if (children[0]->isConst() && children[1]->isConst()) { bool cmp_signed = (children[0]->type == AST_REALVALUE || children[0]->is_signed) && (children[1]->type == AST_REALVALUE || children[1]->is_signed); @@ -4221,7 +4221,7 @@ replace_fcall_later:; if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.bits(), sign_hint); } else if (children[0]->isConst() && children[1]->isConst()) { newNode = new AstNode(AST_REALVALUE); @@ -4240,7 +4240,7 @@ replace_fcall_later:; if (0) { case AST_NEG: const_func = RTLIL::const_neg; } if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint); - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.bits(), sign_hint); } else if (children[0]->isConst()) { newNode = new AstNode(AST_REALVALUE); @@ -4268,10 +4268,10 @@ replace_fcall_later:; newNode->realvalue = choice->asReal(sign_hint); } else { RTLIL::Const y = choice->bitsAsConst(width_hint, sign_hint); - if (choice->is_string && y.bits.size() % 8 == 0 && sign_hint == false) - newNode = mkconst_str(y.bits); + if (choice->is_string && y.size() % 8 == 0 && sign_hint == false) + newNode = mkconst_str(y.bits()); else - newNode = mkconst_bits(y.bits, sign_hint); + newNode = mkconst_bits(y.bits(), sign_hint); } } else if (choice->isConst()) { @@ -4280,11 +4280,11 @@ replace_fcall_later:; } else if (children[1]->type == AST_CONSTANT && children[2]->type == AST_CONSTANT) { RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint); RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint); - log_assert(a.bits.size() == b.bits.size()); - for (size_t i = 0; i < a.bits.size(); i++) - if (a.bits[i] != b.bits[i]) - a.bits[i] = RTLIL::State::Sx; - newNode = mkconst_bits(a.bits, sign_hint); + log_assert(a.size() == b.size()); + for (size_t i = 0; i < a.size(); i++) + if (a.bits()[i] != b.bits()[i]) + a.bits()[i] = RTLIL::State::Sx; + newNode = mkconst_bits(a.bits(), sign_hint); } else if (children[1]->isConst() && children[2]->isConst()) { newNode = new AstNode(AST_REALVALUE); if (children[1]->asReal(sign_hint) == children[2]->asReal(sign_hint)) @@ -4305,7 +4305,7 @@ replace_fcall_later:; val = children[1]->bitsAsUnsizedConst(width); else val = children[1]->bitsAsConst(width); - newNode = mkconst_bits(val.bits, children[1]->is_signed); + newNode = mkconst_bits(val.bits(), children[1]->is_signed); } break; case AST_CONCAT: @@ -4890,7 +4890,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, target->str = str; target->id2ast = id2ast; target->was_checked = true; - block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).bits, false))); + block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).bits(), false))); pos = epos; } } @@ -5245,7 +5245,7 @@ bool AstNode::is_simple_const_expr() bool AstNode::replace_variables(std::map &variables, AstNode *fcall, bool must_succeed) { if (type == AST_IDENTIFIER && variables.count(str)) { - int offset = variables.at(str).offset, width = variables.at(str).val.bits.size(); + int offset = variables.at(str).offset, width = variables.at(str).val.size(); if (!children.empty()) { if (children.size() != 1 || children.at(0)->type != AST_RANGE) { if (!must_succeed) @@ -5268,7 +5268,7 @@ bool AstNode::replace_variables(std::map &varia offset -= variables.at(str).offset; if (variables.at(str).range_swapped) offset = -offset; - std::vector &var_bits = variables.at(str).val.bits; + std::vector &var_bits = variables.at(str).val.bits(); std::vector new_bits(var_bits.begin() + offset, var_bits.begin() + offset + width); AstNode *newNode = mkconst_bits(new_bits, variables.at(str).is_signed); newNode->cloneInto(this); @@ -5399,7 +5399,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) } if (stmt->children.at(0)->children.empty()) { - variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size()); + variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.size()); } else { AstNode *range = stmt->children.at(0)->children.at(0); if (!range->range_valid) { @@ -5410,12 +5410,12 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) int offset = min(range->range_left, range->range_right); int width = std::abs(range->range_left - range->range_right) + 1; varinfo_t &v = variables[stmt->children.at(0)->str]; - RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size()); + RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.size()); for (int i = 0; i < width; i++) { int index = i + offset - v.offset; if (v.range_swapped) index = -index; - v.val.bits.at(index) = r.bits.at(i); + v.val.bits().at(index) = r.bits().at(i); } } @@ -5558,7 +5558,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) log_abort(); } - result = AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed); + result = AstNode::mkconst_bits(variables.at(str).val.bits(), variables.at(str).is_signed); finished: delete block; diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 731656866..f6b894563 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -149,7 +149,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (buffer[0] == '.') { if (lutptr) { - for (auto &bit : lutptr->bits) + for (auto &bit : lutptr->bits()) if (bit == RTLIL::State::Sx) bit = lut_default_state; lutptr = NULL; @@ -321,9 +321,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool const_v = Const(str); } else { int n = strlen(v); - const_v.bits.resize(n); + const_v.bits().resize(n); for (int i = 0; i < n; i++) - const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0; + const_v.bits()[i] = v[n-i-1] != '0' ? State::S1 : State::S0; } if (!strcmp(cmd, ".attr")) { if (obj_attributes == nullptr) { @@ -566,16 +566,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool for (int i = 0; i < input_len; i++) switch (input[i]) { case '0': - sopcell->parameters[ID::TABLE].bits.push_back(State::S1); - sopcell->parameters[ID::TABLE].bits.push_back(State::S0); + sopcell->parameters[ID::TABLE].bits().push_back(State::S1); + sopcell->parameters[ID::TABLE].bits().push_back(State::S0); break; case '1': - sopcell->parameters[ID::TABLE].bits.push_back(State::S0); - sopcell->parameters[ID::TABLE].bits.push_back(State::S1); + sopcell->parameters[ID::TABLE].bits().push_back(State::S0); + sopcell->parameters[ID::TABLE].bits().push_back(State::S1); break; default: - sopcell->parameters[ID::TABLE].bits.push_back(State::S0); - sopcell->parameters[ID::TABLE].bits.push_back(State::S0); + sopcell->parameters[ID::TABLE].bits().push_back(State::S0); + sopcell->parameters[ID::TABLE].bits().push_back(State::S0); break; } @@ -605,7 +605,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto try_next_value; } } - lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1; + lutptr->bits().at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1; try_next_value:; } diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y index 7d99b2c42..cd5382124 100644 --- a/frontends/rtlil/rtlil_parser.y +++ b/frontends/rtlil/rtlil_parser.y @@ -437,7 +437,7 @@ constant: bits.pop_back(); $$ = new RTLIL::Const; for (auto it = bits.begin(); it != bits.end(); it++) - $$->bits.push_back(*it); + $$->bits().push_back(*it); free($1); } | TOK_INT { diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 56e94489c..6a79c95aa 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -237,19 +237,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj) RTLIL::Const mkconst_str(const std::string &str) { - RTLIL::Const val; - std::vector data; - data.reserve(str.size() * 8); - for (size_t i = 0; i < str.size(); i++) { - unsigned char ch = str[str.size() - i - 1]; - for (int j = 0; j < 8; j++) { - data.push_back((ch & 1) ? State::S1 : State::S0); - ch = ch >> 1; - } - } - val.bits = data; - val.flags |= RTLIL::CONST_FLAG_STRING; - return val; + return RTLIL::Const(str); } static const RTLIL::Const extract_vhdl_boolean(std::string &val) @@ -1742,9 +1730,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (init_nets.count(net)) { if (init_nets.at(net) == '0') - initval.bits.at(bitidx) = State::S0; + initval.bits().at(bitidx) = State::S0; if (init_nets.at(net) == '1') - initval.bits.at(bitidx) = State::S1; + initval.bits().at(bitidx) = State::S1; initval_valid = true; init_nets.erase(net); } @@ -1818,12 +1806,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma initval = bit.wire->attributes.at(ID::init); while (GetSize(initval) < GetSize(bit.wire)) - initval.bits.push_back(State::Sx); + initval.bits().push_back(State::Sx); if (it.second == '0') - initval.bits.at(bit.offset) = State::S0; + initval.bits().at(bit.offset) = State::S0; if (it.second == '1') - initval.bits.at(bit.offset) = State::S1; + initval.bits().at(bit.offset) = State::S1; bit.wire->attributes[ID::init] = initval; } @@ -2010,7 +1998,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } Const qx_init = Const(State::S1, width); - qx_init.bits.resize(2 * width, State::S0); + qx_init.bits().resize(2 * width, State::S0); clocking.addDff(new_verific_id(inst), sig_dx, sig_qx, qx_init); module->addXnor(new_verific_id(inst), sig_dx, sig_qx, sig_ox); diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 7a8eb39f9..c1ceac14c 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -80,7 +80,7 @@ struct BitPatternPool bits_t sig2bits(RTLIL::SigSpec sig) { bits_t bits; - bits.bitdata = sig.as_const().bits; + bits.bitdata = sig.as_const().bits(); for (auto &b : bits.bitdata) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; diff --git a/kernel/calc.cc b/kernel/calc.cc index 9b02a6e30..77d8d78c9 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -30,13 +30,13 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed) { RTLIL::State padding = RTLIL::State::S0; - if (arg.bits.size() > 0 && is_signed) - padding = arg.bits.back(); + if (arg.size() > 0 && is_signed) + padding = arg.bits().back(); - while (int(arg.bits.size()) < width) - arg.bits.push_back(padding); + while (int(arg.size()) < width) + arg.bits().push_back(padding); - arg.bits.resize(width); + arg.bits().resize(width); } static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos) @@ -45,17 +45,17 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_ BigInteger::Sign sign = BigInteger::positive; State inv_sign_bit = RTLIL::State::S1; - size_t num_bits = val.bits.size(); + size_t num_bits = val.size(); - if (as_signed && num_bits && val.bits[num_bits-1] == RTLIL::State::S1) { + if (as_signed && num_bits && val.bits()[num_bits-1] == RTLIL::State::S1) { inv_sign_bit = RTLIL::State::S0; sign = BigInteger::negative; num_bits--; } for (size_t i = 0; i < num_bits; i++) - if (val.bits[i] == RTLIL::State::S0 || val.bits[i] == RTLIL::State::S1) - mag.setBit(i, val.bits[i] == inv_sign_bit); + if (val.bits()[i] == RTLIL::State::S0 || val.bits()[i] == RTLIL::State::S1) + mag.setBit(i, val.bits()[i] == inv_sign_bit); else if (undef_bit_pos < 0) undef_bit_pos = i; @@ -79,19 +79,19 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b { mag--; for (int i = 0; i < result_len; i++) - result.bits[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1; + result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1; } else { for (int i = 0; i < result_len; i++) - result.bits[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0; + result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0; } } #if 0 if (undef_bit_pos >= 0) for (int i = undef_bit_pos; i < result_len; i++) - result.bits[i] = RTLIL::State::Sx; + result.bits()[i] = RTLIL::State::Sx; #endif return result; @@ -132,19 +132,19 @@ static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b) RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) { if (result_len < 0) - result_len = arg1.bits.size(); + result_len = arg1.size(); RTLIL::Const arg1_ext = arg1; extend_u0(arg1_ext, result_len, signed1); RTLIL::Const result(RTLIL::State::Sx, result_len); for (size_t i = 0; i < size_t(result_len); i++) { - if (i >= arg1_ext.bits.size()) - result.bits[i] = RTLIL::State::S0; - else if (arg1_ext.bits[i] == RTLIL::State::S0) - result.bits[i] = RTLIL::State::S1; - else if (arg1_ext.bits[i] == RTLIL::State::S1) - result.bits[i] = RTLIL::State::S0; + if (i >= arg1_ext.size()) + result.bits()[i] = RTLIL::State::S0; + else if (arg1_ext.bits()[i] == RTLIL::State::S0) + result.bits()[i] = RTLIL::State::S1; + else if (arg1_ext.bits()[i] == RTLIL::State::S1) + result.bits()[i] = RTLIL::State::S0; } return result; @@ -154,16 +154,16 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL: RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1) { if (result_len < 0) - result_len = max(arg1.bits.size(), arg2.bits.size()); + result_len = max(arg1.size(), arg2.size()); extend_u0(arg1, result_len, signed1); extend_u0(arg2, result_len, signed2); RTLIL::Const result(RTLIL::State::Sx, result_len); for (size_t i = 0; i < size_t(result_len); i++) { - RTLIL::State a = i < arg1.bits.size() ? arg1.bits[i] : RTLIL::State::S0; - RTLIL::State b = i < arg2.bits.size() ? arg2.bits[i] : RTLIL::State::S0; - result.bits[i] = logic_func(a, b); + RTLIL::State a = i < arg1.size() ? arg1.bits()[i] : RTLIL::State::S0; + RTLIL::State b = i < arg2.size() ? arg2.bits()[i] : RTLIL::State::S0; + result.bits()[i] = logic_func(a, b); } return result; @@ -193,12 +193,12 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log { RTLIL::State temp = initial; - for (size_t i = 0; i < arg1.bits.size(); i++) - temp = logic_func(temp, arg1.bits[i]); + for (size_t i = 0; i < arg1.size(); i++) + temp = logic_func(temp, arg1.bits()[i]); RTLIL::Const result(temp); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -220,11 +220,11 @@ RTLIL::Const RTLIL::const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Cons RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len) { RTLIL::Const buffer = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len); - if (!buffer.bits.empty()) { - if (buffer.bits.front() == RTLIL::State::S0) - buffer.bits.front() = RTLIL::State::S1; - else if (buffer.bits.front() == RTLIL::State::S1) - buffer.bits.front() = RTLIL::State::S0; + if (!buffer.bits().empty()) { + if (buffer.bits().front() == RTLIL::State::S0) + buffer.bits().front() = RTLIL::State::S1; + else if (buffer.bits().front() == RTLIL::State::S1) + buffer.bits().front() = RTLIL::State::S0; } return buffer; } @@ -240,8 +240,8 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const BigInteger a = const2big(arg1, signed1, undef_bit_pos_a); RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -255,8 +255,8 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::Const result(logic_and(bit_a, bit_b)); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -270,8 +270,8 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::Const result(logic_or(bit_a, bit_b)); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -286,7 +286,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co BigInteger offset = const2big(arg2, signed2, undef_bit_pos) * direction; if (result_len < 0) - result_len = arg1.bits.size(); + result_len = arg1.size(); RTLIL::Const result(RTLIL::State::Sx, result_len); if (undef_bit_pos >= 0) @@ -295,11 +295,11 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co for (int i = 0; i < result_len; i++) { BigInteger pos = BigInteger(i) + offset; if (pos < 0) - result.bits[i] = vacant_bits; - else if (pos >= BigInteger(int(arg1.bits.size()))) - result.bits[i] = sign_ext ? arg1.bits.back() : vacant_bits; + result.bits()[i] = vacant_bits; + else if (pos >= BigInteger(int(arg1.size()))) + result.bits()[i] = sign_ext ? arg1.bits().back() : vacant_bits; else - result.bits[i] = arg1.bits[pos.toInt()]; + result.bits()[i] = arg1.bits()[pos.toInt()]; } return result; @@ -347,8 +347,8 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -358,8 +358,8 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -369,31 +369,31 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, RTLIL::Const arg2_ext = arg2; RTLIL::Const result(RTLIL::State::S0, result_len); - int width = max(arg1_ext.bits.size(), arg2_ext.bits.size()); + int width = max(arg1_ext.size(), arg2_ext.size()); extend_u0(arg1_ext, width, signed1 && signed2); extend_u0(arg2_ext, width, signed1 && signed2); RTLIL::State matched_status = RTLIL::State::S1; - for (size_t i = 0; i < arg1_ext.bits.size(); i++) { - if (arg1_ext.bits.at(i) == RTLIL::State::S0 && arg2_ext.bits.at(i) == RTLIL::State::S1) + for (size_t i = 0; i < arg1_ext.size(); i++) { + if (arg1_ext.bits().at(i) == RTLIL::State::S0 && arg2_ext.bits().at(i) == RTLIL::State::S1) return result; - if (arg1_ext.bits.at(i) == RTLIL::State::S1 && arg2_ext.bits.at(i) == RTLIL::State::S0) + if (arg1_ext.bits().at(i) == RTLIL::State::S1 && arg2_ext.bits().at(i) == RTLIL::State::S0) return result; - if (arg1_ext.bits.at(i) > RTLIL::State::S1 || arg2_ext.bits.at(i) > RTLIL::State::S1) + if (arg1_ext.bits().at(i) > RTLIL::State::S1 || arg2_ext.bits().at(i) > RTLIL::State::S1) matched_status = RTLIL::State::Sx; } - result.bits.front() = matched_status; + result.bits().front() = matched_status; return result; } RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { RTLIL::Const result = RTLIL::const_eq(arg1, arg2, signed1, signed2, result_len); - if (result.bits.front() == RTLIL::State::S0) - result.bits.front() = RTLIL::State::S1; - else if (result.bits.front() == RTLIL::State::S1) - result.bits.front() = RTLIL::State::S0; + if (result.bits().front() == RTLIL::State::S0) + result.bits().front() = RTLIL::State::S1; + else if (result.bits().front() == RTLIL::State::S1) + result.bits().front() = RTLIL::State::S0; return result; } @@ -403,26 +403,26 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2 RTLIL::Const arg2_ext = arg2; RTLIL::Const result(RTLIL::State::S0, result_len); - int width = max(arg1_ext.bits.size(), arg2_ext.bits.size()); + int width = max(arg1_ext.size(), arg2_ext.size()); extend_u0(arg1_ext, width, signed1 && signed2); extend_u0(arg2_ext, width, signed1 && signed2); - for (size_t i = 0; i < arg1_ext.bits.size(); i++) { - if (arg1_ext.bits.at(i) != arg2_ext.bits.at(i)) + for (size_t i = 0; i < arg1_ext.size(); i++) { + if (arg1_ext.bits().at(i) != arg2_ext.bits().at(i)) return result; } - result.bits.front() = RTLIL::State::S1; + result.bits().front() = RTLIL::State::S1; return result; } RTLIL::Const RTLIL::const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { RTLIL::Const result = RTLIL::const_eqx(arg1, arg2, signed1, signed2, result_len); - if (result.bits.front() == RTLIL::State::S0) - result.bits.front() = RTLIL::State::S1; - else if (result.bits.front() == RTLIL::State::S1) - result.bits.front() = RTLIL::State::S0; + if (result.bits().front() == RTLIL::State::S0) + result.bits().front() = RTLIL::State::S1; + else if (result.bits().front() == RTLIL::State::S1) + result.bits().front() = RTLIL::State::S0; return result; } @@ -432,8 +432,8 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -443,8 +443,8 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - while (int(result.bits.size()) < result_len) - result.bits.push_back(RTLIL::State::S0); + while (int(result.size()) < result_len) + result.bits().push_back(RTLIL::State::S0); return result; } @@ -452,21 +452,21 @@ RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2 { int undef_bit_pos = -1; BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos); - return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos); + return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos); } RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { int undef_bit_pos = -1; BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos); - return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos); + return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos); } RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { int undef_bit_pos = -1; BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos); - return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } // truncating division @@ -480,7 +480,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2 bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative); a = a.getSign() == BigInteger::negative ? -a : a; b = b.getSign() == BigInteger::negative ? -b : b; - return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } // truncating modulo @@ -494,7 +494,7 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2 bool result_neg = a.getSign() == BigInteger::negative; a = a.getSign() == BigInteger::negative ? -a : a; b = b.getSign() == BigInteger::negative ? -b : b; - return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) @@ -516,7 +516,7 @@ RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const // bigint division with negative numbers is wonky, make sure we only negate at the very end result = -((a + b - 1) / b); } - return big2const(result, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(result, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) @@ -539,7 +539,7 @@ RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const } else { modulo = b_sign == BigInteger::negative ? truncated - b : truncated + b; } - return big2const(modulo, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(modulo, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) @@ -590,7 +590,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2 y *= -1; } - return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0)); + return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); } RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) @@ -634,18 +634,18 @@ RTLIL::Const RTLIL::const_pmux(const RTLIL::Const &arg1, const RTLIL::Const &arg for (int i = 0; i < arg3.size(); i++) if (arg3[i] == State::S1) - return RTLIL::Const(std::vector(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size())); + return RTLIL::Const(std::vector(arg2.bits().begin() + i*arg1.size(), arg2.bits().begin() + (i+1)*arg1.size())); log_abort(); // unreachable } RTLIL::Const RTLIL::const_bmux(const RTLIL::Const &arg1, const RTLIL::Const &arg2) { - std::vector t = arg1.bits; + std::vector t = arg1.bits(); for (int i = GetSize(arg2)-1; i >= 0; i--) { - RTLIL::State sel = arg2.bits.at(i); + RTLIL::State sel = arg2.bits().at(i); std::vector new_t; if (sel == State::S0) new_t = std::vector(t.begin(), t.begin() + GetSize(t)/2); @@ -681,10 +681,10 @@ RTLIL::Const RTLIL::const_demux(const RTLIL::Const &arg1, const RTLIL::Const &ar res.push_back(State::S0); } else if (x) { for (int j = 0; j < width; j++) - res.push_back(arg1.bits[j] == State::S0 ? State::S0 : State::Sx); + res.push_back(arg1.bits()[j] == State::S0 ? State::S0 : State::Sx); } else { for (int j = 0; j < width; j++) - res.push_back(arg1.bits[j]); + res.push_back(arg1.bits()[j]); } } return res; diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 5dda4503f..5335e4198 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -274,7 +274,10 @@ Aig::Aig(Cell *cell) name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); } else { mkname_last = name; - name += stringf(":%d", p.second.as_int()); + if (p.second.flags & RTLIL::CONST_FLAG_STRING_COMPACT) + name += ":" + p.second.decode_string(); + else + name += stringf(":%d", p.second.as_int()); } mkname_a_signed = false; diff --git a/kernel/celltypes.h b/kernel/celltypes.h index fde6624e1..5e69c8435 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -325,7 +325,7 @@ struct CellTypes static RTLIL::Const eval_not(RTLIL::Const v) { - for (auto &bit : v.bits) + for (auto &bit : v.bits()) if (bit == State::S0) bit = State::S1; else if (bit == State::S1) bit = State::S0; return v; @@ -419,13 +419,13 @@ struct CellTypes RTLIL::Const ret; int width = cell->parameters.at(ID::Y_WIDTH).as_int(); int offset = cell->parameters.at(ID::OFFSET).as_int(); - ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width); + ret.bits().insert(ret.bits().end(), arg1.bits().begin()+offset, arg1.bits().begin()+offset+width); return ret; } if (cell->type == ID($concat)) { RTLIL::Const ret = arg1; - ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end()); + ret.bits().insert(ret.bits().end(), arg2.bits().begin(), arg2.bits().end()); return ret; } @@ -448,7 +448,7 @@ struct CellTypes { int width = cell->parameters.at(ID::WIDTH).as_int(); - std::vector t = cell->parameters.at(ID::LUT).bits; + std::vector t = cell->parameters.at(ID::LUT).bits(); while (GetSize(t) < (1 << width)) t.push_back(State::S0); t.resize(1 << width); @@ -460,7 +460,7 @@ struct CellTypes { int width = cell->parameters.at(ID::WIDTH).as_int(); int depth = cell->parameters.at(ID::DEPTH).as_int(); - std::vector t = cell->parameters.at(ID::TABLE).bits; + std::vector t = cell->parameters.at(ID::TABLE).bits(); while (GetSize(t) < width*depth*2) t.push_back(State::S0); @@ -473,7 +473,7 @@ struct CellTypes bool match_x = true; for (int j = 0; j < width; j++) { - RTLIL::State a = arg1.bits.at(j); + RTLIL::State a = arg1.bits().at(j); if (t.at(2*width*i + 2*j + 0) == State::S1) { if (a == State::S1) match_x = false; if (a != State::S0) match = false; @@ -513,7 +513,7 @@ struct CellTypes if (cell->type == ID($_OAI3_)) return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1)); - log_assert(arg3.bits.size() == 0); + log_assert(arg3.size() == 0); return eval(cell, arg1, arg2, errp); } @@ -524,7 +524,7 @@ struct CellTypes if (cell->type == ID($_OAI4_)) return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1)); - log_assert(arg4.bits.size() == 0); + log_assert(arg4.size() == 0); return eval(cell, arg1, arg2, arg3, errp); } }; diff --git a/kernel/consteval.h b/kernel/consteval.h index 4c0c26049..5265c3b0b 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -76,7 +76,7 @@ struct ConstEval #ifndef NDEBUG RTLIL::SigSpec current_val = values_map(sig); for (int i = 0; i < GetSize(current_val); i++) - log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]); + log_assert(current_val[i].wire != NULL || current_val[i] == value.bits()[i]); #endif values_map.add(sig, RTLIL::SigSpec(value)); } @@ -115,7 +115,7 @@ struct ConstEval for (int i = 0; i < GetSize(coval); i++) { carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry); - coval.bits[i] = carry ? State::S1 : State::S0; + coval.bits()[i] = carry ? State::S1 : State::S0; } set(sig_co, coval); @@ -153,7 +153,7 @@ struct ConstEval for (int i = 0; i < sig_s.size(); i++) { - RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0); + RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits().at(0); RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size()); if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1) @@ -180,10 +180,10 @@ struct ConstEval if (y_values.size() > 1) { - std::vector master_bits = y_values.at(0).bits; + std::vector master_bits = y_values.at(0).bits(); for (size_t i = 1; i < y_values.size(); i++) { - std::vector &slave_bits = y_values.at(i).bits; + std::vector &slave_bits = y_values.at(i).bits(); log_assert(master_bits.size() == slave_bits.size()); for (size_t j = 0; j < master_bits.size(); j++) if (master_bits[j] != slave_bits[j]) @@ -248,8 +248,8 @@ struct ConstEval RTLIL::Const val_x = const_or(t2, t3, false, false, width); for (int i = 0; i < GetSize(val_y); i++) - if (val_y.bits[i] == RTLIL::Sx) - val_x.bits[i] = RTLIL::Sx; + if (val_y.bits()[i] == RTLIL::Sx) + val_x.bits()[i] = RTLIL::Sx; set(sig_y, val_y); set(sig_x, val_x); diff --git a/kernel/ff.cc b/kernel/ff.cc index 697ba7342..a8afb6e59 100644 --- a/kernel/ff.cc +++ b/kernel/ff.cc @@ -298,11 +298,11 @@ FfData FfData::slice(const std::vector &bits) { res.sig_set.append(sig_set[i]); } if (has_arst) - res.val_arst.bits.push_back(val_arst[i]); + res.val_arst.bits().push_back(val_arst[i]); if (has_srst) - res.val_srst.bits.push_back(val_srst[i]); + res.val_srst.bits().push_back(val_srst[i]); if (initvals) - res.val_init.bits.push_back(val_init[i]); + res.val_init.bits().push_back(val_init[i]); } res.width = GetSize(res.sig_q); return res; @@ -760,7 +760,7 @@ void FfData::flip_bits(const pool &bits) { Const mask = Const(State::S0, width); for (auto bit: bits) - mask.bits[bit] = State::S1; + mask.bits()[bit] = State::S1; if (has_clk || has_gclk) sig_d = module->Xor(NEW_ID, sig_d, mask); diff --git a/kernel/ffinit.h b/kernel/ffinit.h index 9d33ac572..6b580f302 100644 --- a/kernel/ffinit.h +++ b/kernel/ffinit.h @@ -76,7 +76,7 @@ struct FfInitVals { RTLIL::Const res; for (auto bit : sig) - res.bits.push_back((*this)(bit)); + res.bits().push_back((*this)(bit)); return res; } diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index c65108413..3b361c1c2 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -42,9 +42,9 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, poolgetPort(ID::B); - std::vector config_bits = cell->getParam(ID::CONFIG).bits; + std::vector config_bits = cell->getParam(ID::CONFIG).bits(); int config_cursor = 0; int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int(); @@ -199,7 +199,7 @@ struct Macc bool eval(RTLIL::Const &result) const { - for (auto &bit : result.bits) + for (auto &bit : result.bits()) bit = State::S0; for (auto &port : ports) diff --git a/kernel/mem.cc b/kernel/mem.cc index 01c866770..1d87f6b96 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -157,10 +157,10 @@ void Mem::emit() { } for (int sub = 0; sub < (1 << port.wide_log2); sub++) { - rd_wide_continuation.bits.push_back(State(sub != 0)); - rd_clk_enable.bits.push_back(State(port.clk_enable)); - rd_clk_polarity.bits.push_back(State(port.clk_polarity)); - rd_ce_over_srst.bits.push_back(State(port.ce_over_srst)); + rd_wide_continuation.bits().push_back(State(sub != 0)); + rd_clk_enable.bits().push_back(State(port.clk_enable)); + rd_clk_polarity.bits().push_back(State(port.clk_polarity)); + rd_ce_over_srst.bits().push_back(State(port.ce_over_srst)); rd_clk.append(port.clk); rd_arst.append(port.arst); rd_srst.append(port.srst); @@ -170,17 +170,17 @@ void Mem::emit() { rd_addr.append(addr); log_assert(GetSize(addr) == abits); for (auto idx : wr_port_xlat) { - rd_transparency_mask.bits.push_back(State(bool(port.transparency_mask[idx]))); - rd_collision_x_mask.bits.push_back(State(bool(port.collision_x_mask[idx]))); + rd_transparency_mask.bits().push_back(State(bool(port.transparency_mask[idx]))); + rd_collision_x_mask.bits().push_back(State(bool(port.collision_x_mask[idx]))); } } rd_data.append(port.data); for (auto &bit : port.arst_value) - rd_arst_value.bits.push_back(bit); + rd_arst_value.bits().push_back(bit); for (auto &bit : port.srst_value) - rd_srst_value.bits.push_back(bit); + rd_srst_value.bits().push_back(bit); for (auto &bit : port.init_value) - rd_init_value.bits.push_back(bit); + rd_init_value.bits().push_back(bit); } if (rd_ports.empty()) { rd_wide_continuation = State::S0; @@ -222,12 +222,12 @@ void Mem::emit() { } for (int sub = 0; sub < (1 << port.wide_log2); sub++) { - wr_wide_continuation.bits.push_back(State(sub != 0)); - wr_clk_enable.bits.push_back(State(port.clk_enable)); - wr_clk_polarity.bits.push_back(State(port.clk_polarity)); + wr_wide_continuation.bits().push_back(State(sub != 0)); + wr_clk_enable.bits().push_back(State(port.clk_enable)); + wr_clk_polarity.bits().push_back(State(port.clk_polarity)); wr_clk.append(port.clk); for (auto idx : wr_port_xlat) - wr_priority_mask.bits.push_back(State(bool(port.priority_mask[idx]))); + wr_priority_mask.bits().push_back(State(bool(port.priority_mask[idx]))); SigSpec addr = port.sub_addr(sub); addr.extend_u0(abits, false); wr_addr.append(addr); @@ -427,7 +427,7 @@ void Mem::coalesce_inits() { log_assert(offset + GetSize(init.data) <= GetSize(cdata)); for (int i = 0; i < GetSize(init.data); i++) if (init.en[i % width] == State::S1) - cdata.bits[i+offset] = init.data.bits[i]; + cdata.bits()[i+offset] = init.data.bits()[i]; init.removed = true; } MemInit new_init; @@ -446,7 +446,7 @@ Const Mem::get_init_data() const { int offset = (init.addr.as_int() - start_offset) * width; for (int i = 0; i < GetSize(init.data); i++) if (0 <= i+offset && i+offset < GetSize(init_data) && init.en[i % width] == State::S1) - init_data.bits[i+offset] = init.data.bits[i]; + init_data.bits()[i+offset] = init.data.bits()[i]; } return init_data; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d3946a620..47cde8d3d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -202,23 +202,16 @@ const pool &RTLIL::builtin_ff_cell_types() { RTLIL::Const::Const(const std::string &str) { - flags = RTLIL::CONST_FLAG_STRING; - bits.reserve(str.size() * 8); - for (int i = str.size()-1; i >= 0; i--) { - unsigned char ch = str[i]; - for (int j = 0; j < 8; j++) { - bits.push_back((ch & 1) != 0 ? State::S1 : State::S0); - ch = ch >> 1; - } - } + flags = RTLIL::CONST_FLAG_STRING | CONST_FLAG_STRING_COMPACT; + this->str = str; } RTLIL::Const::Const(int val, int width) { flags = RTLIL::CONST_FLAG_NONE; - bits.reserve(width); + bits_.reserve(width); for (int i = 0; i < width; i++) { - bits.push_back((val & 1) != 0 ? State::S1 : State::S0); + bits_.push_back((val & 1) != 0 ? State::S1 : State::S0); val = val >> 1; } } @@ -226,65 +219,115 @@ RTLIL::Const::Const(int val, int width) RTLIL::Const::Const(RTLIL::State bit, int width) { flags = RTLIL::CONST_FLAG_NONE; - bits.reserve(width); + bits_.reserve(width); for (int i = 0; i < width; i++) - bits.push_back(bit); + bits_.push_back(bit); } RTLIL::Const::Const(const std::vector &bits) { flags = RTLIL::CONST_FLAG_NONE; - this->bits.reserve(bits.size()); + this->bits_.reserve(bits.size()); for (const auto &b : bits) - this->bits.emplace_back(b ? State::S1 : State::S0); + this->bits_.emplace_back(b ? State::S1 : State::S0); } bool RTLIL::Const::operator <(const RTLIL::Const &other) const { - if (bits.size() != other.bits.size()) - return bits.size() < other.bits.size(); - for (size_t i = 0; i < bits.size(); i++) - if (bits[i] != other.bits[i]) - return bits[i] < other.bits[i]; + if ((flags & CONST_FLAG_STRING_COMPACT) != (other.flags & CONST_FLAG_STRING_COMPACT)) + return decode_string() < other.decode_string(); + + if (flags & CONST_FLAG_STRING_COMPACT) + return str < other.str; + + if (bits_.size() != other.bits_.size()) + return bits_.size() < other.bits_.size(); + for (size_t i = 0; i < bits_.size(); i++) + if (bits_[i] != other.bits_[i]) + return bits_[i] < other.bits_[i]; return false; } bool RTLIL::Const::operator ==(const RTLIL::Const &other) const { - return bits == other.bits; + if ((flags & CONST_FLAG_STRING_COMPACT) != (other.flags & CONST_FLAG_STRING_COMPACT)) + return decode_string() == other.decode_string(); + + if (flags & CONST_FLAG_STRING_COMPACT) + return str == other.str; + return bits_ == other.bits_; } bool RTLIL::Const::operator !=(const RTLIL::Const &other) const { - return bits != other.bits; + if ((flags & CONST_FLAG_STRING_COMPACT) != (other.flags & CONST_FLAG_STRING_COMPACT)) + return decode_string() != other.decode_string(); + + if (flags & CONST_FLAG_STRING_COMPACT) + return str != other.str; + return bits_ != other.bits_; +} + +std::vector& RTLIL::Const::bits() +{ + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); + return bits_; +} + +const std::vector& RTLIL::Const::bits() const +{ + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); + return bits_; +} + + +std::vector RTLIL::Const::to_bits() const +{ + if (!(flags & CONST_FLAG_STRING_COMPACT)) { + return bits_; + } + + std::vector b; + b.reserve(str.size() * 8); + for (int i = str.size()-1; i >= 0; i--) { + unsigned char ch = str[i]; + for (int j = 0; j < 8; j++) { + b.push_back((ch & 1) != 0 ? State::S1 : State::S0); + ch = ch >> 1; + } + } + return b; } bool RTLIL::Const::as_bool() const { - for (size_t i = 0; i < bits.size(); i++) - if (bits[i] == State::S1) + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); + for (size_t i = 0; i < bits_.size(); i++) + if (bits_[i] == State::S1) return true; return false; } int RTLIL::Const::as_int(bool is_signed) const { + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); int32_t ret = 0; - for (size_t i = 0; i < bits.size() && i < 32; i++) - if (bits[i] == State::S1) + for (size_t i = 0; i < bits_.size() && i < 32; i++) + if (bits_[i] == State::S1) ret |= 1 << i; - if (is_signed && bits.back() == State::S1) - for (size_t i = bits.size(); i < 32; i++) + if (is_signed && bits_.back() == State::S1) + for (size_t i = bits_.size(); i < 32; i++) ret |= 1 << i; return ret; } std::string RTLIL::Const::as_string() const { + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); std::string ret; - ret.reserve(bits.size()); - for (size_t i = bits.size(); i > 0; i--) - switch (bits[i-1]) { + ret.reserve(bits_.size()); + for (size_t i = bits_.size(); i > 0; i--) + switch (bits_[i-1]) { case S0: ret += "0"; break; case S1: ret += "1"; break; case Sx: ret += "x"; break; @@ -298,22 +341,25 @@ std::string RTLIL::Const::as_string() const RTLIL::Const RTLIL::Const::from_string(const std::string &str) { Const c; - c.bits.reserve(str.size()); + c.bits_.reserve(str.size()); for (auto it = str.rbegin(); it != str.rend(); it++) switch (*it) { - case '0': c.bits.push_back(State::S0); break; - case '1': c.bits.push_back(State::S1); break; - case 'x': c.bits.push_back(State::Sx); break; - case 'z': c.bits.push_back(State::Sz); break; - case 'm': c.bits.push_back(State::Sm); break; - default: c.bits.push_back(State::Sa); + case '0': c.bits_.push_back(State::S0); break; + case '1': c.bits_.push_back(State::S1); break; + case 'x': c.bits_.push_back(State::Sx); break; + case 'z': c.bits_.push_back(State::Sz); break; + case 'm': c.bits_.push_back(State::Sm); break; + default: c.bits_.push_back(State::Sa); } return c; } std::string RTLIL::Const::decode_string() const { - const int n = GetSize(bits); + if (flags & CONST_FLAG_STRING_COMPACT) + return str; + + const int n = GetSize(bits_); const int n_over_8 = n / 8; std::string s; s.reserve(n_over_8); @@ -321,7 +367,7 @@ std::string RTLIL::Const::decode_string() const if (i < n) { char ch = 0; for (int j = 0; j < (n - i); j++) { - if (bits[i + j] == RTLIL::State::S1) { + if (bits_[i + j] == RTLIL::State::S1) { ch |= 1 << j; } } @@ -332,7 +378,7 @@ std::string RTLIL::Const::decode_string() const for (; i >= 0; i -= 8) { char ch = 0; for (int j = 0; j < 8; j++) { - if (bits[i + j] == RTLIL::State::S1) { + if (bits_[i + j] == RTLIL::State::S1) { ch |= 1 << j; } } @@ -344,9 +390,10 @@ std::string RTLIL::Const::decode_string() const bool RTLIL::Const::is_fully_zero() const { + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); cover("kernel.rtlil.const.is_fully_zero"); - for (const auto &bit : bits) + for (const auto &bit : bits_) if (bit != RTLIL::State::S0) return false; @@ -355,9 +402,10 @@ bool RTLIL::Const::is_fully_zero() const bool RTLIL::Const::is_fully_ones() const { + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); cover("kernel.rtlil.const.is_fully_ones"); - for (const auto &bit : bits) + for (const auto &bit : bits_) if (bit != RTLIL::State::S1) return false; @@ -368,7 +416,10 @@ bool RTLIL::Const::is_fully_def() const { cover("kernel.rtlil.const.is_fully_def"); - for (const auto &bit : bits) + if (flags & CONST_FLAG_STRING_COMPACT) + return true; + + for (const auto &bit : bits_) if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1) return false; @@ -379,7 +430,10 @@ bool RTLIL::Const::is_fully_undef() const { cover("kernel.rtlil.const.is_fully_undef"); - for (const auto &bit : bits) + if (flags & CONST_FLAG_STRING_COMPACT) + return false; + + for (const auto &bit : bits_) if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz) return false; @@ -390,7 +444,10 @@ bool RTLIL::Const::is_fully_undef_x_only() const { cover("kernel.rtlil.const.is_fully_undef_x_only"); - for (const auto &bit : bits) + if (flags & CONST_FLAG_STRING_COMPACT) + return false; + + for (const auto &bit : bits_) if (bit != RTLIL::State::Sx) return false; @@ -401,9 +458,12 @@ bool RTLIL::Const::is_onehot(int *pos) const { cover("kernel.rtlil.const.is_onehot"); + if (flags & CONST_FLAG_STRING_COMPACT) + return false; + bool found = false; for (int i = 0; i < GetSize(*this); i++) { - auto &bit = bits[i]; + auto &bit = bits_[i]; if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1) return false; if (bit == RTLIL::State::S1) { @@ -1034,6 +1094,14 @@ namespace { cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str()); } + void is_param(const RTLIL::IdString& name) + { + auto it = cell->parameters.find(name); + if (it == cell->parameters.end()) + error(__LINE__); + expected_params.insert(name); + } + int param(const RTLIL::IdString& name) { auto it = cell->parameters.find(name); @@ -1063,14 +1131,14 @@ namespace { void param_bits(const RTLIL::IdString& name, int width) { - param(name); - if (GetSize(cell->parameters.at(name).bits) != width) + is_param(name); + if (GetSize(cell->parameters.at(name).bits()) != width) error(__LINE__); } std::string param_string(const RTLIL::IdString &name) { - param(name); + is_param(name); return cell->parameters.at(name).decode_string(); } @@ -1212,8 +1280,8 @@ namespace { } if (cell->type == ID($macc)) { - param(ID::CONFIG); - param(ID::CONFIG_WIDTH); + is_param(ID::CONFIG); + is_param(ID::CONFIG_WIDTH); port(ID::A, param(ID::A_WIDTH)); port(ID::B, param(ID::B_WIDTH)); port(ID::Y, param(ID::Y_WIDTH)); @@ -1241,7 +1309,7 @@ namespace { } if (cell->type == ID($slice)) { - param(ID::OFFSET); + is_param(ID::OFFSET); port(ID::A, param(ID::A_WIDTH)); port(ID::Y, param(ID::Y_WIDTH)); if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH)) @@ -1293,7 +1361,7 @@ namespace { } if (cell->type == ID($lut)) { - param(ID::LUT); + is_param(ID::LUT); port(ID::A, param(ID::WIDTH)); port(ID::Y, 1); check_expected(); @@ -1301,8 +1369,8 @@ namespace { } if (cell->type == ID($sop)) { - param(ID::DEPTH); - param(ID::TABLE); + is_param(ID::DEPTH); + is_param(ID::TABLE); port(ID::A, param(ID::WIDTH)); port(ID::Y, 1); check_expected(); @@ -1487,15 +1555,15 @@ namespace { } if (cell->type == ID($fsm)) { - param(ID::NAME); + is_param(ID::NAME); param_bool(ID::CLK_POLARITY); param_bool(ID::ARST_POLARITY); - param(ID::STATE_BITS); - param(ID::STATE_NUM); - param(ID::STATE_NUM_LOG2); - param(ID::STATE_RST); + is_param(ID::STATE_BITS); + is_param(ID::STATE_NUM); + is_param(ID::STATE_NUM_LOG2); + is_param(ID::STATE_RST); param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM)); - param(ID::TRANS_NUM); + is_param(ID::TRANS_NUM); param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH))); port(ID::CLK, 1); port(ID::ARST, 1); @@ -1506,7 +1574,7 @@ namespace { } if (cell->type == ID($memrd)) { - param(ID::MEMID); + is_param(ID::MEMID); param_bool(ID::CLK_ENABLE); param_bool(ID::CLK_POLARITY); param_bool(ID::TRANSPARENT); @@ -1519,11 +1587,11 @@ namespace { } if (cell->type == ID($memrd_v2)) { - param(ID::MEMID); + is_param(ID::MEMID); param_bool(ID::CLK_ENABLE); param_bool(ID::CLK_POLARITY); - param(ID::TRANSPARENCY_MASK); - param(ID::COLLISION_X_MASK); + is_param(ID::TRANSPARENCY_MASK); + is_param(ID::COLLISION_X_MASK); param_bool(ID::CE_OVER_SRST); param_bits(ID::ARST_VALUE, param(ID::WIDTH)); param_bits(ID::SRST_VALUE, param(ID::WIDTH)); @@ -1539,10 +1607,10 @@ namespace { } if (cell->type == ID($memwr)) { - param(ID::MEMID); + is_param(ID::MEMID); param_bool(ID::CLK_ENABLE); param_bool(ID::CLK_POLARITY); - param(ID::PRIORITY); + is_param(ID::PRIORITY); port(ID::CLK, 1); port(ID::EN, param(ID::WIDTH)); port(ID::ADDR, param(ID::ABITS)); @@ -1552,11 +1620,11 @@ namespace { } if (cell->type == ID($memwr_v2)) { - param(ID::MEMID); + is_param(ID::MEMID); param_bool(ID::CLK_ENABLE); param_bool(ID::CLK_POLARITY); - param(ID::PORTID); - param(ID::PRIORITY_MASK); + is_param(ID::PORTID); + is_param(ID::PRIORITY_MASK); port(ID::CLK, 1); port(ID::EN, param(ID::WIDTH)); port(ID::ADDR, param(ID::ABITS)); @@ -1566,8 +1634,8 @@ namespace { } if (cell->type == ID($meminit)) { - param(ID::MEMID); - param(ID::PRIORITY); + is_param(ID::MEMID); + is_param(ID::PRIORITY); port(ID::ADDR, param(ID::ABITS)); port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS)); check_expected(); @@ -1575,8 +1643,8 @@ namespace { } if (cell->type == ID($meminit_v2)) { - param(ID::MEMID); - param(ID::PRIORITY); + is_param(ID::MEMID); + is_param(ID::PRIORITY); port(ID::ADDR, param(ID::ABITS)); port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS)); port(ID::EN, param(ID::WIDTH)); @@ -1585,10 +1653,10 @@ namespace { } if (cell->type == ID($mem)) { - param(ID::MEMID); - param(ID::SIZE); - param(ID::OFFSET); - param(ID::INIT); + is_param(ID::MEMID); + is_param(ID::SIZE); + is_param(ID::OFFSET); + is_param(ID::INIT); param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS))); param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS))); param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS))); @@ -1607,10 +1675,10 @@ namespace { } if (cell->type == ID($mem_v2)) { - param(ID::MEMID); - param(ID::SIZE); - param(ID::OFFSET); - param(ID::INIT); + is_param(ID::MEMID); + is_param(ID::SIZE); + is_param(ID::OFFSET); + is_param(ID::INIT); param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS))); param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS))); param_bits(ID::RD_TRANSPARENCY_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS))); @@ -1701,12 +1769,12 @@ namespace { param_bool(ID::FULL); param_bool(ID::SRC_DST_PEN); param_bool(ID::SRC_DST_POL); - param(ID::T_RISE_MIN); - param(ID::T_RISE_TYP); - param(ID::T_RISE_MAX); - param(ID::T_FALL_MIN); - param(ID::T_FALL_TYP); - param(ID::T_FALL_MAX); + is_param(ID::T_RISE_MIN); + is_param(ID::T_RISE_TYP); + is_param(ID::T_RISE_MAX); + is_param(ID::T_FALL_MIN); + is_param(ID::T_FALL_TYP); + is_param(ID::T_FALL_MAX); port(ID::EN, 1); port(ID::SRC, param(ID::SRC_WIDTH)); port(ID::DST, param(ID::DST_WIDTH)); @@ -1722,17 +1790,17 @@ namespace { } if (cell->type == ID($specrule)) { - param(ID::TYPE); + is_param(ID::TYPE); param_bool(ID::SRC_PEN); param_bool(ID::SRC_POL); param_bool(ID::DST_PEN); param_bool(ID::DST_POL); - param(ID::T_LIMIT_MIN); - param(ID::T_LIMIT_TYP); - param(ID::T_LIMIT_MAX); - param(ID::T_LIMIT2_MIN); - param(ID::T_LIMIT2_TYP); - param(ID::T_LIMIT2_MAX); + is_param(ID::T_LIMIT_MIN); + is_param(ID::T_LIMIT_TYP); + is_param(ID::T_LIMIT_MAX); + is_param(ID::T_LIMIT2_MIN); + is_param(ID::T_LIMIT2_TYP); + is_param(ID::T_LIMIT2_MAX); port(ID::SRC_EN, 1); port(ID::DST_EN, 1); port(ID::SRC, param(ID::SRC_WIDTH)); @@ -1742,10 +1810,10 @@ namespace { } if (cell->type == ID($print)) { - param(ID(FORMAT)); + is_param(ID(FORMAT)); param_bool(ID::TRG_ENABLE); - param(ID::TRG_POLARITY); - param(ID::PRIORITY); + is_param(ID::TRG_POLARITY); + is_param(ID::PRIORITY); port(ID::EN, 1); port(ID::TRG, param(ID::TRG_WIDTH)); port(ID::ARGS, param(ID::ARGS_WIDTH)); @@ -1757,10 +1825,10 @@ namespace { std::string flavor = param_string(ID(FLAVOR)); if (!(flavor == "assert" || flavor == "assume" || flavor == "live" || flavor == "fair" || flavor == "cover")) error(__LINE__); - param(ID(FORMAT)); + is_param(ID(FORMAT)); param_bool(ID::TRG_ENABLE); - param(ID::TRG_POLARITY); - param(ID::PRIORITY); + is_param(ID::TRG_POLARITY); + is_param(ID::PRIORITY); port(ID::A, 1); port(ID::EN, 1); port(ID::TRG, param(ID::TRG_WIDTH)); @@ -1770,7 +1838,7 @@ namespace { } if (cell->type == ID($scopeinfo)) { - param(ID::TYPE); + is_param(ID::TYPE); check_expected(); std::string scope_type = cell->getParam(ID::TYPE).decode_string(); if (scope_type != "module" && scope_type != "struct") @@ -1875,8 +1943,8 @@ namespace { { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } if (cell->type.in(ID($set_tag))) { - param(ID::WIDTH); - param(ID::TAG); + is_param(ID::WIDTH); + is_param(ID::TAG); port(ID::A, param(ID::WIDTH)); port(ID::SET, param(ID::WIDTH)); port(ID::CLR, param(ID::WIDTH)); @@ -1885,16 +1953,16 @@ namespace { return; } if (cell->type.in(ID($get_tag),ID($original_tag))) { - param(ID::WIDTH); - param(ID::TAG); + is_param(ID::WIDTH); + is_param(ID::TAG); port(ID::A, param(ID::WIDTH)); port(ID::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type.in(ID($overwrite_tag))) { - param(ID::WIDTH); - param(ID::TAG); + is_param(ID::WIDTH); + is_param(ID::TAG); port(ID::A, param(ID::WIDTH)); port(ID::SET, param(ID::WIDTH)); port(ID::CLR, param(ID::WIDTH)); @@ -1902,7 +1970,7 @@ namespace { return; } if (cell->type.in(ID($future_ff))) { - param(ID::WIDTH); + is_param(ID::WIDTH); port(ID::A, param(ID::WIDTH)); port(ID::Y, param(ID::WIDTH)); check_expected(); @@ -3730,7 +3798,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit) wire = bit.wire; offset = 0; if (wire == NULL) - data = RTLIL::Const(bit.data).bits; + data = RTLIL::Const(bit.data).bits(); else offset = bit.offset; width = 1; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f9da29495..02cc2c799 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -50,8 +50,9 @@ namespace RTLIL enum ConstFlags : unsigned char { CONST_FLAG_NONE = 0, CONST_FLAG_STRING = 1, - CONST_FLAG_SIGNED = 2, // only used for parameters - CONST_FLAG_REAL = 4 // only used for parameters + CONST_FLAG_STRING_COMPACT = 2, // internally efficient string storage + CONST_FLAG_SIGNED = 4, // only used for parameters + CONST_FLAG_REAL = 8, // only used for parameters }; struct Const; @@ -657,14 +658,18 @@ namespace RTLIL struct RTLIL::Const { + private: + // TODO unionize + std::vector bits_; + std::string str; // active on CONST_FLAG_STRING_COMPACT + public: int flags; - std::vector bits; Const() : flags(RTLIL::CONST_FLAG_NONE) {} Const(const std::string &str); Const(int val, int width = 32); Const(RTLIL::State bit, int width = 1); - Const(const std::vector &bits) : bits(bits) { flags = CONST_FLAG_NONE; } + Const(const std::vector &bits) : bits_(bits) { flags = CONST_FLAG_NONE; } Const(const std::vector &bits); Const(const RTLIL::Const &c) = default; RTLIL::Const &operator =(const RTLIL::Const &other) = default; @@ -673,19 +678,22 @@ struct RTLIL::Const bool operator ==(const RTLIL::Const &other) const; bool operator !=(const RTLIL::Const &other) const; + const std::vector& bits() const; + std::vector& bits(); bool as_bool() const; int as_int(bool is_signed = false) const; std::string as_string() const; static Const from_string(const std::string &str); + std::vector to_bits() const; std::string decode_string() const; - - inline int size() const { return bits.size(); } - inline bool empty() const { return bits.empty(); } - inline RTLIL::State &operator[](int index) { return bits.at(index); } - inline const RTLIL::State &operator[](int index) const { return bits.at(index); } - inline decltype(bits)::iterator begin() { return bits.begin(); } - inline decltype(bits)::iterator end() { return bits.end(); } + // (flags & CONST_FLAG_STRING_COMPACT) ? : ; + inline size_t size() const { return (flags & CONST_FLAG_STRING_COMPACT) ? 8 * str.size() : bits_.size(); } + inline bool empty() const { return (flags & CONST_FLAG_STRING_COMPACT) ? str.empty() : bits_.empty(); } + inline RTLIL::State &operator[](int index) { log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); return bits_.at(index); } + inline const RTLIL::State &operator[](int index) const { log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); return bits_.at(index); } + inline decltype(bits_)::iterator begin() { log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); return bits_.begin(); } + inline decltype(bits_)::iterator end() { log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); return bits_.end(); } bool is_fully_zero() const; bool is_fully_ones() const; @@ -695,25 +703,34 @@ struct RTLIL::Const bool is_onehot(int *pos = nullptr) const; inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); RTLIL::Const ret; - ret.bits.reserve(len); + ret.bits_.reserve(len); for (int i = offset; i < offset + len; i++) - ret.bits.push_back(i < GetSize(bits) ? bits[i] : padding); + ret.bits_.push_back(i < GetSize(bits_) ? bits_[i] : padding); return ret; } void extu(int width) { - bits.resize(width, RTLIL::State::S0); + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); + bits_.resize(width, RTLIL::State::S0); } void exts(int width) { - bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back()); + log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); + bits_.resize(width, bits_.empty() ? RTLIL::State::Sx : bits_.back()); } inline unsigned int hash() const { unsigned int h = mkhash_init; - for (auto b : bits) - h = mkhash(h, b); + + if(flags & CONST_FLAG_STRING_COMPACT) { + for (auto c : str) + h = mkhash(h, c); + } else { + for (auto b : bits_) + h = mkhash(h, b); + } return h; } }; @@ -759,8 +776,8 @@ struct RTLIL::SigChunk int width, offset; SigChunk() : wire(nullptr), width(0), offset(0) {} - SigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {} - SigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {} + SigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {} + SigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {} SigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {} SigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {} SigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {} diff --git a/kernel/satgen.cc b/kernel/satgen.cc index baaf22d1f..de2200176 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -922,7 +922,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector lut; - for (auto bit : cell->getParam(ID::LUT).bits) + for (auto bit : cell->getParam(ID::LUT).bits()) lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); while (GetSize(lut) < (1 << GetSize(a))) lut.push_back(ez->CONST_FALSE); @@ -974,7 +974,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) int width = cell->getParam(ID::WIDTH).as_int(); int depth = cell->getParam(ID::DEPTH).as_int(); - vector table_raw = cell->getParam(ID::TABLE).bits; + vector table_raw = cell->getParam(ID::TABLE).bits(); while (GetSize(table_raw) < 2*width*depth) table_raw.push_back(State::S0); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index efdc54b79..fca2bca67 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1126,40 +1126,31 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi design = yosys_design; if (command == "auto") { - std::string filename_trim = filename; - - auto has_extension = [](const std::string& filename, const std::string& extension) { - if (filename.size() >= extension.size()) { - return filename.compare(filename.size() - extension.size(), extension.size(), extension) == 0; - } - return false; - }; - - if (has_extension(filename_trim, ".gz")) { - filename_trim.erase(filename_trim.size() - 3); - } - - if (has_extension(filename_trim, ".v")) { - command = " -vlog2k"; - } else if (has_extension(filename_trim, ".sv")) { - command = " -sv"; - } else if (has_extension(filename_trim, ".vhd") || has_extension(filename_trim, ".vhdl")) { - command = " -vhdl"; - } else if (has_extension(filename_trim, ".blif") || has_extension(filename_trim, ".eblif")) { - command = "blif"; - } else if (has_extension(filename_trim, ".json")) { - command = "json"; - } else if (has_extension(filename_trim, ".il")) { - command = "rtlil"; - } else if (has_extension(filename_trim, ".ys")) { - command = "script"; - } else if (has_extension(filename_trim, ".tcl")) { - command = "tcl"; - } else if (filename == "-") { - command = "script"; - } else { - log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str()); - } + std::string filename_trim = filename; + if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".gz") == 0) + filename_trim.erase(filename_trim.size()-3); + if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-2, std::string::npos, ".v") == 0) + command = " -vlog2k"; + else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0) + command = " -sv"; + else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0) + command = " -vhdl"; + else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0) + command = "blif"; + else if (filename_trim.size() > 5 && filename_trim.compare(filename_trim.size()-6, std::string::npos, ".eblif") == 0) + command = "blif"; + else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0) + command = "json"; + else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0) + command = "rtlil"; + else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0) + command = "script"; + else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0) + command = "tcl"; + else if (filename == "-") + command = "script"; + else + log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str()); } if (command == "script") diff --git a/kernel/yw.cc b/kernel/yw.cc index ef043fb0d..f36212c7f 100644 --- a/kernel/yw.cc +++ b/kernel/yw.cc @@ -185,7 +185,7 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const const std::string &bits = steps[t].bits; RTLIL::Const result(State::Sa, width); - result.bits.reserve(width); + result.bits().reserve(width); int read_begin = GetSize(bits) - 1 - bits_offset; int read_end = max(-1, read_begin - width); @@ -200,7 +200,7 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const default: log_abort(); } - result.bits[j] = bit; + result.bits()[j] = bit; } return result; diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index c398afffa..da06acedf 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -354,7 +354,7 @@ struct BugpointPass : public Pass { for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) { auto &mask = it2->priority_mask; if (GetSize(mask) > i) { - mask.bits.erase(mask.bits.begin() + i); + mask.bits().erase(mask.bits().begin() + i); } } return design_copy; diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc index bac6b1521..dde5f1567 100644 --- a/passes/cmds/clean_zerowidth.cc +++ b/passes/cmds/clean_zerowidth.cc @@ -160,7 +160,7 @@ struct CleanZeroWidthPass : public Pass { memwr.address = State::S0; Const priority_mask; for (auto x : swizzle) { - priority_mask.bits.push_back(memwr.priority_mask.bits[x]); + priority_mask.bits().push_back(memwr.priority_mask.bits()[x]); } memwr.priority_mask = priority_mask; swizzle.push_back(i); diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 2b2340dab..6756ab4cd 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -883,7 +883,7 @@ struct DftTagWorker { { if (sig_a.is_fully_const()) { auto const_val = sig_a.as_const(); - for (auto &bit : const_val.bits) + for (auto &bit : const_val.bits()) bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit; return const_val; } diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index 7973ac262..241d4e67b 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -40,12 +40,12 @@ struct PrintAttrsPass : public Pass { } static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) { - if (x.flags == RTLIL::CONST_FLAG_STRING) + if (x.flags & RTLIL::CONST_FLAG_STRING) log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str()); else if (x.flags == RTLIL::CONST_FLAG_NONE) log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str()); else - log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail + log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail } void execute(std::vector args, RTLIL::Design *design) override diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 7293002f3..29f5bb98d 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -243,7 +243,9 @@ struct SetundefPass : public Pass { { for (auto *cell : module->selected_cells()) { for (auto ¶meter : cell->parameters) { - for (auto &bit : parameter.second.bits) { + if (parameter.second.flags & RTLIL::CONST_FLAG_STRING) + continue; + for (auto &bit : parameter.second.bits()) { if (bit > RTLIL::State::S1) bit = worker.next_bit(); } @@ -390,7 +392,7 @@ struct SetundefPass : public Pass { for (auto wire : initwires) { Const &initval = wire->attributes[ID::init]; - initval.bits.resize(GetSize(wire), State::Sx); + initval.bits().resize(GetSize(wire), State::Sx); for (int i = 0; i < GetSize(wire); i++) { SigBit bit = sigmap(SigBit(wire, i)); @@ -421,7 +423,7 @@ struct SetundefPass : public Pass { continue; Const &initval = wire->attributes[ID::init]; - initval.bits.resize(GetSize(wire), State::Sx); + initval.bits().resize(GetSize(wire), State::Sx); if (initval.is_fully_undef()) { wire->attributes.erase(ID::init); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 927cefca3..b256db690 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -77,7 +77,7 @@ struct SplitnetsWorker if (it != wire->attributes.end()) { Const old_init = it->second, new_init; for (int i = offset; i < offset+width; i++) - new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx); + new_init.bits().push_back(i < GetSize(old_init) ? old_init.bits().at(i) : State::Sx); new_wire->attributes.emplace(ID::init, new_init); } diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 62a9d309e..fcadf240f 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -168,10 +168,10 @@ undef_bit_in_next_state: ctrl_in_bit_indices[ctrl_in[i]] = i; for (auto &it : ctrl_in_bit_indices) - if (tr.ctrl_in.bits.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0) + if (tr.ctrl_in.bits().at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0) for (auto &dc_bit : exclusive_ctrls.at(it.first)) if (ctrl_in_bit_indices.count(dc_bit)) - tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa; + tr.ctrl_in.bits().at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa; RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits); if (state_in >= 0) diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index df31dbb7a..e9d9fc800 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -30,11 +30,11 @@ PRIVATE_NAMESPACE_BEGIN static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern) { - log_assert(GetSize(super_pattern.bits) == GetSize(sub_pattern.bits)); - for (int i = 0; i < GetSize(super_pattern.bits); i++) - if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) { - if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) { - if (super_pattern.bits[i] != sub_pattern.bits[i]) + log_assert(GetSize(super_pattern.bits()) == GetSize(sub_pattern.bits())); + for (int i = 0; i < GetSize(super_pattern.bits()); i++) + if (sub_pattern.bits()[i] == RTLIL::State::S0 || sub_pattern.bits()[i] == RTLIL::State::S1) { + if (super_pattern.bits()[i] == RTLIL::State::S0 || super_pattern.bits()[i] == RTLIL::State::S1) { + if (super_pattern.bits()[i] != sub_pattern.bits()[i]) return false; } else return false; @@ -54,10 +54,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::maptype = ID($adff); state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY]; state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state]; - for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits) + for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits()) if (bit != RTLIL::State::S1) bit = RTLIL::State::S0; state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST)); @@ -198,10 +198,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) RTLIL::Const state = fsm_data.state_table[i]; RTLIL::SigSpec sig_a, sig_b; - for (size_t j = 0; j < state.bits.size(); j++) - if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) { + for (size_t j = 0; j < state.size(); j++) + if (state.bits()[j] == RTLIL::State::S0 || state.bits()[j] == RTLIL::State::S1) { sig_a.append(RTLIL::SigSpec(state_wire, j)); - sig_b.append(RTLIL::SigSpec(state.bits[j])); + sig_b.append(RTLIL::SigSpec(state.bits()[j])); } if (sig_b == RTLIL::SigSpec(RTLIL::State::S1)) @@ -261,8 +261,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) for (size_t i = 0; i < fsm_data.state_table.size(); i++) { RTLIL::Const state = fsm_data.state_table[i]; int bit_idx = -1; - for (size_t j = 0; j < state.bits.size(); j++) - if (state.bits[j] == RTLIL::State::S1) + for (size_t j = 0; j < state.size(); j++) + if (state.bits()[j] == RTLIL::State::S1) bit_idx = j; if (bit_idx >= 0) next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i)); @@ -306,7 +306,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) fullstate_cache.insert(j); for (auto &tr : fsm_data.transition_table) { - if (tr.ctrl_out.bits[i] == RTLIL::State::S1) + if (tr.ctrl_out.bits()[i] == RTLIL::State::S1) pattern_cache[tr.ctrl_in].insert(tr.state_in); else fullstate_cache.erase(tr.state_in); diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index f2eb06760..c07c2fe77 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -106,11 +106,11 @@ struct FsmOpt for (int i = 0; i < ctrl_in.size(); i++) { RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1); if (ctrl_bit.is_fully_const()) { - if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit) + if (tr.ctrl_in.bits()[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits()[i]) != ctrl_bit) goto delete_this_transition; continue; } - if (tr.ctrl_in.bits[i] <= RTLIL::State::S1) + if (tr.ctrl_in.bits()[i] <= RTLIL::State::S1) ctrl_in_used[i] = true; } new_transition_table.push_back(tr); @@ -169,8 +169,8 @@ struct FsmOpt for (auto tr : fsm_data.transition_table) { - RTLIL::State &si = tr.ctrl_in.bits[i]; - RTLIL::State &sj = tr.ctrl_in.bits[j]; + RTLIL::State &si = tr.ctrl_in.bits()[i]; + RTLIL::State &sj = tr.ctrl_in.bits()[j]; if (si > RTLIL::State::S1) si = sj; @@ -207,8 +207,8 @@ struct FsmOpt for (auto tr : fsm_data.transition_table) { - RTLIL::State &si = tr.ctrl_in.bits[i]; - RTLIL::State &sj = tr.ctrl_out.bits[j]; + RTLIL::State &si = tr.ctrl_in.bits()[i]; + RTLIL::State &sj = tr.ctrl_out.bits()[j]; if (si > RTLIL::State::S1 || si == sj) { RTLIL::SigSpec tmp(tr.ctrl_in); @@ -232,22 +232,22 @@ struct FsmOpt for (auto &pattern : set) { - if (pattern.bits[bit] > RTLIL::State::S1) { + if (pattern.bits()[bit] > RTLIL::State::S1) { new_set.insert(pattern); continue; } RTLIL::Const other_pattern = pattern; - if (pattern.bits[bit] == RTLIL::State::S1) - other_pattern.bits[bit] = RTLIL::State::S0; + if (pattern.bits()[bit] == RTLIL::State::S1) + other_pattern.bits()[bit] = RTLIL::State::S0; else - other_pattern.bits[bit] = RTLIL::State::S1; + other_pattern.bits()[bit] = RTLIL::State::S1; if (set.count(other_pattern) > 0) { log(" Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern), tr.state_in, tr.state_out, log_signal(tr.ctrl_out)); - other_pattern.bits[bit] = RTLIL::State::Sa; + other_pattern.bits()[bit] = RTLIL::State::Sa; new_set.insert(other_pattern); did_something = true; continue; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 3dc29b5a0..ce8e825c2 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -43,8 +43,8 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & fprintf(f, "set_fsm_encoding {"); for (int i = 0; i < GetSize(fsm_data.state_table); i++) { fprintf(f, " s%d=2#", i); - for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--) - fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0'); + for (int j = GetSize(fsm_data.state_table[i].bits())-1; j >= 0; j--) + fprintf(f, "%c", fsm_data.state_table[i].bits()[j] == RTLIL::State::S1 ? '1' : '0'); } fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(), @@ -105,7 +105,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs if (encoding == "one-hot") { new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits); - new_code.bits[state_idx] = RTLIL::State::S1; + new_code.bits()[state_idx] = RTLIL::State::S1; } else if (encoding == "binary") { new_code = RTLIL::Const(state_idx, fsm_data.state_bits); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 97371efab..e24047a16 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -48,8 +48,8 @@ struct FsmData cell->parameters[ID::STATE_TABLE] = RTLIL::Const(); for (int i = 0; i < int(state_table.size()); i++) { - std::vector &bits_table = cell->parameters[ID::STATE_TABLE].bits; - std::vector &bits_state = state_table[i].bits; + std::vector &bits_table = cell->parameters[ID::STATE_TABLE].bits(); + std::vector &bits_state = state_table[i].bits(); bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end()); } @@ -57,16 +57,16 @@ struct FsmData cell->parameters[ID::TRANS_TABLE] = RTLIL::Const(); for (int i = 0; i < int(transition_table.size()); i++) { - std::vector &bits_table = cell->parameters[ID::TRANS_TABLE].bits; + std::vector &bits_table = cell->parameters[ID::TRANS_TABLE].bits(); transition_t &tr = transition_table[i]; RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2); RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2); - std::vector &bits_state_in = const_state_in.bits; - std::vector &bits_state_out = const_state_out.bits; + std::vector &bits_state_in = const_state_in.bits(); + std::vector &bits_state_out = const_state_out.bits(); - std::vector &bits_ctrl_in = tr.ctrl_in.bits; - std::vector &bits_ctrl_out = tr.ctrl_out.bits; + std::vector &bits_ctrl_in = tr.ctrl_in.bits(); + std::vector &bits_ctrl_out = tr.ctrl_out.bits(); // append lsb first bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end()); @@ -97,23 +97,23 @@ struct FsmData for (int i = 0; i < state_num; i++) { RTLIL::Const state_code; int off_begin = i*state_bits, off_end = off_begin + state_bits; - state_code.bits.insert(state_code.bits.begin(), state_table.bits.begin()+off_begin, state_table.bits.begin()+off_end); + state_code.bits().insert(state_code.bits().begin(), state_table.bits().begin()+off_begin, state_table.bits().begin()+off_end); this->state_table.push_back(state_code); } for (int i = 0; i < trans_num; i++) { - auto off_ctrl_out = trans_table.bits.begin() + i*(num_inputs+num_outputs+2*state_num_log2); + auto off_ctrl_out = trans_table.bits().begin() + i*(num_inputs+num_outputs+2*state_num_log2); auto off_state_out = off_ctrl_out + num_outputs; auto off_ctrl_in = off_state_out + state_num_log2; auto off_state_in = off_ctrl_in + num_inputs; auto off_end = off_state_in + state_num_log2; RTLIL::Const state_in, state_out, ctrl_in, ctrl_out; - ctrl_out.bits.insert(state_in.bits.begin(), off_ctrl_out, off_state_out); - state_out.bits.insert(state_out.bits.begin(), off_state_out, off_ctrl_in); - ctrl_in.bits.insert(ctrl_in.bits.begin(), off_ctrl_in, off_state_in); - state_in.bits.insert(state_in.bits.begin(), off_state_in, off_end); + ctrl_out.bits().insert(state_in.bits().begin(), off_ctrl_out, off_state_out); + state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in); + ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in); + state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end); transition_t tr; tr.state_in = state_in.as_int(); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 8476d392c..bf0566572 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -279,7 +279,7 @@ struct SubmodWorker for (auto cell : module->cells()) { - if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].bits.size() == 0) { + if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].size() == 0) { cell->attributes.erase(ID::submod); continue; } diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 77a4eb81b..122f09324 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -533,6 +533,7 @@ void MemMapping::determine_style() { find_attr = search_for_attribute(mem, attr); if (find_attr.first) { Const val = find_attr.second; + log(">>>%s<<<\n", log_const(val)); if (val == 1) { kind = RamKind::NotLogic; log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", log_id(attr), log_id(mem.module->name), log_id(mem.memid)); @@ -1019,7 +1020,7 @@ void MemMapping::handle_priority() { } bool is_all_zero(const Const &val) { - for (auto bit: val.bits) + for (auto bit: val.bits()) if (bit == State::S1) return false; return true; @@ -1913,7 +1914,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons if (!bit.valid) { hw_val.push_back(State::Sx); } else { - hw_val.push_back(val.bits[bit.bit]); + hw_val.push_back(val.bits()[bit.bit]); } } if (pdef.rdinitval == ResetValKind::NoUndef) @@ -1926,7 +1927,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons if (!bit.valid) { hw_val.push_back(State::Sx); } else { - hw_val.push_back(rport.arst_value.bits[bit.bit]); + hw_val.push_back(rport.arst_value.bits()[bit.bit]); } } if (pdef.rdarstval == ResetValKind::NoUndef) @@ -1939,7 +1940,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons if (!bit.valid) { hw_val.push_back(State::Sx); } else { - hw_val.push_back(rport.srst_value.bits[bit.bit]); + hw_val.push_back(rport.srst_value.bits()[bit.bit]); } } if (pdef.rdsrstval == ResetValKind::NoUndef) @@ -2103,7 +2104,7 @@ void MemMapping::emit(const MemConfig &cfg) { if (hwa & 1 << i) addr += 1 << hw_addr_swizzle[i]; if (addr >= mem.start_offset && addr < mem.start_offset + mem.size) - initval.push_back(init_data.bits[(addr - mem.start_offset) * mem.width + bit.bit]); + initval.push_back(init_data.bits()[(addr - mem.start_offset) * mem.width + bit.bit]); else initval.push_back(State::Sx); } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index ba39b9c80..684512d14 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -393,8 +393,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos RTLIL::Const &val = it2->second; SigSpec sig = assign_map(wire); for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++) - if (val.bits[i] != State::Sx) - init_bits[sig[i]] = val.bits[i]; + if (val.bits()[i] != State::Sx) + init_bits[sig[i]] = val.bits()[i]; wire->attributes.erase(it2); } } @@ -406,7 +406,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos for (int i = 0; i < wire->width; i++) { auto it = init_bits.find(RTLIL::SigBit(wire, i)); if (it != init_bits.end()) { - val.bits[i] = it->second; + val.bits()[i] = it->second; found = true; } } @@ -425,7 +425,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (wire->attributes.count(ID::init)) initval = wire->attributes.at(ID::init); if (GetSize(initval) != GetSize(wire)) - initval.bits.resize(GetSize(wire), State::Sx); + initval.bits().resize(GetSize(wire), State::Sx); if (initval.is_fully_undef()) wire->attributes.erase(ID::init); diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index b77be4515..8539432c0 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -361,9 +361,9 @@ struct OptDffWorker bool failed = false; for (int i = 0; i < ff.width; i++) { if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral) - val_arst.bits.push_back(State::S0); + val_arst.bits().push_back(State::S0); else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral) - val_arst.bits.push_back(State::S1); + val_arst.bits().push_back(State::S1); else failed = true; } @@ -626,7 +626,7 @@ struct OptDffWorker groups[resets].push_back(i); } else remaining_indices.push_back(i); - val_srst.bits.push_back(reset_val); + val_srst.bits().push_back(reset_val); } for (auto &it : groups) { @@ -634,7 +634,7 @@ struct OptDffWorker new_ff.val_srst = Const(); for (int i = 0; i < new_ff.width; i++) { int j = it.second[i]; - new_ff.val_srst.bits.push_back(val_srst[j]); + new_ff.val_srst.bits().push_back(val_srst[j]); } ctrl_t srst = combine_resets(it.first, ff.is_fine); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index ae5a980b1..cd63356e1 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -31,6 +31,10 @@ PRIVATE_NAMESPACE_BEGIN bool did_something; +void did_something_hook() { + did_something = true; +} + void replace_undriven(RTLIL::Module *module, const CellTypes &ct) { SigMap sigmap(module); @@ -89,7 +93,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct) log_debug("Setting undriven signal in %s to constant: %s = %s\n", log_id(module), log_signal(sig), log_signal(val)); module->connect(sig, val); - did_something = true; + did_something_hook(); } if (!revisit_initwires.empty()) @@ -106,11 +110,11 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct) if (initval.is_fully_undef()) { log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire)); wire->attributes.erase(ID::init); - did_something = true; + did_something_hook(); } else if (initval != wire->attributes.at(ID::init)) { log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval)); wire->attributes[ID::init] = initval; - did_something = true; + did_something_hook(); } } } @@ -129,7 +133,7 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, assign_map.add(Y, out_val); module->connect(Y, out_val); module->remove(cell); - did_something = true; + did_something_hook(); } bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap, bool keepdc) @@ -300,7 +304,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ cover_list("opt.opt_expr.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str()); module->remove(cell); - did_something = true; + did_something_hook(); return true; } @@ -351,21 +355,21 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative) bool all_bits_one = true; bool last_bit_one = true; - if (GetSize(value.bits) < 1) + if (GetSize(value.bits()) < 1) return false; - if (GetSize(value.bits) == 1) { - if (value.bits[0] != State::S1) + if (GetSize(value.bits()) == 1) { + if (value.bits()[0] != State::S1) return false; if (is_signed) is_negative = true; return true; } - for (int i = 0; i < GetSize(value.bits); i++) { - if (value.bits[i] != State::S1) + for (int i = 0; i < GetSize(value.bits()); i++) { + if (value.bits()[i] != State::S1) all_bits_one = false; - if (value.bits[i] != (i ? State::S0 : State::S1)) + if (value.bits()[i] != (i ? State::S0 : State::S1)) last_bit_one = false; } @@ -645,7 +649,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n", log_id(cell->type), log_id(cell->name), log_id(module)); cell->type = ID($not); - did_something = true; + did_something_hook(); } else { cover("opt.opt_expr.unary_buffer"); replace_cell(assign_map, module, cell, "unary_buffer", ID::Y, cell->getPort(ID::A)); @@ -729,7 +733,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons assign_map.add(y_group_x, y_new_x); module->connect(y_group_x, y_new_x); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -757,7 +761,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons assign_map.add(y_group_1, b_group_1); module->connect(y_group_1, b_group_1); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } else if (sig_a.is_fully_def() || sig_b.is_fully_def()) @@ -790,7 +794,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons module->connect(y_group_1, y_new_1); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -820,7 +824,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a)); cell->setPort(ID::A, new_sig_a); cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a); - did_something = true; + did_something_hook(); } } @@ -843,7 +847,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b)); cell->setPort(ID::B, new_sig_b); cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b); - did_something = true; + did_something_hook(); } } @@ -869,7 +873,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort(ID::A, sig_a = new_a); cell->parameters.at(ID::A_WIDTH) = 1; - did_something = true; + did_something_hook(); } } @@ -895,7 +899,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort(ID::A, sig_a = new_a); cell->parameters.at(ID::A_WIDTH) = 1; - did_something = true; + did_something_hook(); } } @@ -921,7 +925,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->setPort(ID::B, sig_b = new_b); cell->parameters.at(ID::B_WIDTH) = 1; - did_something = true; + did_something_hook(); } } @@ -963,7 +967,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->setPort(ID::B, new_b); cell->setPort(ID::Y, sig_y.extract_end(i)); cell->fixup_parameters(); - did_something = true; + did_something_hook(); } } @@ -1022,7 +1026,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->setPort(ID::Y, sig_y.extract_end(i)); cell->setPort(ID::CO, sig_co.extract_end(i)); cell->fixup_parameters(); - did_something = true; + did_something_hook(); } } } @@ -1074,7 +1078,7 @@ skip_fine_alu: sig_a.remove(width, GetSize(sig_a)-width); cell->setPort(ID::A, sig_a); cell->setParam(ID::A_WIDTH, width); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -1093,7 +1097,7 @@ skip_fine_alu: cell->setPort(ID::A, cell->getPort(ID::B)); cell->setPort(ID::B, tmp); cell->setPort(ID::S, invert_map.at(assign_map(cell->getPort(ID::S)))); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1201,7 +1205,7 @@ skip_fine_alu: log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); cell->setPort(ID::A, SigSpec(State::Sx, GetSize(a))); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -1279,7 +1283,7 @@ skip_fine_alu: cell->parameters.erase(ID::B_WIDTH); cell->parameters.erase(ID::B_SIGNED); cell->unsetPort(ID::B); - did_something = true; + did_something_hook(); } goto next_cell; } @@ -1300,7 +1304,7 @@ skip_fine_alu: cell->unsetPort(ID::B); cell->unsetParam(ID::B_SIGNED); cell->unsetParam(ID::B_WIDTH); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1334,7 +1338,7 @@ skip_fine_alu: module->connect(cell->getPort(ID::Y), sig_y); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1445,7 +1449,7 @@ skip_fine_alu: cell->parameters.erase(ID::B_SIGNED); cell->check(); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -1474,7 +1478,7 @@ skip_identity: cell->type = ID($not); } else cell->type = ID($_NOT_); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1494,7 +1498,7 @@ skip_identity: cell->type = ID($and); } else cell->type = ID($_AND_); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1514,7 +1518,7 @@ skip_identity: cell->type = ID($or); } else cell->type = ID($_OR_); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1565,7 +1569,7 @@ skip_identity: cell->type = ID($mux); cell->parameters.erase(ID::S_WIDTH); } - did_something = true; + did_something_hook(); } } @@ -1712,7 +1716,7 @@ skip_identity: module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1741,7 +1745,7 @@ skip_identity: cell->setPort(ID::B, new_b); cell->check(); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -1766,7 +1770,7 @@ skip_identity: module->connect(sig_y, RTLIL::SigSpec(0, GetSize(sig_y))); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1783,7 +1787,7 @@ skip_identity: module->connect(RTLIL::SigSig(sig_y.extract(0, y_zeros), RTLIL::SigSpec(0, y_zeros))); cell->check(); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -1808,7 +1812,7 @@ skip_identity: module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(State::Sx, sig_y.size()))); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } @@ -1882,7 +1886,7 @@ skip_identity: } } - did_something = true; + did_something_hook(); goto next_cell; } } @@ -1976,7 +1980,7 @@ skip_identity: cover("opt.opt_expr.alu_split"); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } skip_alu_split: @@ -2037,7 +2041,7 @@ skip_alu_split: module->connect(y_sig, y_value); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } @@ -2051,7 +2055,7 @@ skip_alu_split: cell->setParam(ID::A_WIDTH, GetSize(sig_a)); cell->setParam(ID::B_WIDTH, GetSize(sig_b)); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -2187,7 +2191,7 @@ skip_alu_split: if (replace) module->connect(cell->getPort(ID::Y), replace_sig); module->remove(cell); - did_something = true; + did_something_hook(); goto next_cell; } } @@ -2212,7 +2216,7 @@ void replace_const_connections(RTLIL::Module *module) { changes.push_back({conn.first, mapped}); } if (!changes.empty()) - did_something = true; + did_something_hook(); for (auto &it : changes) cell->setPort(it.first, it.second); } diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index d982ef2d2..93ced1d3a 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -98,7 +98,7 @@ struct OptFfInvWorker Const mask = lut->getParam(ID::LUT); Const new_mask; for (int j = 0; j < (1 << GetSize(sig_a)); j++) { - new_mask.bits.push_back(mask.bits[j ^ flip_mask]); + new_mask.bits().push_back(mask.bits()[j ^ flip_mask]); } if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) { module->connect(lut->getPort(ID::Y), ff.sig_q); @@ -180,10 +180,10 @@ struct OptFfInvWorker Const mask = d_lut->getParam(ID::LUT); Const new_mask; for (int i = 0; i < GetSize(mask); i++) { - if (mask.bits[i] == State::S0) - new_mask.bits.push_back(State::S1); + if (mask.bits()[i] == State::S0) + new_mask.bits().push_back(State::S1); else - new_mask.bits.push_back(State::S0); + new_mask.bits().push_back(State::S0); } d_lut->setParam(ID::LUT, new_mask); if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) { diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index 9a2d8e6a5..bf13e6500 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -90,7 +90,7 @@ struct OptMemPass : public Pass { } for (auto &init : mem.inits) { for (int i = 0; i < GetSize(init.data); i++) { - State bit = init.data.bits[i]; + State bit = init.data.bits()[i]; int lane = i % mem.width; if (bit != State::Sx && bit != State::S0) { always_0[lane] = false; @@ -182,9 +182,9 @@ struct OptMemPass : public Pass { for (auto i: swizzle) { int bidx = sub * mem.width + i; new_data.append(port.data[bidx]); - new_init.bits.push_back(port.init_value.bits[bidx]); - new_arst.bits.push_back(port.arst_value.bits[bidx]); - new_srst.bits.push_back(port.srst_value.bits[bidx]); + new_init.bits().push_back(port.init_value.bits()[bidx]); + new_arst.bits().push_back(port.arst_value.bits()[bidx]); + new_srst.bits().push_back(port.srst_value.bits()[bidx]); } } port.data = new_data; @@ -197,11 +197,11 @@ struct OptMemPass : public Pass { Const new_en; for (int s = 0; s < GetSize(init.data); s += mem.width) { for (auto i: swizzle) { - new_data.bits.push_back(init.data.bits[s + i]); + new_data.bits().push_back(init.data.bits()[s + i]); } } for (auto i: swizzle) { - new_en.bits.push_back(init.en.bits[i]); + new_en.bits().push_back(init.en.bits()[i]); } init.data = new_data; init.en = new_en; diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index eb3aa462e..78566f9da 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -140,8 +140,13 @@ struct OptMergeWorker hash_conn_strings.push_back(s + "\n"); } - for (auto &it : cell->parameters) - hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n"); + for (auto &it : cell->parameters) { + Const c = it.second; + std::string s = "P " + it.first.str() + "="; + s += (c.flags & RTLIL::CONST_FLAG_STRING_COMPACT) ? c.decode_string() : c.as_string(); + s += "\n"; + hash_conn_strings.push_back(s); + } std::sort(hash_conn_strings.begin(), hash_conn_strings.end()); diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 90ddf8dd7..7118f276f 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -323,7 +323,7 @@ struct Pmux2ShiftxPass : public Pass { for (auto it : bits) { entry.first.append(it.first); - entry.second.bits.push_back(it.second); + entry.second.bits().push_back(it.second); } eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry; @@ -344,7 +344,7 @@ struct Pmux2ShiftxPass : public Pass { for (auto it : bits) { entry.first.append(it.first); - entry.second.bits.push_back(it.second); + entry.second.bits().push_back(it.second); } eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry; @@ -411,7 +411,7 @@ struct Pmux2ShiftxPass : public Pass { for (int i : seldb.at(sig)) { Const val = eqdb.at(S[i]).second; int onebits = 0; - for (auto b : val.bits) + for (auto b : val.bits()) if (b == State::S1) onebits++; if (onebits > 1) diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 586bd9dfe..57a0df27b 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -781,18 +781,18 @@ struct ShareWorker std::vector p_first_bits = p.first; for (int i = 0; i < GetSize(p_first_bits); i++) { RTLIL::SigBit b = p_first_bits[i]; - RTLIL::State v = p.second.bits[i]; + RTLIL::State v = p.second.bits()[i]; if (p_bits.count(b) && p_bits.at(b) != v) return false; p_bits[b] = v; } p.first = RTLIL::SigSpec(); - p.second.bits.clear(); + p.second.bits().clear(); for (auto &it : p_bits) { p.first.append(it.first); - p.second.bits.push_back(it.second); + p.second.bits().push_back(it.second); } return true; @@ -815,10 +815,10 @@ struct ShareWorker { auto otherval = val; - if (otherval.bits[i] == State::S0) - otherval.bits[i] = State::S1; - else if (otherval.bits[i] == State::S1) - otherval.bits[i] = State::S0; + if (otherval.bits()[i] == State::S0) + otherval.bits()[i] = State::S1; + else if (otherval.bits()[i] == State::S1) + otherval.bits()[i] = State::S0; else continue; @@ -828,7 +828,7 @@ struct ShareWorker newsig.remove(i); auto newval = val; - newval.bits.erase(newval.bits.begin() + i); + newval.bits().erase(newval.bits().begin() + i); db[newsig].insert(newval); db[sig].erase(otherval); @@ -907,14 +907,14 @@ struct ShareWorker if (used_in_a) for (auto p : c_patterns) { for (int i = 0; i < GetSize(sig_s); i++) - p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); + p.first.append(sig_s[i]), p.second.bits().push_back(RTLIL::State::S0); if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); } for (int idx : used_in_b_parts) for (auto p : c_patterns) { - p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); + p.first.append(sig_s[idx]), p.second.bits().push_back(RTLIL::State::S1); if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); } @@ -965,7 +965,7 @@ struct ShareWorker for (int i = 0; i < GetSize(p_first); i++) if (filter_bits.count(p_first[i]) == 0) { new_p.first.append(p_first[i]); - new_p.second.bits.push_back(p.second.bits.at(i)); + new_p.second.bits().push_back(p.second.bits().at(i)); } out.insert(new_p); diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 87a5cb56d..02678d676 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -219,10 +219,10 @@ struct WreduceWorker // Narrow ARST_VALUE parameter to new size. if (cell->parameters.count(ID::ARST_VALUE)) { - rst_value.bits.resize(GetSize(sig_q)); + rst_value.bits().resize(GetSize(sig_q)); cell->setParam(ID::ARST_VALUE, rst_value); } else if (cell->parameters.count(ID::SRST_VALUE)) { - rst_value.bits.resize(GetSize(sig_q)); + rst_value.bits().resize(GetSize(sig_q)); cell->setParam(ID::SRST_VALUE, rst_value); } diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 72b4522d8..6ca882522 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -339,11 +339,11 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (st.overflow->type == ID($ge)) { Const B = st.overflow->getPort(ID::B).as_const(); - log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1); + log_assert(std::count(B.bits().begin(), B.bits().end(), State::S1) == 1); // Since B is an exact power of 2, subtract 1 // by inverting all bits up until hitting // that one hi bit - for (auto &b : B.bits) + for (auto &b : B.bits()) if (b == State::S0) b = State::S1; else if (b == State::S1) { b = State::S0; diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 817a15a1e..596d757f4 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -363,7 +363,7 @@ match overflow select GetSize(port(overflow, \Y)) <= 48 select port(overflow, \B).is_fully_const() define B port(overflow, \B).as_const() - select std::count(B.bits.begin(), B.bits.end(), State::S1) == 1 + select std::count(B.bits().begin(), B.bits().end(), State::S1) == 1 index port(overflow, \A) === sigP optional endmatch diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 4da20c395..b4a16c06a 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -53,11 +53,11 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) Const value = valuesig.as_const(); Const &wireinit = lhs_c.wire->attributes[ID::init]; - while (GetSize(wireinit.bits) < lhs_c.wire->width) - wireinit.bits.push_back(State::Sx); + while (GetSize(wireinit.bits()) < lhs_c.wire->width) + wireinit.bits().push_back(State::Sx); for (int i = 0; i < lhs_c.width; i++) { - auto &initbit = wireinit.bits[i + lhs_c.offset]; + auto &initbit = wireinit.bits()[i + lhs_c.offset]; if (initbit != State::Sx && initbit != value[i]) log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c)); initbit = value[i]; diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc index ae6774547..7bc250ca1 100644 --- a/passes/proc/proc_rom.cc +++ b/passes/proc/proc_rom.cc @@ -100,7 +100,7 @@ struct RomWorker val[it2->second] = it.second[i].data; } } - for (auto bit: val.bits) { + for (auto bit: val.bits()) { if (bit == State::Sm) { log_debug("rejecting switch: lhs not uniform\n"); return; @@ -113,8 +113,8 @@ struct RomWorker return; } Const c = addr.as_const(); - while (GetSize(c) && c.bits.back() == State::S0) - c.bits.pop_back(); + while (GetSize(c) && c.bits().back() == State::S0) + c.bits().pop_back(); if (GetSize(c) > swsigbits) continue; if (GetSize(c) > 30) { @@ -160,11 +160,11 @@ struct RomWorker auto it = vals.find(i); if (it == vals.end()) { log_assert(got_default); - for (auto bit: default_val.bits) - init_data.bits.push_back(bit); + for (auto bit: default_val.bits()) + init_data.bits().push_back(bit); } else { - for (auto bit: it->second.bits) - init_data.bits.push_back(bit); + for (auto bit: it->second.bits()) + init_data.bits().push_back(bit); } } @@ -183,12 +183,6 @@ struct RomWorker mem.rd_ports.push_back(std::move(rd)); mem.emit(); - - if (sw->has_attribute(ID::src)) { - mem.inits[0].cell->attributes[ID::src] = sw->attributes[ID::src]; - mem.rd_ports[0].cell->attributes[ID::src] = sw->attributes[ID::src]; - } - for (auto cs: sw->cases) delete cs; sw->cases.clear(); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index acebea6c5..e95c38996 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -250,13 +250,13 @@ struct VlogHammerReporter std::string module_name = module_names[mod].c_str(); ConstEval ce(module); - std::vector bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width); + std::vector bits(patterns[idx].bits().begin(), patterns[idx].bits().begin() + total_input_width); for (int i = 0; i < int(inputs.size()); i++) { RTLIL::Wire *wire = module->wire(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { ce.set(RTLIL::SigSpec(wire, j), bits.back()); recorded_set_vars.append(RTLIL::SigSpec(wire, j)); - recorded_set_vals.bits.push_back(bits.back()); + recorded_set_vals.bits().push_back(bits.back()); bits.pop_back(); } if (module == modules.front()) { @@ -346,7 +346,7 @@ struct VlogHammerReporter log_error("Pattern %s is to short!\n", pattern.c_str()); patterns.push_back(sig.as_const()); if (invert_pattern) { - for (auto &bit : patterns.back().bits) + for (auto &bit : patterns.back().bits()) if (bit == RTLIL::State::S0) bit = RTLIL::State::S1; else if (bit == RTLIL::State::S1) @@ -557,7 +557,7 @@ struct EvalPass : public Pass { tab_line.clear(); ce.pop(); - tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.bits.size()); + tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.size()); } while (tabvals.as_bool()); diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index e7ec29ee4..96a80aab4 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -131,7 +131,7 @@ void create_dff_dq_map(std::map &map, RTLIL::Mo info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool(); std::vector sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector(); std::vector sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector(); - std::vector arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits; + std::vector arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits(); for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); info.arst_value = arst_value.at(i); diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index 0eadb69e0..c45226545 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -363,7 +363,7 @@ struct PropagateWorker for (auto wire : module->wires()) if (wire->has_attribute(ID::replaced_by_gclk)) - replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1, false); + replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].bits().at(0) == State::S1, false); for (auto cell : module->cells()) { if (cell->type.in(ID($not), ID($_NOT_))) { @@ -745,7 +745,7 @@ struct FormalFfPass : public Pass { for (auto wire : module->wires()) { if (!wire->has_attribute(ID::replaced_by_gclk)) continue; - bool clk_pol = wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1; + bool clk_pol = wire->attributes[ID::replaced_by_gclk].bits().at(0) == State::S1; found.emplace_back(SigSpec(wire), clk_pol); } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 69f81e3df..6760769ec 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -629,9 +629,9 @@ struct SatHelper bool found_undef = false; for (int i = 0; i < info.width; i++) { - value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); + value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) - value.bits.back() = RTLIL::State::Sx, found_undef = true; + value.bits().back() = RTLIL::State::Sx, found_undef = true; } if (info.timestep != last_timestep) { @@ -740,9 +740,9 @@ struct SatHelper RTLIL::Const value; for (int i = 0; i < info.width; i++) { - value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); + value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) - value.bits.back() = RTLIL::State::Sx; + value.bits().back() = RTLIL::State::Sx; } if (info.timestep != last_timestep) { @@ -754,11 +754,11 @@ struct SatHelper } if(info.width == 1) { - fprintf(f, "%c%s\n", bitvals[value.bits[0]], vcdnames[info.description].c_str()); + fprintf(f, "%c%s\n", bitvals[value.bits()[0]], vcdnames[info.description].c_str()); } else { fprintf(f, "b"); for(int k=info.width-1; k >= 0; k --) //need to flip bit ordering for VCD - fprintf(f, "%c", bitvals[value.bits[k]]); + fprintf(f, "%c", bitvals[value.bits()[k]]); fprintf(f, " %s\n", vcdnames[info.description].c_str()); } } @@ -786,9 +786,9 @@ struct SatHelper { Const value; for (int i = 0; i < info.width; i++) { - value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); + value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) - value.bits.back() = RTLIL::State::Sx; + value.bits().back() = RTLIL::State::Sx; } wavedata[info.description].first = info.width; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index aeed16b97..5af7676d2 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -134,7 +134,7 @@ void zinit(State &v) void zinit(Const &v) { - for (auto &bit : v.bits) + for (auto &bit : v.bits()) zinit(bit); } @@ -422,11 +422,11 @@ struct SimInstance for (auto bit : sigmap(sig)) if (bit.wire == nullptr) - value.bits.push_back(bit.data); + value.bits().push_back(bit.data); else if (state_nets.count(bit)) - value.bits.push_back(state_nets.at(bit)); + value.bits().push_back(state_nets.at(bit)); else - value.bits.push_back(State::Sz); + value.bits().push_back(State::Sz); if (shared->debug) log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value)); @@ -485,9 +485,9 @@ struct SimInstance int offset = (addr - state.mem->start_offset) * state.mem->width; for (int i = 0; i < GetSize(data); i++) - if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data.bits[i] != State::Sa) - if (state.data.bits[i+offset] != data.bits[i]) - dirty = true, state.data.bits[i+offset] = data.bits[i]; + if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data.bits()[i] != State::Sa) + if (state.data.bits()[i+offset] != data.bits()[i]) + dirty = true, state.data.bits()[i+offset] = data.bits()[i]; if (dirty) dirty_memories.insert(memid); @@ -498,8 +498,8 @@ struct SimInstance auto &state = mem_database[memid]; if (offset >= state.mem->size * state.mem->width) log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid)); - if (state.data.bits[offset] != data) { - state.data.bits[offset] = data; + if (state.data.bits()[offset] != data) { + state.data.bits()[offset] = data; dirty_memories.insert(memid); } } @@ -768,8 +768,8 @@ struct SimInstance int index = addr_int - mem.start_offset; if (index >= 0 && index < mem.size) for (int i = 0; i < (mem.width << port.wide_log2); i++) - if (enable[i] == State::S1 && mdb.data.bits.at(index*mem.width+i) != data[i]) { - mdb.data.bits.at(index*mem.width+i) = data[i]; + if (enable[i] == State::S1 && mdb.data.bits().at(index*mem.width+i) != data[i]) { + mdb.data.bits().at(index*mem.width+i) = data[i]; dirty_memories.insert(mem.memid); did_something = true; } @@ -2525,7 +2525,7 @@ struct AIWWriter : public OutputWriter { auto val = it.second ? State::S1 : State::S0; SigBit bit = aiw_inputs.at(it.first); - auto v = current[mapping[bit.wire]].bits.at(bit.offset); + auto v = current[mapping[bit.wire]].bits().at(bit.offset); if (v == val) skip = true; } @@ -2535,7 +2535,7 @@ struct AIWWriter : public OutputWriter { if (aiw_inputs.count(i)) { SigBit bit = aiw_inputs.at(i); - auto v = current[mapping[bit.wire]].bits.at(bit.offset); + auto v = current[mapping[bit.wire]].bits().at(bit.offset); if (v == State::S1) aiwfile << '1'; else @@ -2544,7 +2544,7 @@ struct AIWWriter : public OutputWriter } if (aiw_inits.count(i)) { SigBit bit = aiw_inits.at(i); - auto v = current[mapping[bit.wire]].bits.at(bit.offset); + auto v = current[mapping[bit.wire]].bits().at(bit.offset); if (v == State::S1) aiwfile << '1'; else diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index 5553abec2..25416b6c4 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -185,25 +185,35 @@ struct SyntProperties : public Pass { log("\n"); log(" synthprop [options]\n"); log("\n"); - log("This creates synthesizable properties for the selected module.\n"); + log("This creates synthesizable properties for selected module.\n"); log("\n"); log("\n"); log(" -name \n"); - log(" name of the output port for assertions (default: assertions).\n"); + log("\n"); + log("Name output port for assertions (default: assertions).\n"); + log("\n"); log("\n"); log(" -map \n"); - log(" write the port mapping for synthesizable properties into the given file.\n"); + log("\n"); + log("Write port mapping for synthesizable properties.\n"); + log("\n"); log("\n"); log(" -or_outputs\n"); - log(" Or all outputs together to create a single output that goes high when\n"); - log(" any property is violated, instead of generating individual output bits.\n"); + log("\n"); + log("Or all outputs together to create a single output that goes high when any\n"); + log("property is violated, instead of generating individual output bits.\n"); + log("\n"); log("\n"); log(" -reset \n"); - log(" name of the top-level reset input. Latch a high state on the generated\n"); - log(" outputs until an asynchronous top-level reset input is activated.\n"); + log("\n"); + log("Name of top-level reset input. Latch a high state on the generated outputs\n"); + log("until an asynchronous top-level reset input is activated.\n"); + log("\n"); log("\n"); log(" -resetn \n"); - log(" like above but with inverse polarity\n"); + log("\n"); + log("Name of top-level reset input (inverse polarity). Latch a high state on the\n"); + log("generated outputs until an asynchronous top-level reset input is activated.\n"); log("\n"); log("\n"); } diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 4eaed1f75..ce63ba9f8 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1543,7 +1543,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // and get cleaned away clone_lut: driver_mask = driver_lut->getParam(ID::LUT); - for (auto &b : driver_mask.bits) { + for (auto &b : driver_mask.bits()) { if (b == RTLIL::State::S0) b = RTLIL::State::S1; else if (b == RTLIL::State::S1) b = RTLIL::State::S0; } diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 9cfe55947..cc4b7f810 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -118,13 +118,13 @@ struct DffinitPass : public Pass { for (int i = 0; i < GetSize(sig); i++) { if (initval[i] == State::Sx) continue; - while (GetSize(value.bits) <= i) - value.bits.push_back(State::S0); - if (noreinit && value.bits[i] != State::Sx && value.bits[i] != initval[i]) + while (GetSize(value.bits()) <= i) + value.bits().push_back(State::S0); + if (noreinit && value.bits()[i] != State::Sx && value.bits()[i] != initval[i]) log_error("Trying to assign a different init value for %s.%s.%s which technically " "have a conflicted init value.\n", log_id(module), log_id(cell), log_id(it.second)); - value.bits[i] = initval[i]; + value.bits()[i] = initval[i]; } if (highlow_mode && GetSize(value) != 0) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 64de3a1ca..f3927a486 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -684,7 +684,7 @@ struct TechmapWorker for (auto &bit : sigmap(conn.second)) { int val = unique_bit_id.at(bit); for (int i = 0; i < bits; i++) { - value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0); + value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0); val = val >> 1; } } @@ -1226,7 +1226,7 @@ struct TechmapPass : public Pass { dict> celltypeMap; for (auto module : map->modules()) { - if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) { + if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).empty()) { char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str()); for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) { std::vector queue; diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index cc208c516..12a5bf523 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -73,10 +73,10 @@ struct ZinitPass : public Pass { pool bits; for (int i = 0; i < ff.width; i++) { - if (ff.val_init.bits[i] == State::S1) + if (ff.val_init.bits()[i] == State::S1) bits.insert(i); - else if (ff.val_init.bits[i] != State::S0 && all_mode) - ff.val_init.bits[i] = State::S0; + else if (ff.val_init.bits()[i] != State::S0 && all_mode) + ff.val_init.bits()[i] = State::S0; } ff.flip_bits(bits); ff.emit(); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index e21ec452c..f7a67798b 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -541,13 +541,13 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: RTLIL::Const in_value; for (int i = 0; i < GetSize(gold_wire); i++) - in_value.bits.push_back(xorshift32(2) ? State::S1 : State::S0); + in_value.bits().push_back(xorshift32(2) ? State::S1 : State::S0); if (xorshift32(4) == 0) { int inv_chance = 1 + xorshift32(8); for (int i = 0; i < GetSize(gold_wire); i++) if (xorshift32(inv_chance) == 0) - in_value.bits[i] = RTLIL::Sx; + in_value.bits()[i] = RTLIL::Sx; } if (verbose) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 3edf6c8fc..b26869080 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -867,12 +867,8 @@ module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1); parameter INIT = 0; endmodule -(* blackbox, keep *) module GSR (input GSRI); -endmodule - -(* blackbox, keep *) -module BANDGAP (input BGEN); + wire GSRO = GSRI; endmodule (* abc9_box, lib_whitebox *) @@ -1905,14 +1901,3 @@ output OSCOUT; parameter FREQ_DIV = 100; parameter REGULATOR_EN = 1'b0; endmodule - -(* blackbox *) -module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT); -input CLK0, CLK1, CLK2, CLK3, SELFORCE; -input [3:0] CLKSEL; -output CLKOUT; -parameter DCS_MODE = "RISING"; -endmodule - - - diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py index 224ece02f..4d117e428 100644 --- a/techlibs/gowin/cells_xtra.py +++ b/techlibs/gowin/cells_xtra.py @@ -13,7 +13,7 @@ class State(Enum): IN_MODULE = auto() IN_PARAMETER = auto() -_skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE', +_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE', 'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE', 'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9', 'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10', diff --git a/techlibs/gowin/cells_xtra.v b/techlibs/gowin/cells_xtra.v index 6ab50a097..4b89b8098 100644 --- a/techlibs/gowin/cells_xtra.v +++ b/techlibs/gowin/cells_xtra.v @@ -1564,6 +1564,12 @@ parameter IDLE = 4'd0, RD_S2 = 4'd12; endmodule +module DCS (...); +input CLK0, CLK1, CLK2, CLK3, SELFORCE; +input [3:0] CLKSEL; +output CLKOUT; +endmodule + module DQCE (...); input CLKIN; input CE; @@ -1681,6 +1687,10 @@ endmodule module ADC (...); endmodule +module BANDGAP (...); +input BGEN; +endmodule + module CLKDIV2 (...); parameter GSREN = "false"; input HCLKIN, RESETN; diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc index a77711e01..d86e69774 100644 --- a/techlibs/greenpak4/greenpak4_dffinv.cc +++ b/techlibs/greenpak4/greenpak4_dffinv.cc @@ -35,10 +35,10 @@ void invert_gp_dff(Cell *cell, bool invert_input) { Const initval = cell->getParam(ID::INIT); if (GetSize(initval) >= 1) { - if (initval.bits[0] == State::S0) - initval.bits[0] = State::S1; - else if (initval.bits[0] == State::S1) - initval.bits[0] = State::S0; + if (initval.bits()[0] == State::S0) + initval.bits()[0] = State::S1; + else if (initval.bits()[0] == State::S1) + initval.bits()[0] = State::S0; cell->setParam(ID::INIT, initval); } @@ -46,10 +46,10 @@ void invert_gp_dff(Cell *cell, bool invert_input) { Const srmode = cell->getParam(ID(SRMODE)); if (GetSize(srmode) >= 1) { - if (srmode.bits[0] == State::S0) - srmode.bits[0] = State::S1; - else if (srmode.bits[0] == State::S1) - srmode.bits[0] = State::S0; + if (srmode.bits()[0] == State::S0) + srmode.bits()[0] = State::S1; + else if (srmode.bits()[0] == State::S1) + srmode.bits()[0] = State::S0; cell->setParam(ID(SRMODE), srmode); } } diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc index 9df979c33..bb1129b35 100644 --- a/techlibs/quicklogic/ql_dsp_simd.cc +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -60,7 +60,7 @@ struct QlDspSimdPass : public Pass { // .......................................... - const int m_ModeBitsSize = 80; + const size_t m_ModeBitsSize = 80; // DSP parameters const std::vector m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"}; @@ -176,7 +176,7 @@ struct QlDspSimdPass : public Pass { sigspec.append(sig); } - int padding = width / 2 - sigspec.bits().size(); + int padding = width / 2 - sigspec.size(); if (padding) { if (!isOutput) @@ -200,8 +200,8 @@ struct QlDspSimdPass : public Pass { auto val_a = dsp_a->getParam(it); auto val_b = dsp_b->getParam(it); - mode_bits.bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); - mode_bits.bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); + mode_bits.bits().insert(mode_bits.end(), val_a.begin(), val_a.end()); + mode_bits.bits().insert(mode_bits.end(), val_b.begin(), val_b.end()); } // Enable the fractured mode by connecting the control diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index 677082916..42f10095d 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -79,7 +79,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool for (int j = 0; j < GetSize(select.second); j++) if (i & 1 << idx_sel[j]) sel_lut_idx |= 1 << j; - bool select_val = (select.first.bits[sel_lut_idx] == State::S1); + bool select_val = (select.first.bits()[sel_lut_idx] == State::S1); bool new_bit; if (select_val ^ select_inv) { // Use alt_data. @@ -90,9 +90,9 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool } else { // Use original LUT. int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1); - new_bit = data.first.bits[lut_idx] == State::S1; + new_bit = data.first.bits()[lut_idx] == State::S1; } - result.first.bits[i] = new_bit ? State::S1 : State::S0; + result.first.bits()[i] = new_bit ? State::S1 : State::S0; } return true; } @@ -212,7 +212,7 @@ lut_sigin_done: if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) { // Flip all bits in the LUT. for (int i = 0; i < GetSize(lut_d.first); i++) - lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1; + lut_d.first.bits()[i] = (lut_d.first.bits()[i] == State::S1) ? State::S0 : State::S1; } LutData lut_d_post_ce;