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const: represent string constants as string, assert not accessed as bits

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Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
parent 960bca0196
commit 498e0498c5
81 changed files with 764 additions and 690 deletions
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17
techlibs/gowin/cells_sim.v
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@ -867,12 +867,8 @@ module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
parameter INIT = 0;
endmodule
(* blackbox, keep *)
module GSR (input GSRI);
endmodule
(* blackbox, keep *)
module BANDGAP (input BGEN);
wire GSRO = GSRI;
endmodule
(* abc9_box, lib_whitebox *)
@ -1905,14 +1901,3 @@ output OSCOUT;
parameter FREQ_DIV = 100;
parameter REGULATOR_EN = 1'b0;
endmodule
(* blackbox *)
module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
endmodule