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const: represent string constants as string, assert not accessed as bits

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This commit is contained in:
Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
parent 960bca0196
commit 498e0498c5
81 changed files with 764 additions and 690 deletions
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17
techlibs/gowin/cells_sim.v
View file

@ -867,12 +867,8 @@ module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
parameter INIT = 0;
endmodule
(* blackbox, keep *)
module GSR (input GSRI);
endmodule
(* blackbox, keep *)
module BANDGAP (input BGEN);
wire GSRO = GSRI;
endmodule
(* abc9_box, lib_whitebox *)
@ -1905,14 +1901,3 @@ output OSCOUT;
parameter FREQ_DIV = 100;
parameter REGULATOR_EN = 1'b0;
endmodule
(* blackbox *)
module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
endmodule

2
techlibs/gowin/cells_xtra.py
View file

@ -13,7 +13,7 @@ class State(Enum):
IN_MODULE = auto()
IN_PARAMETER = auto()
_skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE',
'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9',
'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10',

10
techlibs/gowin/cells_xtra.v
View file

@ -1564,6 +1564,12 @@ parameter IDLE = 4'd0,
RD_S2 = 4'd12;
endmodule
module DCS (...);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
endmodule
module DQCE (...);
input CLKIN;
input CE;
@ -1681,6 +1687,10 @@ endmodule
module ADC (...);
endmodule
module BANDGAP (...);
input BGEN;
endmodule
module CLKDIV2 (...);
parameter GSREN = "false";
input HCLKIN, RESETN;

16
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -35,10 +35,10 @@ void invert_gp_dff(Cell *cell, bool invert_input)
{
Const initval = cell->getParam(ID::INIT);
if (GetSize(initval) >= 1) {
if (initval.bits[0] == State::S0)
initval.bits[0] = State::S1;
else if (initval.bits[0] == State::S1)
initval.bits[0] = State::S0;
if (initval.bits()[0] == State::S0)
initval.bits()[0] = State::S1;
else if (initval.bits()[0] == State::S1)
initval.bits()[0] = State::S0;
cell->setParam(ID::INIT, initval);
}
@ -46,10 +46,10 @@ void invert_gp_dff(Cell *cell, bool invert_input)
{
Const srmode = cell->getParam(ID(SRMODE));
if (GetSize(srmode) >= 1) {
if (srmode.bits[0] == State::S0)
srmode.bits[0] = State::S1;
else if (srmode.bits[0] == State::S1)
srmode.bits[0] = State::S0;
if (srmode.bits()[0] == State::S0)
srmode.bits()[0] = State::S1;
else if (srmode.bits()[0] == State::S1)
srmode.bits()[0] = State::S0;
cell->setParam(ID(SRMODE), srmode);
}
}

8
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -60,7 +60,7 @@ struct QlDspSimdPass : public Pass {
// ..........................................
const int m_ModeBitsSize = 80;
const size_t m_ModeBitsSize = 80;
// DSP parameters
const std::vector<std::string> m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"};
@ -176,7 +176,7 @@ struct QlDspSimdPass : public Pass {
sigspec.append(sig);
}
int padding = width / 2 - sigspec.bits().size();
int padding = width / 2 - sigspec.size();
if (padding) {
if (!isOutput)
@ -200,8 +200,8 @@ struct QlDspSimdPass : public Pass {
auto val_a = dsp_a->getParam(it);
auto val_b = dsp_b->getParam(it);
mode_bits.bits.insert(mode_bits.end(), val_a.begin(), val_a.end());
mode_bits.bits.insert(mode_bits.end(), val_b.begin(), val_b.end());
mode_bits.bits().insert(mode_bits.end(), val_a.begin(), val_a.end());
mode_bits.bits().insert(mode_bits.end(), val_b.begin(), val_b.end());
}
// Enable the fractured mode by connecting the control

8
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -79,7 +79,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
for (int j = 0; j < GetSize(select.second); j++)
if (i & 1 << idx_sel[j])
sel_lut_idx |= 1 << j;
bool select_val = (select.first.bits[sel_lut_idx] == State::S1);
bool select_val = (select.first.bits()[sel_lut_idx] == State::S1);
bool new_bit;
if (select_val ^ select_inv) {
// Use alt_data.
@ -90,9 +90,9 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
} else {
// Use original LUT.
int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
new_bit = data.first.bits[lut_idx] == State::S1;
new_bit = data.first.bits()[lut_idx] == State::S1;
}
result.first.bits[i] = new_bit ? State::S1 : State::S0;
result.first.bits()[i] = new_bit ? State::S1 : State::S0;
}
return true;
}
@ -212,7 +212,7 @@ lut_sigin_done:
if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
// Flip all bits in the LUT.
for (int i = 0; i < GetSize(lut_d.first); i++)
lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1;
lut_d.first.bits()[i] = (lut_d.first.bits()[i] == State::S1) ? State::S0 : State::S1;
}
LutData lut_d_post_ce;