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https://github.com/YosysHQ/yosys
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const: represent string constants as string, assert not accessed as bits
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parent
960bca0196
commit
498e0498c5
81 changed files with 764 additions and 690 deletions
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@ -53,11 +53,11 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
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Const value = valuesig.as_const();
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Const &wireinit = lhs_c.wire->attributes[ID::init];
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while (GetSize(wireinit.bits) < lhs_c.wire->width)
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wireinit.bits.push_back(State::Sx);
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while (GetSize(wireinit.bits()) < lhs_c.wire->width)
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wireinit.bits().push_back(State::Sx);
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for (int i = 0; i < lhs_c.width; i++) {
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auto &initbit = wireinit.bits[i + lhs_c.offset];
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auto &initbit = wireinit.bits()[i + lhs_c.offset];
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if (initbit != State::Sx && initbit != value[i])
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log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
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initbit = value[i];
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@ -100,7 +100,7 @@ struct RomWorker
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val[it2->second] = it.second[i].data;
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}
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}
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for (auto bit: val.bits) {
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for (auto bit: val.bits()) {
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if (bit == State::Sm) {
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log_debug("rejecting switch: lhs not uniform\n");
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return;
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@ -113,8 +113,8 @@ struct RomWorker
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return;
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}
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Const c = addr.as_const();
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while (GetSize(c) && c.bits.back() == State::S0)
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c.bits.pop_back();
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while (GetSize(c) && c.bits().back() == State::S0)
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c.bits().pop_back();
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if (GetSize(c) > swsigbits)
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continue;
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if (GetSize(c) > 30) {
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@ -160,11 +160,11 @@ struct RomWorker
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auto it = vals.find(i);
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if (it == vals.end()) {
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log_assert(got_default);
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for (auto bit: default_val.bits)
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init_data.bits.push_back(bit);
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for (auto bit: default_val.bits())
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init_data.bits().push_back(bit);
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} else {
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for (auto bit: it->second.bits)
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init_data.bits.push_back(bit);
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for (auto bit: it->second.bits())
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init_data.bits().push_back(bit);
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}
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}
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@ -183,12 +183,6 @@ struct RomWorker
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mem.rd_ports.push_back(std::move(rd));
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mem.emit();
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if (sw->has_attribute(ID::src)) {
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mem.inits[0].cell->attributes[ID::src] = sw->attributes[ID::src];
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mem.rd_ports[0].cell->attributes[ID::src] = sw->attributes[ID::src];
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}
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for (auto cs: sw->cases)
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delete cs;
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sw->cases.clear();
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