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const: represent string constants as string, assert not accessed as bits

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This commit is contained in:
Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
parent 960bca0196
commit 498e0498c5
81 changed files with 764 additions and 690 deletions
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8
passes/opt/opt_clean.cc
View file

@ -393,8 +393,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
RTLIL::Const &val = it2->second;
SigSpec sig = assign_map(wire);
for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++)
if (val.bits[i] != State::Sx)
init_bits[sig[i]] = val.bits[i];
if (val.bits()[i] != State::Sx)
init_bits[sig[i]] = val.bits()[i];
wire->attributes.erase(it2);
}
}
@ -406,7 +406,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
for (int i = 0; i < wire->width; i++) {
auto it = init_bits.find(RTLIL::SigBit(wire, i));
if (it != init_bits.end()) {
val.bits[i] = it->second;
val.bits()[i] = it->second;
found = true;
}
}
@ -425,7 +425,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (wire->attributes.count(ID::init))
initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire))
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
wire->attributes.erase(ID::init);

8
passes/opt/opt_dff.cc
View file

@ -361,9 +361,9 @@ struct OptDffWorker
bool failed = false;
for (int i = 0; i < ff.width; i++) {
if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral)
val_arst.bits.push_back(State::S0);
val_arst.bits().push_back(State::S0);
else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral)
val_arst.bits.push_back(State::S1);
val_arst.bits().push_back(State::S1);
else
failed = true;
}
@ -626,7 +626,7 @@ struct OptDffWorker
groups[resets].push_back(i);
} else
remaining_indices.push_back(i);
val_srst.bits.push_back(reset_val);
val_srst.bits().push_back(reset_val);
}
for (auto &it : groups) {
@ -634,7 +634,7 @@ struct OptDffWorker
new_ff.val_srst = Const();
for (int i = 0; i < new_ff.width; i++) {
int j = it.second[i];
new_ff.val_srst.bits.push_back(val_srst[j]);
new_ff.val_srst.bits().push_back(val_srst[j]);
}
ctrl_t srst = combine_resets(it.first, ff.is_fine);

92
passes/opt/opt_expr.cc
View file

@ -31,6 +31,10 @@ PRIVATE_NAMESPACE_BEGIN
bool did_something;
void did_something_hook() {
did_something = true;
}
void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
{
SigMap sigmap(module);
@ -89,7 +93,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
log_debug("Setting undriven signal in %s to constant: %s = %s\n", log_id(module), log_signal(sig), log_signal(val));
module->connect(sig, val);
did_something = true;
did_something_hook();
}
if (!revisit_initwires.empty())
@ -106,11 +110,11 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
wire->attributes.erase(ID::init);
did_something = true;
did_something_hook();
} else if (initval != wire->attributes.at(ID::init)) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
wire->attributes[ID::init] = initval;
did_something = true;
did_something_hook();
}
}
}
@ -129,7 +133,7 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
assign_map.add(Y, out_val);
module->connect(Y, out_val);
module->remove(cell);
did_something = true;
did_something_hook();
}
bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap, bool keepdc)
@ -300,7 +304,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
cover_list("opt.opt_expr.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str());
module->remove(cell);
did_something = true;
did_something_hook();
return true;
}
@ -351,21 +355,21 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative)
bool all_bits_one = true;
bool last_bit_one = true;
if (GetSize(value.bits) < 1)
if (GetSize(value.bits()) < 1)
return false;
if (GetSize(value.bits) == 1) {
if (value.bits[0] != State::S1)
if (GetSize(value.bits()) == 1) {
if (value.bits()[0] != State::S1)
return false;
if (is_signed)
is_negative = true;
return true;
}
for (int i = 0; i < GetSize(value.bits); i++) {
if (value.bits[i] != State::S1)
for (int i = 0; i < GetSize(value.bits()); i++) {
if (value.bits()[i] != State::S1)
all_bits_one = false;
if (value.bits[i] != (i ? State::S0 : State::S1))
if (value.bits()[i] != (i ? State::S0 : State::S1))
last_bit_one = false;
}
@ -645,7 +649,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type = ID($not);
did_something = true;
did_something_hook();
} else {
cover("opt.opt_expr.unary_buffer");
replace_cell(assign_map, module, cell, "unary_buffer", ID::Y, cell->getPort(ID::A));
@ -729,7 +733,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assign_map.add(y_group_x, y_new_x); module->connect(y_group_x, y_new_x);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -757,7 +761,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assign_map.add(y_group_1, b_group_1); module->connect(y_group_1, b_group_1);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
else if (sig_a.is_fully_def() || sig_b.is_fully_def())
@ -790,7 +794,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
module->connect(y_group_1, y_new_1);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -820,7 +824,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
cell->setPort(ID::A, new_sig_a);
cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a);
did_something = true;
did_something_hook();
}
}
@ -843,7 +847,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
cell->setPort(ID::B, new_sig_b);
cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b);
did_something = true;
did_something_hook();
}
}
@ -869,7 +873,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
did_something_hook();
}
}
@ -895,7 +899,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
did_something_hook();
}
}
@ -921,7 +925,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort(ID::B, sig_b = new_b);
cell->parameters.at(ID::B_WIDTH) = 1;
did_something = true;
did_something_hook();
}
}
@ -963,7 +967,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->setPort(ID::B, new_b);
cell->setPort(ID::Y, sig_y.extract_end(i));
cell->fixup_parameters();
did_something = true;
did_something_hook();
}
}
@ -1022,7 +1026,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->setPort(ID::Y, sig_y.extract_end(i));
cell->setPort(ID::CO, sig_co.extract_end(i));
cell->fixup_parameters();
did_something = true;
did_something_hook();
}
}
}
@ -1074,7 +1078,7 @@ skip_fine_alu:
sig_a.remove(width, GetSize(sig_a)-width);
cell->setPort(ID::A, sig_a);
cell->setParam(ID::A_WIDTH, width);
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1093,7 +1097,7 @@ skip_fine_alu:
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(ID::B, tmp);
cell->setPort(ID::S, invert_map.at(assign_map(cell->getPort(ID::S))));
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1201,7 +1205,7 @@ skip_fine_alu:
log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str());
cell->setPort(ID::A, SigSpec(State::Sx, GetSize(a)));
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1279,7 +1283,7 @@ skip_fine_alu:
cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID::B_SIGNED);
cell->unsetPort(ID::B);
did_something = true;
did_something_hook();
}
goto next_cell;
}
@ -1300,7 +1304,7 @@ skip_fine_alu:
cell->unsetPort(ID::B);
cell->unsetParam(ID::B_SIGNED);
cell->unsetParam(ID::B_WIDTH);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1334,7 +1338,7 @@ skip_fine_alu:
module->connect(cell->getPort(ID::Y), sig_y);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1445,7 +1449,7 @@ skip_fine_alu:
cell->parameters.erase(ID::B_SIGNED);
cell->check();
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1474,7 +1478,7 @@ skip_identity:
cell->type = ID($not);
} else
cell->type = ID($_NOT_);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1494,7 +1498,7 @@ skip_identity:
cell->type = ID($and);
} else
cell->type = ID($_AND_);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1514,7 +1518,7 @@ skip_identity:
cell->type = ID($or);
} else
cell->type = ID($_OR_);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1565,7 +1569,7 @@ skip_identity:
cell->type = ID($mux);
cell->parameters.erase(ID::S_WIDTH);
}
did_something = true;
did_something_hook();
}
}
@ -1712,7 +1716,7 @@ skip_identity:
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1741,7 +1745,7 @@ skip_identity:
cell->setPort(ID::B, new_b);
cell->check();
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1766,7 +1770,7 @@ skip_identity:
module->connect(sig_y, RTLIL::SigSpec(0, GetSize(sig_y)));
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1783,7 +1787,7 @@ skip_identity:
module->connect(RTLIL::SigSig(sig_y.extract(0, y_zeros), RTLIL::SigSpec(0, y_zeros)));
cell->check();
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1808,7 +1812,7 @@ skip_identity:
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(State::Sx, sig_y.size())));
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1882,7 +1886,7 @@ skip_identity:
}
}
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1976,7 +1980,7 @@ skip_identity:
cover("opt.opt_expr.alu_split");
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
skip_alu_split:
@ -2037,7 +2041,7 @@ skip_alu_split:
module->connect(y_sig, y_value);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -2051,7 +2055,7 @@ skip_alu_split:
cell->setParam(ID::A_WIDTH, GetSize(sig_a));
cell->setParam(ID::B_WIDTH, GetSize(sig_b));
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -2187,7 +2191,7 @@ skip_alu_split:
if (replace)
module->connect(cell->getPort(ID::Y), replace_sig);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -2212,7 +2216,7 @@ void replace_const_connections(RTLIL::Module *module) {
changes.push_back({conn.first, mapped});
}
if (!changes.empty())
did_something = true;
did_something_hook();
for (auto &it : changes)
cell->setPort(it.first, it.second);
}

8
passes/opt/opt_ffinv.cc
View file

@ -98,7 +98,7 @@ struct OptFfInvWorker
Const mask = lut->getParam(ID::LUT);
Const new_mask;
for (int j = 0; j < (1 << GetSize(sig_a)); j++) {
new_mask.bits.push_back(mask.bits[j ^ flip_mask]);
new_mask.bits().push_back(mask.bits()[j ^ flip_mask]);
}
if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
module->connect(lut->getPort(ID::Y), ff.sig_q);
@ -180,10 +180,10 @@ struct OptFfInvWorker
Const mask = d_lut->getParam(ID::LUT);
Const new_mask;
for (int i = 0; i < GetSize(mask); i++) {
if (mask.bits[i] == State::S0)
new_mask.bits.push_back(State::S1);
if (mask.bits()[i] == State::S0)
new_mask.bits().push_back(State::S1);
else
new_mask.bits.push_back(State::S0);
new_mask.bits().push_back(State::S0);
}
d_lut->setParam(ID::LUT, new_mask);
if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {

12
passes/opt/opt_mem.cc
View file

@ -90,7 +90,7 @@ struct OptMemPass : public Pass {
}
for (auto &init : mem.inits) {
for (int i = 0; i < GetSize(init.data); i++) {
State bit = init.data.bits[i];
State bit = init.data.bits()[i];
int lane = i % mem.width;
if (bit != State::Sx && bit != State::S0) {
always_0[lane] = false;
@ -182,9 +182,9 @@ struct OptMemPass : public Pass {
for (auto i: swizzle) {
int bidx = sub * mem.width + i;
new_data.append(port.data[bidx]);
new_init.bits.push_back(port.init_value.bits[bidx]);
new_arst.bits.push_back(port.arst_value.bits[bidx]);
new_srst.bits.push_back(port.srst_value.bits[bidx]);
new_init.bits().push_back(port.init_value.bits()[bidx]);
new_arst.bits().push_back(port.arst_value.bits()[bidx]);
new_srst.bits().push_back(port.srst_value.bits()[bidx]);
}
}
port.data = new_data;
@ -197,11 +197,11 @@ struct OptMemPass : public Pass {
Const new_en;
for (int s = 0; s < GetSize(init.data); s += mem.width) {
for (auto i: swizzle) {
new_data.bits.push_back(init.data.bits[s + i]);
new_data.bits().push_back(init.data.bits()[s + i]);
}
}
for (auto i: swizzle) {
new_en.bits.push_back(init.en.bits[i]);
new_en.bits().push_back(init.en.bits()[i]);
}
init.data = new_data;
init.en = new_en;

9
passes/opt/opt_merge.cc
View file

@ -140,8 +140,13 @@ struct OptMergeWorker
hash_conn_strings.push_back(s + "\n");
}
for (auto &it : cell->parameters)
hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
for (auto &it : cell->parameters) {
Const c = it.second;
std::string s = "P " + it.first.str() + "=";
s += (c.flags & RTLIL::CONST_FLAG_STRING_COMPACT) ? c.decode_string() : c.as_string();
s += "\n";
hash_conn_strings.push_back(s);
}
std::sort(hash_conn_strings.begin(), hash_conn_strings.end());

6
passes/opt/pmux2shiftx.cc
View file

@ -323,7 +323,7 @@ struct Pmux2ShiftxPass : public Pass {
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits.push_back(it.second);
entry.second.bits().push_back(it.second);
}
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
@ -344,7 +344,7 @@ struct Pmux2ShiftxPass : public Pass {
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits.push_back(it.second);
entry.second.bits().push_back(it.second);
}
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
@ -411,7 +411,7 @@ struct Pmux2ShiftxPass : public Pass {
for (int i : seldb.at(sig)) {
Const val = eqdb.at(S[i]).second;
int onebits = 0;
for (auto b : val.bits)
for (auto b : val.bits())
if (b == State::S1)
onebits++;
if (onebits > 1)

22
passes/opt/share.cc
View file

@ -781,18 +781,18 @@ struct ShareWorker
std::vector<RTLIL::SigBit> p_first_bits = p.first;
for (int i = 0; i < GetSize(p_first_bits); i++) {
RTLIL::SigBit b = p_first_bits[i];
RTLIL::State v = p.second.bits[i];
RTLIL::State v = p.second.bits()[i];
if (p_bits.count(b) && p_bits.at(b) != v)
return false;
p_bits[b] = v;
}
p.first = RTLIL::SigSpec();
p.second.bits.clear();
p.second.bits().clear();
for (auto &it : p_bits) {
p.first.append(it.first);
p.second.bits.push_back(it.second);
p.second.bits().push_back(it.second);
}
return true;
@ -815,10 +815,10 @@ struct ShareWorker
{
auto otherval = val;
if (otherval.bits[i] == State::S0)
otherval.bits[i] = State::S1;
else if (otherval.bits[i] == State::S1)
otherval.bits[i] = State::S0;
if (otherval.bits()[i] == State::S0)
otherval.bits()[i] = State::S1;
else if (otherval.bits()[i] == State::S1)
otherval.bits()[i] = State::S0;
else
continue;
@ -828,7 +828,7 @@ struct ShareWorker
newsig.remove(i);
auto newval = val;
newval.bits.erase(newval.bits.begin() + i);
newval.bits().erase(newval.bits().begin() + i);
db[newsig].insert(newval);
db[sig].erase(otherval);
@ -907,14 +907,14 @@ struct ShareWorker
if (used_in_a)
for (auto p : c_patterns) {
for (int i = 0; i < GetSize(sig_s); i++)
p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
p.first.append(sig_s[i]), p.second.bits().push_back(RTLIL::State::S0);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
for (int idx : used_in_b_parts)
for (auto p : c_patterns) {
p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
p.first.append(sig_s[idx]), p.second.bits().push_back(RTLIL::State::S1);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
@ -965,7 +965,7 @@ struct ShareWorker
for (int i = 0; i < GetSize(p_first); i++)
if (filter_bits.count(p_first[i]) == 0) {
new_p.first.append(p_first[i]);
new_p.second.bits.push_back(p.second.bits.at(i));
new_p.second.bits().push_back(p.second.bits().at(i));
}
out.insert(new_p);

4
passes/opt/wreduce.cc
View file

@ -219,10 +219,10 @@ struct WreduceWorker
// Narrow ARST_VALUE parameter to new size.
if (cell->parameters.count(ID::ARST_VALUE)) {
rst_value.bits.resize(GetSize(sig_q));
rst_value.bits().resize(GetSize(sig_q));
cell->setParam(ID::ARST_VALUE, rst_value);
} else if (cell->parameters.count(ID::SRST_VALUE)) {
rst_value.bits.resize(GetSize(sig_q));
rst_value.bits().resize(GetSize(sig_q));
cell->setParam(ID::SRST_VALUE, rst_value);
}