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const: represent string constants as string, assert not accessed as bits

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This commit is contained in:
Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
parent 960bca0196
commit 498e0498c5
81 changed files with 764 additions and 690 deletions
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22
passes/fsm/fsm_opt.cc
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@ -106,11 +106,11 @@ struct FsmOpt
for (int i = 0; i < ctrl_in.size(); i++) {
RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1);
if (ctrl_bit.is_fully_const()) {
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit)
if (tr.ctrl_in.bits()[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits()[i]) != ctrl_bit)
goto delete_this_transition;
continue;
}
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1)
if (tr.ctrl_in.bits()[i] <= RTLIL::State::S1)
ctrl_in_used[i] = true;
}
new_transition_table.push_back(tr);
@ -169,8 +169,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits[i];
RTLIL::State &sj = tr.ctrl_in.bits[j];
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_in.bits()[j];
if (si > RTLIL::State::S1)
si = sj;
@ -207,8 +207,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits[i];
RTLIL::State &sj = tr.ctrl_out.bits[j];
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_out.bits()[j];
if (si > RTLIL::State::S1 || si == sj) {
RTLIL::SigSpec tmp(tr.ctrl_in);
@ -232,22 +232,22 @@ struct FsmOpt
for (auto &pattern : set)
{
if (pattern.bits[bit] > RTLIL::State::S1) {
if (pattern.bits()[bit] > RTLIL::State::S1) {
new_set.insert(pattern);
continue;
}
RTLIL::Const other_pattern = pattern;
if (pattern.bits[bit] == RTLIL::State::S1)
other_pattern.bits[bit] = RTLIL::State::S0;
if (pattern.bits()[bit] == RTLIL::State::S1)
other_pattern.bits()[bit] = RTLIL::State::S0;
else
other_pattern.bits[bit] = RTLIL::State::S1;
other_pattern.bits()[bit] = RTLIL::State::S1;
if (set.count(other_pattern) > 0) {
log(" Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern),
tr.state_in, tr.state_out, log_signal(tr.ctrl_out));
other_pattern.bits[bit] = RTLIL::State::Sa;
other_pattern.bits()[bit] = RTLIL::State::Sa;
new_set.insert(other_pattern);
did_something = true;
continue;