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const: represent string constants as string, assert not accessed as bits

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This commit is contained in:
Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
parent 960bca0196
commit 498e0498c5
81 changed files with 764 additions and 690 deletions
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2
passes/cmds/bugpoint.cc
View file

@ -354,7 +354,7 @@ struct BugpointPass : public Pass {
for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
auto &mask = it2->priority_mask;
if (GetSize(mask) > i) {
mask.bits.erase(mask.bits.begin() + i);
mask.bits().erase(mask.bits().begin() + i);
}
}
return design_copy;

2
passes/cmds/clean_zerowidth.cc
View file

@ -160,7 +160,7 @@ struct CleanZeroWidthPass : public Pass {
memwr.address = State::S0;
Const priority_mask;
for (auto x : swizzle) {
priority_mask.bits.push_back(memwr.priority_mask.bits[x]);
priority_mask.bits().push_back(memwr.priority_mask.bits()[x]);
}
memwr.priority_mask = priority_mask;
swizzle.push_back(i);

2
passes/cmds/dft_tag.cc
View file

@ -883,7 +883,7 @@ struct DftTagWorker {
{
if (sig_a.is_fully_const()) {
auto const_val = sig_a.as_const();
for (auto &bit : const_val.bits)
for (auto &bit : const_val.bits())
bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit;
return const_val;
}

4
passes/cmds/printattrs.cc
View file

@ -40,12 +40,12 @@ struct PrintAttrsPass : public Pass {
}
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags == RTLIL::CONST_FLAG_STRING)
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str());
else if (x.flags == RTLIL::CONST_FLAG_NONE)
log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str());
else
log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override

8
passes/cmds/setundef.cc
View file

@ -243,7 +243,9 @@ struct SetundefPass : public Pass {
{
for (auto *cell : module->selected_cells()) {
for (auto &parameter : cell->parameters) {
for (auto &bit : parameter.second.bits) {
if (parameter.second.flags & RTLIL::CONST_FLAG_STRING)
continue;
for (auto &bit : parameter.second.bits()) {
if (bit > RTLIL::State::S1)
bit = worker.next_bit();
}
@ -390,7 +392,7 @@ struct SetundefPass : public Pass {
for (auto wire : initwires)
{
Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
for (int i = 0; i < GetSize(wire); i++) {
SigBit bit = sigmap(SigBit(wire, i));
@ -421,7 +423,7 @@ struct SetundefPass : public Pass {
continue;
Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) {
wire->attributes.erase(ID::init);

2
passes/cmds/splitnets.cc
View file

@ -77,7 +77,7 @@ struct SplitnetsWorker
if (it != wire->attributes.end()) {
Const old_init = it->second, new_init;
for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
new_init.bits().push_back(i < GetSize(old_init) ? old_init.bits().at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init);
}

4
passes/fsm/fsm_extract.cc
View file

@ -168,10 +168,10 @@ undef_bit_in_next_state:
ctrl_in_bit_indices[ctrl_in[i]] = i;
for (auto &it : ctrl_in_bit_indices)
if (tr.ctrl_in.bits.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
if (tr.ctrl_in.bits().at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
for (auto &dc_bit : exclusive_ctrls.at(it.first))
if (ctrl_in_bit_indices.count(dc_bit))
tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
tr.ctrl_in.bits().at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits);
if (state_in >= 0)

30
passes/fsm/fsm_map.cc
View file

@ -30,11 +30,11 @@ PRIVATE_NAMESPACE_BEGIN
static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern)
{
log_assert(GetSize(super_pattern.bits) == GetSize(sub_pattern.bits));
for (int i = 0; i < GetSize(super_pattern.bits); i++)
if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) {
if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) {
if (super_pattern.bits[i] != sub_pattern.bits[i])
log_assert(GetSize(super_pattern.bits()) == GetSize(sub_pattern.bits()));
for (int i = 0; i < GetSize(super_pattern.bits()); i++)
if (sub_pattern.bits()[i] == RTLIL::State::S0 || sub_pattern.bits()[i] == RTLIL::State::S1) {
if (super_pattern.bits()[i] == RTLIL::State::S0 || super_pattern.bits()[i] == RTLIL::State::S1) {
if (super_pattern.bits()[i] != sub_pattern.bits()[i])
return false;
} else
return false;
@ -54,10 +54,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Const pattern = it.first;
RTLIL::SigSpec eq_sig_a, eq_sig_b, or_sig;
for (size_t j = 0; j < pattern.bits.size(); j++)
if (pattern.bits[j] == RTLIL::State::S0 || pattern.bits[j] == RTLIL::State::S1) {
for (size_t j = 0; j < pattern.size(); j++)
if (pattern.bits()[j] == RTLIL::State::S0 || pattern.bits()[j] == RTLIL::State::S1) {
eq_sig_a.append(ctrl_in.extract(j, 1));
eq_sig_b.append(RTLIL::SigSpec(pattern.bits[j]));
eq_sig_b.append(RTLIL::SigSpec(pattern.bits()[j]));
}
for (int in_state : it.second)
@ -176,7 +176,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
state_dff->type = ID($adff);
state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits)
for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits())
if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0;
state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
@ -198,10 +198,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
RTLIL::Const state = fsm_data.state_table[i];
RTLIL::SigSpec sig_a, sig_b;
for (size_t j = 0; j < state.bits.size(); j++)
if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
for (size_t j = 0; j < state.size(); j++)
if (state.bits()[j] == RTLIL::State::S0 || state.bits()[j] == RTLIL::State::S1) {
sig_a.append(RTLIL::SigSpec(state_wire, j));
sig_b.append(RTLIL::SigSpec(state.bits[j]));
sig_b.append(RTLIL::SigSpec(state.bits()[j]));
}
if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
@ -261,8 +261,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
RTLIL::Const state = fsm_data.state_table[i];
int bit_idx = -1;
for (size_t j = 0; j < state.bits.size(); j++)
if (state.bits[j] == RTLIL::State::S1)
for (size_t j = 0; j < state.size(); j++)
if (state.bits()[j] == RTLIL::State::S1)
bit_idx = j;
if (bit_idx >= 0)
next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
@ -306,7 +306,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
fullstate_cache.insert(j);
for (auto &tr : fsm_data.transition_table) {
if (tr.ctrl_out.bits[i] == RTLIL::State::S1)
if (tr.ctrl_out.bits()[i] == RTLIL::State::S1)
pattern_cache[tr.ctrl_in].insert(tr.state_in);
else
fullstate_cache.erase(tr.state_in);

22
passes/fsm/fsm_opt.cc
View file

@ -106,11 +106,11 @@ struct FsmOpt
for (int i = 0; i < ctrl_in.size(); i++) {
RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1);
if (ctrl_bit.is_fully_const()) {
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit)
if (tr.ctrl_in.bits()[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits()[i]) != ctrl_bit)
goto delete_this_transition;
continue;
}
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1)
if (tr.ctrl_in.bits()[i] <= RTLIL::State::S1)
ctrl_in_used[i] = true;
}
new_transition_table.push_back(tr);
@ -169,8 +169,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits[i];
RTLIL::State &sj = tr.ctrl_in.bits[j];
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_in.bits()[j];
if (si > RTLIL::State::S1)
si = sj;
@ -207,8 +207,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits[i];
RTLIL::State &sj = tr.ctrl_out.bits[j];
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_out.bits()[j];
if (si > RTLIL::State::S1 || si == sj) {
RTLIL::SigSpec tmp(tr.ctrl_in);
@ -232,22 +232,22 @@ struct FsmOpt
for (auto &pattern : set)
{
if (pattern.bits[bit] > RTLIL::State::S1) {
if (pattern.bits()[bit] > RTLIL::State::S1) {
new_set.insert(pattern);
continue;
}
RTLIL::Const other_pattern = pattern;
if (pattern.bits[bit] == RTLIL::State::S1)
other_pattern.bits[bit] = RTLIL::State::S0;
if (pattern.bits()[bit] == RTLIL::State::S1)
other_pattern.bits()[bit] = RTLIL::State::S0;
else
other_pattern.bits[bit] = RTLIL::State::S1;
other_pattern.bits()[bit] = RTLIL::State::S1;
if (set.count(other_pattern) > 0) {
log(" Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern),
tr.state_in, tr.state_out, log_signal(tr.ctrl_out));
other_pattern.bits[bit] = RTLIL::State::Sa;
other_pattern.bits()[bit] = RTLIL::State::Sa;
new_set.insert(other_pattern);
did_something = true;
continue;

6
passes/fsm/fsm_recode.cc
View file

@ -43,8 +43,8 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
fprintf(f, "set_fsm_encoding {");
for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
fprintf(f, " s%d=2#", i);
for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--)
fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
for (int j = GetSize(fsm_data.state_table[i].bits())-1; j >= 0; j--)
fprintf(f, "%c", fsm_data.state_table[i].bits()[j] == RTLIL::State::S1 ? '1' : '0');
}
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
prefix, RTLIL::unescape_id(name).c_str(),
@ -105,7 +105,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
if (encoding == "one-hot") {
new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits);
new_code.bits[state_idx] = RTLIL::State::S1;
new_code.bits()[state_idx] = RTLIL::State::S1;
} else
if (encoding == "binary") {
new_code = RTLIL::Const(state_idx, fsm_data.state_bits);

26
passes/fsm/fsmdata.h
View file

@ -48,8 +48,8 @@ struct FsmData
cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) {
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
std::vector<RTLIL::State> &bits_state = state_table[i].bits;
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits();
std::vector<RTLIL::State> &bits_state = state_table[i].bits();
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
}
@ -57,16 +57,16 @@ struct FsmData
cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
for (int i = 0; i < int(transition_table.size()); i++)
{
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits();
transition_t &tr = transition_table[i];
RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);
std::vector<RTLIL::State> &bits_state_in = const_state_in.bits;
std::vector<RTLIL::State> &bits_state_out = const_state_out.bits;
std::vector<RTLIL::State> &bits_state_in = const_state_in.bits();
std::vector<RTLIL::State> &bits_state_out = const_state_out.bits();
std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits;
std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits;
std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits();
std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits();
// append lsb first
bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());
@ -97,23 +97,23 @@ struct FsmData
for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code;
int off_begin = i*state_bits, off_end = off_begin + state_bits;
state_code.bits.insert(state_code.bits.begin(), state_table.bits.begin()+off_begin, state_table.bits.begin()+off_end);
state_code.bits().insert(state_code.bits().begin(), state_table.bits().begin()+off_begin, state_table.bits().begin()+off_end);
this->state_table.push_back(state_code);
}
for (int i = 0; i < trans_num; i++)
{
auto off_ctrl_out = trans_table.bits.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
auto off_ctrl_out = trans_table.bits().begin() + i*(num_inputs+num_outputs+2*state_num_log2);
auto off_state_out = off_ctrl_out + num_outputs;
auto off_ctrl_in = off_state_out + state_num_log2;
auto off_state_in = off_ctrl_in + num_inputs;
auto off_end = off_state_in + state_num_log2;
RTLIL::Const state_in, state_out, ctrl_in, ctrl_out;
ctrl_out.bits.insert(state_in.bits.begin(), off_ctrl_out, off_state_out);
state_out.bits.insert(state_out.bits.begin(), off_state_out, off_ctrl_in);
ctrl_in.bits.insert(ctrl_in.bits.begin(), off_ctrl_in, off_state_in);
state_in.bits.insert(state_in.bits.begin(), off_state_in, off_end);
ctrl_out.bits().insert(state_in.bits().begin(), off_ctrl_out, off_state_out);
state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in);
ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in);
state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end);
transition_t tr;
tr.state_in = state_in.as_int();

2
passes/hierarchy/submod.cc
View file

@ -279,7 +279,7 @@ struct SubmodWorker
for (auto cell : module->cells())
{
if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].bits.size() == 0) {
if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].size() == 0) {
cell->attributes.erase(ID::submod);
continue;
}

11
passes/memory/memory_libmap.cc
View file

@ -533,6 +533,7 @@ void MemMapping::determine_style() {
find_attr = search_for_attribute(mem, attr);
if (find_attr.first) {
Const val = find_attr.second;
log(">>>%s<<<\n", log_const(val));
if (val == 1) {
kind = RamKind::NotLogic;
log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", log_id(attr), log_id(mem.module->name), log_id(mem.memid));
@ -1019,7 +1020,7 @@ void MemMapping::handle_priority() {
}
bool is_all_zero(const Const &val) {
for (auto bit: val.bits)
for (auto bit: val.bits())
if (bit == State::S1)
return false;
return true;
@ -1913,7 +1914,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(val.bits[bit.bit]);
hw_val.push_back(val.bits()[bit.bit]);
}
}
if (pdef.rdinitval == ResetValKind::NoUndef)
@ -1926,7 +1927,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(rport.arst_value.bits[bit.bit]);
hw_val.push_back(rport.arst_value.bits()[bit.bit]);
}
}
if (pdef.rdarstval == ResetValKind::NoUndef)
@ -1939,7 +1940,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(rport.srst_value.bits[bit.bit]);
hw_val.push_back(rport.srst_value.bits()[bit.bit]);
}
}
if (pdef.rdsrstval == ResetValKind::NoUndef)
@ -2103,7 +2104,7 @@ void MemMapping::emit(const MemConfig &cfg) {
if (hwa & 1 << i)
addr += 1 << hw_addr_swizzle[i];
if (addr >= mem.start_offset && addr < mem.start_offset + mem.size)
initval.push_back(init_data.bits[(addr - mem.start_offset) * mem.width + bit.bit]);
initval.push_back(init_data.bits()[(addr - mem.start_offset) * mem.width + bit.bit]);
else
initval.push_back(State::Sx);
}

8
passes/opt/opt_clean.cc
View file

@ -393,8 +393,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
RTLIL::Const &val = it2->second;
SigSpec sig = assign_map(wire);
for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++)
if (val.bits[i] != State::Sx)
init_bits[sig[i]] = val.bits[i];
if (val.bits()[i] != State::Sx)
init_bits[sig[i]] = val.bits()[i];
wire->attributes.erase(it2);
}
}
@ -406,7 +406,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
for (int i = 0; i < wire->width; i++) {
auto it = init_bits.find(RTLIL::SigBit(wire, i));
if (it != init_bits.end()) {
val.bits[i] = it->second;
val.bits()[i] = it->second;
found = true;
}
}
@ -425,7 +425,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (wire->attributes.count(ID::init))
initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire))
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
wire->attributes.erase(ID::init);

8
passes/opt/opt_dff.cc
View file

@ -361,9 +361,9 @@ struct OptDffWorker
bool failed = false;
for (int i = 0; i < ff.width; i++) {
if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral)
val_arst.bits.push_back(State::S0);
val_arst.bits().push_back(State::S0);
else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral)
val_arst.bits.push_back(State::S1);
val_arst.bits().push_back(State::S1);
else
failed = true;
}
@ -626,7 +626,7 @@ struct OptDffWorker
groups[resets].push_back(i);
} else
remaining_indices.push_back(i);
val_srst.bits.push_back(reset_val);
val_srst.bits().push_back(reset_val);
}
for (auto &it : groups) {
@ -634,7 +634,7 @@ struct OptDffWorker
new_ff.val_srst = Const();
for (int i = 0; i < new_ff.width; i++) {
int j = it.second[i];
new_ff.val_srst.bits.push_back(val_srst[j]);
new_ff.val_srst.bits().push_back(val_srst[j]);
}
ctrl_t srst = combine_resets(it.first, ff.is_fine);

92
passes/opt/opt_expr.cc
View file

@ -31,6 +31,10 @@ PRIVATE_NAMESPACE_BEGIN
bool did_something;
void did_something_hook() {
did_something = true;
}
void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
{
SigMap sigmap(module);
@ -89,7 +93,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
log_debug("Setting undriven signal in %s to constant: %s = %s\n", log_id(module), log_signal(sig), log_signal(val));
module->connect(sig, val);
did_something = true;
did_something_hook();
}
if (!revisit_initwires.empty())
@ -106,11 +110,11 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
wire->attributes.erase(ID::init);
did_something = true;
did_something_hook();
} else if (initval != wire->attributes.at(ID::init)) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
wire->attributes[ID::init] = initval;
did_something = true;
did_something_hook();
}
}
}
@ -129,7 +133,7 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
assign_map.add(Y, out_val);
module->connect(Y, out_val);
module->remove(cell);
did_something = true;
did_something_hook();
}
bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap, bool keepdc)
@ -300,7 +304,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
cover_list("opt.opt_expr.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str());
module->remove(cell);
did_something = true;
did_something_hook();
return true;
}
@ -351,21 +355,21 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative)
bool all_bits_one = true;
bool last_bit_one = true;
if (GetSize(value.bits) < 1)
if (GetSize(value.bits()) < 1)
return false;
if (GetSize(value.bits) == 1) {
if (value.bits[0] != State::S1)
if (GetSize(value.bits()) == 1) {
if (value.bits()[0] != State::S1)
return false;
if (is_signed)
is_negative = true;
return true;
}
for (int i = 0; i < GetSize(value.bits); i++) {
if (value.bits[i] != State::S1)
for (int i = 0; i < GetSize(value.bits()); i++) {
if (value.bits()[i] != State::S1)
all_bits_one = false;
if (value.bits[i] != (i ? State::S0 : State::S1))
if (value.bits()[i] != (i ? State::S0 : State::S1))
last_bit_one = false;
}
@ -645,7 +649,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
log_id(cell->type), log_id(cell->name), log_id(module));
cell->type = ID($not);
did_something = true;
did_something_hook();
} else {
cover("opt.opt_expr.unary_buffer");
replace_cell(assign_map, module, cell, "unary_buffer", ID::Y, cell->getPort(ID::A));
@ -729,7 +733,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assign_map.add(y_group_x, y_new_x); module->connect(y_group_x, y_new_x);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -757,7 +761,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assign_map.add(y_group_1, b_group_1); module->connect(y_group_1, b_group_1);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
else if (sig_a.is_fully_def() || sig_b.is_fully_def())
@ -790,7 +794,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
module->connect(y_group_1, y_new_1);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -820,7 +824,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
cell->setPort(ID::A, new_sig_a);
cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a);
did_something = true;
did_something_hook();
}
}
@ -843,7 +847,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
cell->setPort(ID::B, new_sig_b);
cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b);
did_something = true;
did_something_hook();
}
}
@ -869,7 +873,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
did_something_hook();
}
}
@ -895,7 +899,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
did_something_hook();
}
}
@ -921,7 +925,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort(ID::B, sig_b = new_b);
cell->parameters.at(ID::B_WIDTH) = 1;
did_something = true;
did_something_hook();
}
}
@ -963,7 +967,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->setPort(ID::B, new_b);
cell->setPort(ID::Y, sig_y.extract_end(i));
cell->fixup_parameters();
did_something = true;
did_something_hook();
}
}
@ -1022,7 +1026,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->setPort(ID::Y, sig_y.extract_end(i));
cell->setPort(ID::CO, sig_co.extract_end(i));
cell->fixup_parameters();
did_something = true;
did_something_hook();
}
}
}
@ -1074,7 +1078,7 @@ skip_fine_alu:
sig_a.remove(width, GetSize(sig_a)-width);
cell->setPort(ID::A, sig_a);
cell->setParam(ID::A_WIDTH, width);
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1093,7 +1097,7 @@ skip_fine_alu:
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(ID::B, tmp);
cell->setPort(ID::S, invert_map.at(assign_map(cell->getPort(ID::S))));
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1201,7 +1205,7 @@ skip_fine_alu:
log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str());
cell->setPort(ID::A, SigSpec(State::Sx, GetSize(a)));
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1279,7 +1283,7 @@ skip_fine_alu:
cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID::B_SIGNED);
cell->unsetPort(ID::B);
did_something = true;
did_something_hook();
}
goto next_cell;
}
@ -1300,7 +1304,7 @@ skip_fine_alu:
cell->unsetPort(ID::B);
cell->unsetParam(ID::B_SIGNED);
cell->unsetParam(ID::B_WIDTH);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1334,7 +1338,7 @@ skip_fine_alu:
module->connect(cell->getPort(ID::Y), sig_y);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1445,7 +1449,7 @@ skip_fine_alu:
cell->parameters.erase(ID::B_SIGNED);
cell->check();
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1474,7 +1478,7 @@ skip_identity:
cell->type = ID($not);
} else
cell->type = ID($_NOT_);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1494,7 +1498,7 @@ skip_identity:
cell->type = ID($and);
} else
cell->type = ID($_AND_);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1514,7 +1518,7 @@ skip_identity:
cell->type = ID($or);
} else
cell->type = ID($_OR_);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1565,7 +1569,7 @@ skip_identity:
cell->type = ID($mux);
cell->parameters.erase(ID::S_WIDTH);
}
did_something = true;
did_something_hook();
}
}
@ -1712,7 +1716,7 @@ skip_identity:
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1741,7 +1745,7 @@ skip_identity:
cell->setPort(ID::B, new_b);
cell->check();
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1766,7 +1770,7 @@ skip_identity:
module->connect(sig_y, RTLIL::SigSpec(0, GetSize(sig_y)));
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1783,7 +1787,7 @@ skip_identity:
module->connect(RTLIL::SigSig(sig_y.extract(0, y_zeros), RTLIL::SigSpec(0, y_zeros)));
cell->check();
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1808,7 +1812,7 @@ skip_identity:
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(State::Sx, sig_y.size())));
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -1882,7 +1886,7 @@ skip_identity:
}
}
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -1976,7 +1980,7 @@ skip_identity:
cover("opt.opt_expr.alu_split");
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
skip_alu_split:
@ -2037,7 +2041,7 @@ skip_alu_split:
module->connect(y_sig, y_value);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
@ -2051,7 +2055,7 @@ skip_alu_split:
cell->setParam(ID::A_WIDTH, GetSize(sig_a));
cell->setParam(ID::B_WIDTH, GetSize(sig_b));
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -2187,7 +2191,7 @@ skip_alu_split:
if (replace)
module->connect(cell->getPort(ID::Y), replace_sig);
module->remove(cell);
did_something = true;
did_something_hook();
goto next_cell;
}
}
@ -2212,7 +2216,7 @@ void replace_const_connections(RTLIL::Module *module) {
changes.push_back({conn.first, mapped});
}
if (!changes.empty())
did_something = true;
did_something_hook();
for (auto &it : changes)
cell->setPort(it.first, it.second);
}

8
passes/opt/opt_ffinv.cc
View file

@ -98,7 +98,7 @@ struct OptFfInvWorker
Const mask = lut->getParam(ID::LUT);
Const new_mask;
for (int j = 0; j < (1 << GetSize(sig_a)); j++) {
new_mask.bits.push_back(mask.bits[j ^ flip_mask]);
new_mask.bits().push_back(mask.bits()[j ^ flip_mask]);
}
if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
module->connect(lut->getPort(ID::Y), ff.sig_q);
@ -180,10 +180,10 @@ struct OptFfInvWorker
Const mask = d_lut->getParam(ID::LUT);
Const new_mask;
for (int i = 0; i < GetSize(mask); i++) {
if (mask.bits[i] == State::S0)
new_mask.bits.push_back(State::S1);
if (mask.bits()[i] == State::S0)
new_mask.bits().push_back(State::S1);
else
new_mask.bits.push_back(State::S0);
new_mask.bits().push_back(State::S0);
}
d_lut->setParam(ID::LUT, new_mask);
if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {

12
passes/opt/opt_mem.cc
View file

@ -90,7 +90,7 @@ struct OptMemPass : public Pass {
}
for (auto &init : mem.inits) {
for (int i = 0; i < GetSize(init.data); i++) {
State bit = init.data.bits[i];
State bit = init.data.bits()[i];
int lane = i % mem.width;
if (bit != State::Sx && bit != State::S0) {
always_0[lane] = false;
@ -182,9 +182,9 @@ struct OptMemPass : public Pass {
for (auto i: swizzle) {
int bidx = sub * mem.width + i;
new_data.append(port.data[bidx]);
new_init.bits.push_back(port.init_value.bits[bidx]);
new_arst.bits.push_back(port.arst_value.bits[bidx]);
new_srst.bits.push_back(port.srst_value.bits[bidx]);
new_init.bits().push_back(port.init_value.bits()[bidx]);
new_arst.bits().push_back(port.arst_value.bits()[bidx]);
new_srst.bits().push_back(port.srst_value.bits()[bidx]);
}
}
port.data = new_data;
@ -197,11 +197,11 @@ struct OptMemPass : public Pass {
Const new_en;
for (int s = 0; s < GetSize(init.data); s += mem.width) {
for (auto i: swizzle) {
new_data.bits.push_back(init.data.bits[s + i]);
new_data.bits().push_back(init.data.bits()[s + i]);
}
}
for (auto i: swizzle) {
new_en.bits.push_back(init.en.bits[i]);
new_en.bits().push_back(init.en.bits()[i]);
}
init.data = new_data;
init.en = new_en;

9
passes/opt/opt_merge.cc
View file

@ -140,8 +140,13 @@ struct OptMergeWorker
hash_conn_strings.push_back(s + "\n");
}
for (auto &it : cell->parameters)
hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
for (auto &it : cell->parameters) {
Const c = it.second;
std::string s = "P " + it.first.str() + "=";
s += (c.flags & RTLIL::CONST_FLAG_STRING_COMPACT) ? c.decode_string() : c.as_string();
s += "\n";
hash_conn_strings.push_back(s);
}
std::sort(hash_conn_strings.begin(), hash_conn_strings.end());

6
passes/opt/pmux2shiftx.cc
View file

@ -323,7 +323,7 @@ struct Pmux2ShiftxPass : public Pass {
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits.push_back(it.second);
entry.second.bits().push_back(it.second);
}
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
@ -344,7 +344,7 @@ struct Pmux2ShiftxPass : public Pass {
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits.push_back(it.second);
entry.second.bits().push_back(it.second);
}
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
@ -411,7 +411,7 @@ struct Pmux2ShiftxPass : public Pass {
for (int i : seldb.at(sig)) {
Const val = eqdb.at(S[i]).second;
int onebits = 0;
for (auto b : val.bits)
for (auto b : val.bits())
if (b == State::S1)
onebits++;
if (onebits > 1)

22
passes/opt/share.cc
View file

@ -781,18 +781,18 @@ struct ShareWorker
std::vector<RTLIL::SigBit> p_first_bits = p.first;
for (int i = 0; i < GetSize(p_first_bits); i++) {
RTLIL::SigBit b = p_first_bits[i];
RTLIL::State v = p.second.bits[i];
RTLIL::State v = p.second.bits()[i];
if (p_bits.count(b) && p_bits.at(b) != v)
return false;
p_bits[b] = v;
}
p.first = RTLIL::SigSpec();
p.second.bits.clear();
p.second.bits().clear();
for (auto &it : p_bits) {
p.first.append(it.first);
p.second.bits.push_back(it.second);
p.second.bits().push_back(it.second);
}
return true;
@ -815,10 +815,10 @@ struct ShareWorker
{
auto otherval = val;
if (otherval.bits[i] == State::S0)
otherval.bits[i] = State::S1;
else if (otherval.bits[i] == State::S1)
otherval.bits[i] = State::S0;
if (otherval.bits()[i] == State::S0)
otherval.bits()[i] = State::S1;
else if (otherval.bits()[i] == State::S1)
otherval.bits()[i] = State::S0;
else
continue;
@ -828,7 +828,7 @@ struct ShareWorker
newsig.remove(i);
auto newval = val;
newval.bits.erase(newval.bits.begin() + i);
newval.bits().erase(newval.bits().begin() + i);
db[newsig].insert(newval);
db[sig].erase(otherval);
@ -907,14 +907,14 @@ struct ShareWorker
if (used_in_a)
for (auto p : c_patterns) {
for (int i = 0; i < GetSize(sig_s); i++)
p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
p.first.append(sig_s[i]), p.second.bits().push_back(RTLIL::State::S0);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
for (int idx : used_in_b_parts)
for (auto p : c_patterns) {
p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
p.first.append(sig_s[idx]), p.second.bits().push_back(RTLIL::State::S1);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
@ -965,7 +965,7 @@ struct ShareWorker
for (int i = 0; i < GetSize(p_first); i++)
if (filter_bits.count(p_first[i]) == 0) {
new_p.first.append(p_first[i]);
new_p.second.bits.push_back(p.second.bits.at(i));
new_p.second.bits().push_back(p.second.bits().at(i));
}
out.insert(new_p);

4
passes/opt/wreduce.cc
View file

@ -219,10 +219,10 @@ struct WreduceWorker
// Narrow ARST_VALUE parameter to new size.
if (cell->parameters.count(ID::ARST_VALUE)) {
rst_value.bits.resize(GetSize(sig_q));
rst_value.bits().resize(GetSize(sig_q));
cell->setParam(ID::ARST_VALUE, rst_value);
} else if (cell->parameters.count(ID::SRST_VALUE)) {
rst_value.bits.resize(GetSize(sig_q));
rst_value.bits().resize(GetSize(sig_q));
cell->setParam(ID::SRST_VALUE, rst_value);
}

4
passes/pmgen/xilinx_dsp.cc
View file

@ -339,11 +339,11 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.overflow->type == ID($ge)) {
Const B = st.overflow->getPort(ID::B).as_const();
log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1);
log_assert(std::count(B.bits().begin(), B.bits().end(), State::S1) == 1);
// Since B is an exact power of 2, subtract 1
// by inverting all bits up until hitting
// that one hi bit
for (auto &b : B.bits)
for (auto &b : B.bits())
if (b == State::S0) b = State::S1;
else if (b == State::S1) {
b = State::S0;

2
passes/pmgen/xilinx_dsp.pmg
View file

@ -363,7 +363,7 @@ match overflow
select GetSize(port(overflow, \Y)) <= 48
select port(overflow, \B).is_fully_const()
define <Const> B port(overflow, \B).as_const()
select std::count(B.bits.begin(), B.bits.end(), State::S1) == 1
select std::count(B.bits().begin(), B.bits().end(), State::S1) == 1
index <SigSpec> port(overflow, \A) === sigP
optional
endmatch

6
passes/proc/proc_init.cc
View file

@ -53,11 +53,11 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
Const value = valuesig.as_const();
Const &wireinit = lhs_c.wire->attributes[ID::init];
while (GetSize(wireinit.bits) < lhs_c.wire->width)
wireinit.bits.push_back(State::Sx);
while (GetSize(wireinit.bits()) < lhs_c.wire->width)
wireinit.bits().push_back(State::Sx);
for (int i = 0; i < lhs_c.width; i++) {
auto &initbit = wireinit.bits[i + lhs_c.offset];
auto &initbit = wireinit.bits()[i + lhs_c.offset];
if (initbit != State::Sx && initbit != value[i])
log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
initbit = value[i];

20
passes/proc/proc_rom.cc
View file

@ -100,7 +100,7 @@ struct RomWorker
val[it2->second] = it.second[i].data;
}
}
for (auto bit: val.bits) {
for (auto bit: val.bits()) {
if (bit == State::Sm) {
log_debug("rejecting switch: lhs not uniform\n");
return;
@ -113,8 +113,8 @@ struct RomWorker
return;
}
Const c = addr.as_const();
while (GetSize(c) && c.bits.back() == State::S0)
c.bits.pop_back();
while (GetSize(c) && c.bits().back() == State::S0)
c.bits().pop_back();
if (GetSize(c) > swsigbits)
continue;
if (GetSize(c) > 30) {
@ -160,11 +160,11 @@ struct RomWorker
auto it = vals.find(i);
if (it == vals.end()) {
log_assert(got_default);
for (auto bit: default_val.bits)
init_data.bits.push_back(bit);
for (auto bit: default_val.bits())
init_data.bits().push_back(bit);
} else {
for (auto bit: it->second.bits)
init_data.bits.push_back(bit);
for (auto bit: it->second.bits())
init_data.bits().push_back(bit);
}
}
@ -183,12 +183,6 @@ struct RomWorker
mem.rd_ports.push_back(std::move(rd));
mem.emit();
if (sw->has_attribute(ID::src)) {
mem.inits[0].cell->attributes[ID::src] = sw->attributes[ID::src];
mem.rd_ports[0].cell->attributes[ID::src] = sw->attributes[ID::src];
}
for (auto cs: sw->cases)
delete cs;
sw->cases.clear();

8
passes/sat/eval.cc
View file

@ -250,13 +250,13 @@ struct VlogHammerReporter
std::string module_name = module_names[mod].c_str();
ConstEval ce(module);
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
std::vector<RTLIL::State> bits(patterns[idx].bits().begin(), patterns[idx].bits().begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wire(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
recorded_set_vals.bits.push_back(bits.back());
recorded_set_vals.bits().push_back(bits.back());
bits.pop_back();
}
if (module == modules.front()) {
@ -346,7 +346,7 @@ struct VlogHammerReporter
log_error("Pattern %s is to short!\n", pattern.c_str());
patterns.push_back(sig.as_const());
if (invert_pattern) {
for (auto &bit : patterns.back().bits)
for (auto &bit : patterns.back().bits())
if (bit == RTLIL::State::S0)
bit = RTLIL::State::S1;
else if (bit == RTLIL::State::S1)
@ -557,7 +557,7 @@ struct EvalPass : public Pass {
tab_line.clear();
ce.pop();
tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.bits.size());
tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.size());
}
while (tabvals.as_bool());

2
passes/sat/expose.cc
View file

@ -131,7 +131,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits;
std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits();
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
info.arst_value = arst_value.at(i);

4
passes/sat/formalff.cc
View file

@ -363,7 +363,7 @@ struct PropagateWorker
for (auto wire : module->wires())
if (wire->has_attribute(ID::replaced_by_gclk))
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1, false);
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].bits().at(0) == State::S1, false);
for (auto cell : module->cells()) {
if (cell->type.in(ID($not), ID($_NOT_))) {
@ -745,7 +745,7 @@ struct FormalFfPass : public Pass {
for (auto wire : module->wires()) {
if (!wire->has_attribute(ID::replaced_by_gclk))
continue;
bool clk_pol = wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1;
bool clk_pol = wire->attributes[ID::replaced_by_gclk].bits().at(0) == State::S1;
found.emplace_back(SigSpec(wire), clk_pol);
}

16
passes/sat/sat.cc
View file

@ -629,9 +629,9 @@ struct SatHelper
bool found_undef = false;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx, found_undef = true;
value.bits().back() = RTLIL::State::Sx, found_undef = true;
}
if (info.timestep != last_timestep) {
@ -740,9 +740,9 @@ struct SatHelper
RTLIL::Const value;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx;
value.bits().back() = RTLIL::State::Sx;
}
if (info.timestep != last_timestep) {
@ -754,11 +754,11 @@ struct SatHelper
}
if(info.width == 1) {
fprintf(f, "%c%s\n", bitvals[value.bits[0]], vcdnames[info.description].c_str());
fprintf(f, "%c%s\n", bitvals[value.bits()[0]], vcdnames[info.description].c_str());
} else {
fprintf(f, "b");
for(int k=info.width-1; k >= 0; k --) //need to flip bit ordering for VCD
fprintf(f, "%c", bitvals[value.bits[k]]);
fprintf(f, "%c", bitvals[value.bits()[k]]);
fprintf(f, " %s\n", vcdnames[info.description].c_str());
}
}
@ -786,9 +786,9 @@ struct SatHelper
{
Const value;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx;
value.bits().back() = RTLIL::State::Sx;
}
wavedata[info.description].first = info.width;

28
passes/sat/sim.cc
View file

@ -134,7 +134,7 @@ void zinit(State &v)
void zinit(Const &v)
{
for (auto &bit : v.bits)
for (auto &bit : v.bits())
zinit(bit);
}
@ -422,11 +422,11 @@ struct SimInstance
for (auto bit : sigmap(sig))
if (bit.wire == nullptr)
value.bits.push_back(bit.data);
value.bits().push_back(bit.data);
else if (state_nets.count(bit))
value.bits.push_back(state_nets.at(bit));
value.bits().push_back(state_nets.at(bit));
else
value.bits.push_back(State::Sz);
value.bits().push_back(State::Sz);
if (shared->debug)
log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
@ -485,9 +485,9 @@ struct SimInstance
int offset = (addr - state.mem->start_offset) * state.mem->width;
for (int i = 0; i < GetSize(data); i++)
if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data.bits[i] != State::Sa)
if (state.data.bits[i+offset] != data.bits[i])
dirty = true, state.data.bits[i+offset] = data.bits[i];
if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data.bits()[i] != State::Sa)
if (state.data.bits()[i+offset] != data.bits()[i])
dirty = true, state.data.bits()[i+offset] = data.bits()[i];
if (dirty)
dirty_memories.insert(memid);
@ -498,8 +498,8 @@ struct SimInstance
auto &state = mem_database[memid];
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
if (state.data.bits[offset] != data) {
state.data.bits[offset] = data;
if (state.data.bits()[offset] != data) {
state.data.bits()[offset] = data;
dirty_memories.insert(memid);
}
}
@ -768,8 +768,8 @@ struct SimInstance
int index = addr_int - mem.start_offset;
if (index >= 0 && index < mem.size)
for (int i = 0; i < (mem.width << port.wide_log2); i++)
if (enable[i] == State::S1 && mdb.data.bits.at(index*mem.width+i) != data[i]) {
mdb.data.bits.at(index*mem.width+i) = data[i];
if (enable[i] == State::S1 && mdb.data.bits().at(index*mem.width+i) != data[i]) {
mdb.data.bits().at(index*mem.width+i) = data[i];
dirty_memories.insert(mem.memid);
did_something = true;
}
@ -2525,7 +2525,7 @@ struct AIWWriter : public OutputWriter
{
auto val = it.second ? State::S1 : State::S0;
SigBit bit = aiw_inputs.at(it.first);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].bits().at(bit.offset);
if (v == val)
skip = true;
}
@ -2535,7 +2535,7 @@ struct AIWWriter : public OutputWriter
{
if (aiw_inputs.count(i)) {
SigBit bit = aiw_inputs.at(i);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].bits().at(bit.offset);
if (v == State::S1)
aiwfile << '1';
else
@ -2544,7 +2544,7 @@ struct AIWWriter : public OutputWriter
}
if (aiw_inits.count(i)) {
SigBit bit = aiw_inits.at(i);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].bits().at(bit.offset);
if (v == State::S1)
aiwfile << '1';
else

26
passes/sat/synthprop.cc
View file

@ -185,25 +185,35 @@ struct SyntProperties : public Pass {
log("\n");
log(" synthprop [options]\n");
log("\n");
log("This creates synthesizable properties for the selected module.\n");
log("This creates synthesizable properties for selected module.\n");
log("\n");
log("\n");
log(" -name <portname>\n");
log(" name of the output port for assertions (default: assertions).\n");
log("\n");
log("Name output port for assertions (default: assertions).\n");
log("\n");
log("\n");
log(" -map <filename>\n");
log(" write the port mapping for synthesizable properties into the given file.\n");
log("\n");
log("Write port mapping for synthesizable properties.\n");
log("\n");
log("\n");
log(" -or_outputs\n");
log(" Or all outputs together to create a single output that goes high when\n");
log(" any property is violated, instead of generating individual output bits.\n");
log("\n");
log("Or all outputs together to create a single output that goes high when any\n");
log("property is violated, instead of generating individual output bits.\n");
log("\n");
log("\n");
log(" -reset <portname>\n");
log(" name of the top-level reset input. Latch a high state on the generated\n");
log(" outputs until an asynchronous top-level reset input is activated.\n");
log("\n");
log("Name of top-level reset input. Latch a high state on the generated outputs\n");
log("until an asynchronous top-level reset input is activated.\n");
log("\n");
log("\n");
log(" -resetn <portname>\n");
log(" like above but with inverse polarity\n");
log("\n");
log("Name of top-level reset input (inverse polarity). Latch a high state on the\n");
log("generated outputs until an asynchronous top-level reset input is activated.\n");
log("\n");
log("\n");
}

2
passes/techmap/abc9_ops.cc
View file

@ -1543,7 +1543,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// and get cleaned away
clone_lut:
driver_mask = driver_lut->getParam(ID::LUT);
for (auto &b : driver_mask.bits) {
for (auto &b : driver_mask.bits()) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}

8
passes/techmap/dffinit.cc
View file

@ -118,13 +118,13 @@ struct DffinitPass : public Pass {
for (int i = 0; i < GetSize(sig); i++) {
if (initval[i] == State::Sx)
continue;
while (GetSize(value.bits) <= i)
value.bits.push_back(State::S0);
if (noreinit && value.bits[i] != State::Sx && value.bits[i] != initval[i])
while (GetSize(value.bits()) <= i)
value.bits().push_back(State::S0);
if (noreinit && value.bits()[i] != State::Sx && value.bits()[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second));
value.bits[i] = initval[i];
value.bits()[i] = initval[i];
}
if (highlow_mode && GetSize(value) != 0) {

4
passes/techmap/techmap.cc
View file

@ -684,7 +684,7 @@ struct TechmapWorker
for (auto &bit : sigmap(conn.second)) {
int val = unique_bit_id.at(bit);
for (int i = 0; i < bits; i++) {
value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0);
val = val >> 1;
}
}
@ -1226,7 +1226,7 @@ struct TechmapPass : public Pass {
dict<IdString, pool<IdString>> celltypeMap;
for (auto module : map->modules()) {
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).empty()) {
char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) {
std::vector<std::string> queue;

6
passes/techmap/zinit.cc
View file

@ -73,10 +73,10 @@ struct ZinitPass : public Pass {
pool<int> bits;
for (int i = 0; i < ff.width; i++) {
if (ff.val_init.bits[i] == State::S1)
if (ff.val_init.bits()[i] == State::S1)
bits.insert(i);
else if (ff.val_init.bits[i] != State::S0 && all_mode)
ff.val_init.bits[i] = State::S0;
else if (ff.val_init.bits()[i] != State::S0 && all_mode)
ff.val_init.bits()[i] = State::S0;
}
ff.flip_bits(bits);
ff.emit();

4
passes/tests/test_cell.cc
View file

@ -541,13 +541,13 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
RTLIL::Const in_value;
for (int i = 0; i < GetSize(gold_wire); i++)
in_value.bits.push_back(xorshift32(2) ? State::S1 : State::S0);
in_value.bits().push_back(xorshift32(2) ? State::S1 : State::S0);
if (xorshift32(4) == 0) {
int inv_chance = 1 + xorshift32(8);
for (int i = 0; i < GetSize(gold_wire); i++)
if (xorshift32(inv_chance) == 0)
in_value.bits[i] = RTLIL::Sx;
in_value.bits()[i] = RTLIL::Sx;
}
if (verbose)