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https://github.com/YosysHQ/yosys
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const: represent string constants as string, assert not accessed as bits
This commit is contained in:
Emil J. Tywoniak
parent
960bca0196
commit
498e0498c5
81 changed files with 764 additions and 690 deletions
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@ -80,7 +80,7 @@ struct BitPatternPool
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bits_t sig2bits(RTLIL::SigSpec sig)
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{
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bits_t bits;
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bits.bitdata = sig.as_const().bits;
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bits.bitdata = sig.as_const().bits();
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for (auto &b : bits.bitdata)
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if (b > RTLIL::State::S1)
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b = RTLIL::State::Sa;
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164
kernel/calc.cc
164
kernel/calc.cc
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@ -30,13 +30,13 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
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{
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RTLIL::State padding = RTLIL::State::S0;
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if (arg.bits.size() > 0 && is_signed)
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padding = arg.bits.back();
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if (arg.size() > 0 && is_signed)
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padding = arg.bits().back();
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while (int(arg.bits.size()) < width)
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arg.bits.push_back(padding);
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while (int(arg.size()) < width)
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arg.bits().push_back(padding);
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arg.bits.resize(width);
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arg.bits().resize(width);
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}
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static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
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@ -45,17 +45,17 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
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BigInteger::Sign sign = BigInteger::positive;
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State inv_sign_bit = RTLIL::State::S1;
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size_t num_bits = val.bits.size();
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size_t num_bits = val.size();
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if (as_signed && num_bits && val.bits[num_bits-1] == RTLIL::State::S1) {
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if (as_signed && num_bits && val.bits()[num_bits-1] == RTLIL::State::S1) {
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inv_sign_bit = RTLIL::State::S0;
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sign = BigInteger::negative;
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num_bits--;
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}
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for (size_t i = 0; i < num_bits; i++)
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if (val.bits[i] == RTLIL::State::S0 || val.bits[i] == RTLIL::State::S1)
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mag.setBit(i, val.bits[i] == inv_sign_bit);
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if (val.bits()[i] == RTLIL::State::S0 || val.bits()[i] == RTLIL::State::S1)
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mag.setBit(i, val.bits()[i] == inv_sign_bit);
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else if (undef_bit_pos < 0)
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undef_bit_pos = i;
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@ -79,19 +79,19 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
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{
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mag--;
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for (int i = 0; i < result_len; i++)
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result.bits[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
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result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
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}
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else
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{
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for (int i = 0; i < result_len; i++)
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result.bits[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
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result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
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}
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}
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#if 0
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if (undef_bit_pos >= 0)
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for (int i = undef_bit_pos; i < result_len; i++)
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result.bits[i] = RTLIL::State::Sx;
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result.bits()[i] = RTLIL::State::Sx;
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#endif
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return result;
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@ -132,19 +132,19 @@ static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b)
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RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
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{
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if (result_len < 0)
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result_len = arg1.bits.size();
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result_len = arg1.size();
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RTLIL::Const arg1_ext = arg1;
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extend_u0(arg1_ext, result_len, signed1);
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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for (size_t i = 0; i < size_t(result_len); i++) {
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if (i >= arg1_ext.bits.size())
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result.bits[i] = RTLIL::State::S0;
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else if (arg1_ext.bits[i] == RTLIL::State::S0)
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result.bits[i] = RTLIL::State::S1;
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else if (arg1_ext.bits[i] == RTLIL::State::S1)
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result.bits[i] = RTLIL::State::S0;
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if (i >= arg1_ext.size())
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result.bits()[i] = RTLIL::State::S0;
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else if (arg1_ext.bits()[i] == RTLIL::State::S0)
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result.bits()[i] = RTLIL::State::S1;
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else if (arg1_ext.bits()[i] == RTLIL::State::S1)
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result.bits()[i] = RTLIL::State::S0;
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}
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return result;
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@ -154,16 +154,16 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
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RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1)
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{
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if (result_len < 0)
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result_len = max(arg1.bits.size(), arg2.bits.size());
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result_len = max(arg1.size(), arg2.size());
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extend_u0(arg1, result_len, signed1);
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extend_u0(arg2, result_len, signed2);
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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for (size_t i = 0; i < size_t(result_len); i++) {
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RTLIL::State a = i < arg1.bits.size() ? arg1.bits[i] : RTLIL::State::S0;
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RTLIL::State b = i < arg2.bits.size() ? arg2.bits[i] : RTLIL::State::S0;
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result.bits[i] = logic_func(a, b);
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RTLIL::State a = i < arg1.size() ? arg1.bits()[i] : RTLIL::State::S0;
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RTLIL::State b = i < arg2.size() ? arg2.bits()[i] : RTLIL::State::S0;
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result.bits()[i] = logic_func(a, b);
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}
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return result;
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@ -193,12 +193,12 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log
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{
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RTLIL::State temp = initial;
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for (size_t i = 0; i < arg1.bits.size(); i++)
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temp = logic_func(temp, arg1.bits[i]);
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for (size_t i = 0; i < arg1.size(); i++)
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temp = logic_func(temp, arg1.bits()[i]);
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RTLIL::Const result(temp);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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while (int(result.size()) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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return result;
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}
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@ -220,11 +220,11 @@ RTLIL::Const RTLIL::const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Cons
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RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
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{
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RTLIL::Const buffer = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len);
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if (!buffer.bits.empty()) {
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if (buffer.bits.front() == RTLIL::State::S0)
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buffer.bits.front() = RTLIL::State::S1;
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else if (buffer.bits.front() == RTLIL::State::S1)
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buffer.bits.front() = RTLIL::State::S0;
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if (!buffer.bits().empty()) {
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if (buffer.bits().front() == RTLIL::State::S0)
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buffer.bits().front() = RTLIL::State::S1;
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else if (buffer.bits().front() == RTLIL::State::S1)
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buffer.bits().front() = RTLIL::State::S0;
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}
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return buffer;
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}
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@ -240,8 +240,8 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const
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BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
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RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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while (int(result.size()) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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return result;
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}
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@ -255,8 +255,8 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const
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RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::Const result(logic_and(bit_a, bit_b));
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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while (int(result.size()) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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return result;
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}
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@ -270,8 +270,8 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const
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RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::Const result(logic_or(bit_a, bit_b));
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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while (int(result.size()) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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return result;
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}
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@ -286,7 +286,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
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BigInteger offset = const2big(arg2, signed2, undef_bit_pos) * direction;
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if (result_len < 0)
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result_len = arg1.bits.size();
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result_len = arg1.size();
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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if (undef_bit_pos >= 0)
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@ -295,11 +295,11 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
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for (int i = 0; i < result_len; i++) {
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BigInteger pos = BigInteger(i) + offset;
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if (pos < 0)
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result.bits[i] = vacant_bits;
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else if (pos >= BigInteger(int(arg1.bits.size())))
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result.bits[i] = sign_ext ? arg1.bits.back() : vacant_bits;
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result.bits()[i] = vacant_bits;
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else if (pos >= BigInteger(int(arg1.size())))
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result.bits()[i] = sign_ext ? arg1.bits().back() : vacant_bits;
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else
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result.bits[i] = arg1.bits[pos.toInt()];
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result.bits()[i] = arg1.bits()[pos.toInt()];
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}
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return result;
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@ -347,8 +347,8 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos);
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RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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while (int(result.size()) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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return result;
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}
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@ -358,8 +358,8 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos);
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RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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while (int(result.size()) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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return result;
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}
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@ -369,31 +369,31 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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RTLIL::Const arg2_ext = arg2;
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RTLIL::Const result(RTLIL::State::S0, result_len);
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int width = max(arg1_ext.bits.size(), arg2_ext.bits.size());
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int width = max(arg1_ext.size(), arg2_ext.size());
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extend_u0(arg1_ext, width, signed1 && signed2);
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extend_u0(arg2_ext, width, signed1 && signed2);
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RTLIL::State matched_status = RTLIL::State::S1;
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for (size_t i = 0; i < arg1_ext.bits.size(); i++) {
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if (arg1_ext.bits.at(i) == RTLIL::State::S0 && arg2_ext.bits.at(i) == RTLIL::State::S1)
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for (size_t i = 0; i < arg1_ext.size(); i++) {
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if (arg1_ext.bits().at(i) == RTLIL::State::S0 && arg2_ext.bits().at(i) == RTLIL::State::S1)
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return result;
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if (arg1_ext.bits.at(i) == RTLIL::State::S1 && arg2_ext.bits.at(i) == RTLIL::State::S0)
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if (arg1_ext.bits().at(i) == RTLIL::State::S1 && arg2_ext.bits().at(i) == RTLIL::State::S0)
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return result;
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if (arg1_ext.bits.at(i) > RTLIL::State::S1 || arg2_ext.bits.at(i) > RTLIL::State::S1)
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if (arg1_ext.bits().at(i) > RTLIL::State::S1 || arg2_ext.bits().at(i) > RTLIL::State::S1)
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matched_status = RTLIL::State::Sx;
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}
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result.bits.front() = matched_status;
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result.bits().front() = matched_status;
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return result;
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}
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RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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{
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RTLIL::Const result = RTLIL::const_eq(arg1, arg2, signed1, signed2, result_len);
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if (result.bits.front() == RTLIL::State::S0)
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result.bits.front() = RTLIL::State::S1;
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else if (result.bits.front() == RTLIL::State::S1)
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result.bits.front() = RTLIL::State::S0;
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if (result.bits().front() == RTLIL::State::S0)
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result.bits().front() = RTLIL::State::S1;
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else if (result.bits().front() == RTLIL::State::S1)
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result.bits().front() = RTLIL::State::S0;
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return result;
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}
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@ -403,26 +403,26 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2
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RTLIL::Const arg2_ext = arg2;
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RTLIL::Const result(RTLIL::State::S0, result_len);
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int width = max(arg1_ext.bits.size(), arg2_ext.bits.size());
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int width = max(arg1_ext.size(), arg2_ext.size());
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extend_u0(arg1_ext, width, signed1 && signed2);
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extend_u0(arg2_ext, width, signed1 && signed2);
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for (size_t i = 0; i < arg1_ext.bits.size(); i++) {
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if (arg1_ext.bits.at(i) != arg2_ext.bits.at(i))
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for (size_t i = 0; i < arg1_ext.size(); i++) {
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if (arg1_ext.bits().at(i) != arg2_ext.bits().at(i))
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return result;
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}
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result.bits.front() = RTLIL::State::S1;
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result.bits().front() = RTLIL::State::S1;
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return result;
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}
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RTLIL::Const RTLIL::const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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{
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RTLIL::Const result = RTLIL::const_eqx(arg1, arg2, signed1, signed2, result_len);
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if (result.bits.front() == RTLIL::State::S0)
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result.bits.front() = RTLIL::State::S1;
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else if (result.bits.front() == RTLIL::State::S1)
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result.bits.front() = RTLIL::State::S0;
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if (result.bits().front() == RTLIL::State::S0)
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result.bits().front() = RTLIL::State::S1;
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else if (result.bits().front() == RTLIL::State::S1)
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result.bits().front() = RTLIL::State::S0;
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return result;
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}
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@ -432,8 +432,8 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos);
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RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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while (int(result.size()) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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return result;
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}
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@ -443,8 +443,8 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
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bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos);
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RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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while (int(result.size()) < result_len)
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result.bits().push_back(RTLIL::State::S0);
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return result;
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}
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@ -452,21 +452,21 @@ RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2
|
|||
{
|
||||
int undef_bit_pos = -1;
|
||||
BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos);
|
||||
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
|
||||
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos);
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
{
|
||||
int undef_bit_pos = -1;
|
||||
BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos);
|
||||
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
|
||||
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos);
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
{
|
||||
int undef_bit_pos = -1;
|
||||
BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos);
|
||||
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
|
||||
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
|
||||
}
|
||||
|
||||
// truncating division
|
||||
|
|
@ -480,7 +480,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2
|
|||
bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative);
|
||||
a = a.getSign() == BigInteger::negative ? -a : a;
|
||||
b = b.getSign() == BigInteger::negative ? -b : b;
|
||||
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
|
||||
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
|
||||
}
|
||||
|
||||
// truncating modulo
|
||||
|
|
@ -494,7 +494,7 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2
|
|||
bool result_neg = a.getSign() == BigInteger::negative;
|
||||
a = a.getSign() == BigInteger::negative ? -a : a;
|
||||
b = b.getSign() == BigInteger::negative ? -b : b;
|
||||
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
|
||||
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
|
|
@ -516,7 +516,7 @@ RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const
|
|||
// bigint division with negative numbers is wonky, make sure we only negate at the very end
|
||||
result = -((a + b - 1) / b);
|
||||
}
|
||||
return big2const(result, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
|
||||
return big2const(result, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
|
|
@ -539,7 +539,7 @@ RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const
|
|||
} else {
|
||||
modulo = b_sign == BigInteger::negative ? truncated - b : truncated + b;
|
||||
}
|
||||
return big2const(modulo, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
|
||||
return big2const(modulo, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
|
|
@ -590,7 +590,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
|
|||
y *= -1;
|
||||
}
|
||||
|
||||
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
|
||||
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
|
||||
|
|
@ -634,18 +634,18 @@ RTLIL::Const RTLIL::const_pmux(const RTLIL::Const &arg1, const RTLIL::Const &arg
|
|||
|
||||
for (int i = 0; i < arg3.size(); i++)
|
||||
if (arg3[i] == State::S1)
|
||||
return RTLIL::Const(std::vector<RTLIL::State>(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size()));
|
||||
return RTLIL::Const(std::vector<RTLIL::State>(arg2.bits().begin() + i*arg1.size(), arg2.bits().begin() + (i+1)*arg1.size()));
|
||||
|
||||
log_abort(); // unreachable
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_bmux(const RTLIL::Const &arg1, const RTLIL::Const &arg2)
|
||||
{
|
||||
std::vector<RTLIL::State> t = arg1.bits;
|
||||
std::vector<RTLIL::State> t = arg1.bits();
|
||||
|
||||
for (int i = GetSize(arg2)-1; i >= 0; i--)
|
||||
{
|
||||
RTLIL::State sel = arg2.bits.at(i);
|
||||
RTLIL::State sel = arg2.bits().at(i);
|
||||
std::vector<RTLIL::State> new_t;
|
||||
if (sel == State::S0)
|
||||
new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
|
||||
|
|
@ -681,10 +681,10 @@ RTLIL::Const RTLIL::const_demux(const RTLIL::Const &arg1, const RTLIL::Const &ar
|
|||
res.push_back(State::S0);
|
||||
} else if (x) {
|
||||
for (int j = 0; j < width; j++)
|
||||
res.push_back(arg1.bits[j] == State::S0 ? State::S0 : State::Sx);
|
||||
res.push_back(arg1.bits()[j] == State::S0 ? State::S0 : State::Sx);
|
||||
} else {
|
||||
for (int j = 0; j < width; j++)
|
||||
res.push_back(arg1.bits[j]);
|
||||
res.push_back(arg1.bits()[j]);
|
||||
}
|
||||
}
|
||||
return res;
|
||||
|
|
|
|||
|
|
@ -274,7 +274,10 @@ Aig::Aig(Cell *cell)
|
|||
name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
|
||||
} else {
|
||||
mkname_last = name;
|
||||
name += stringf(":%d", p.second.as_int());
|
||||
if (p.second.flags & RTLIL::CONST_FLAG_STRING_COMPACT)
|
||||
name += ":" + p.second.decode_string();
|
||||
else
|
||||
name += stringf(":%d", p.second.as_int());
|
||||
}
|
||||
|
||||
mkname_a_signed = false;
|
||||
|
|
|
|||
|
|
@ -325,7 +325,7 @@ struct CellTypes
|
|||
|
||||
static RTLIL::Const eval_not(RTLIL::Const v)
|
||||
{
|
||||
for (auto &bit : v.bits)
|
||||
for (auto &bit : v.bits())
|
||||
if (bit == State::S0) bit = State::S1;
|
||||
else if (bit == State::S1) bit = State::S0;
|
||||
return v;
|
||||
|
|
@ -419,13 +419,13 @@ struct CellTypes
|
|||
RTLIL::Const ret;
|
||||
int width = cell->parameters.at(ID::Y_WIDTH).as_int();
|
||||
int offset = cell->parameters.at(ID::OFFSET).as_int();
|
||||
ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
|
||||
ret.bits().insert(ret.bits().end(), arg1.bits().begin()+offset, arg1.bits().begin()+offset+width);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (cell->type == ID($concat)) {
|
||||
RTLIL::Const ret = arg1;
|
||||
ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
|
||||
ret.bits().insert(ret.bits().end(), arg2.bits().begin(), arg2.bits().end());
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -448,7 +448,7 @@ struct CellTypes
|
|||
{
|
||||
int width = cell->parameters.at(ID::WIDTH).as_int();
|
||||
|
||||
std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
|
||||
std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits();
|
||||
while (GetSize(t) < (1 << width))
|
||||
t.push_back(State::S0);
|
||||
t.resize(1 << width);
|
||||
|
|
@ -460,7 +460,7 @@ struct CellTypes
|
|||
{
|
||||
int width = cell->parameters.at(ID::WIDTH).as_int();
|
||||
int depth = cell->parameters.at(ID::DEPTH).as_int();
|
||||
std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
|
||||
std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits();
|
||||
|
||||
while (GetSize(t) < width*depth*2)
|
||||
t.push_back(State::S0);
|
||||
|
|
@ -473,7 +473,7 @@ struct CellTypes
|
|||
bool match_x = true;
|
||||
|
||||
for (int j = 0; j < width; j++) {
|
||||
RTLIL::State a = arg1.bits.at(j);
|
||||
RTLIL::State a = arg1.bits().at(j);
|
||||
if (t.at(2*width*i + 2*j + 0) == State::S1) {
|
||||
if (a == State::S1) match_x = false;
|
||||
if (a != State::S0) match = false;
|
||||
|
|
@ -513,7 +513,7 @@ struct CellTypes
|
|||
if (cell->type == ID($_OAI3_))
|
||||
return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
|
||||
|
||||
log_assert(arg3.bits.size() == 0);
|
||||
log_assert(arg3.size() == 0);
|
||||
return eval(cell, arg1, arg2, errp);
|
||||
}
|
||||
|
||||
|
|
@ -524,7 +524,7 @@ struct CellTypes
|
|||
if (cell->type == ID($_OAI4_))
|
||||
return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
|
||||
|
||||
log_assert(arg4.bits.size() == 0);
|
||||
log_assert(arg4.size() == 0);
|
||||
return eval(cell, arg1, arg2, arg3, errp);
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ struct ConstEval
|
|||
#ifndef NDEBUG
|
||||
RTLIL::SigSpec current_val = values_map(sig);
|
||||
for (int i = 0; i < GetSize(current_val); i++)
|
||||
log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
|
||||
log_assert(current_val[i].wire != NULL || current_val[i] == value.bits()[i]);
|
||||
#endif
|
||||
values_map.add(sig, RTLIL::SigSpec(value));
|
||||
}
|
||||
|
|
@ -115,7 +115,7 @@ struct ConstEval
|
|||
|
||||
for (int i = 0; i < GetSize(coval); i++) {
|
||||
carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);
|
||||
coval.bits[i] = carry ? State::S1 : State::S0;
|
||||
coval.bits()[i] = carry ? State::S1 : State::S0;
|
||||
}
|
||||
|
||||
set(sig_co, coval);
|
||||
|
|
@ -153,7 +153,7 @@ struct ConstEval
|
|||
|
||||
for (int i = 0; i < sig_s.size(); i++)
|
||||
{
|
||||
RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
|
||||
RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits().at(0);
|
||||
RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());
|
||||
|
||||
if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
|
||||
|
|
@ -180,10 +180,10 @@ struct ConstEval
|
|||
|
||||
if (y_values.size() > 1)
|
||||
{
|
||||
std::vector<RTLIL::State> master_bits = y_values.at(0).bits;
|
||||
std::vector<RTLIL::State> master_bits = y_values.at(0).bits();
|
||||
|
||||
for (size_t i = 1; i < y_values.size(); i++) {
|
||||
std::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;
|
||||
std::vector<RTLIL::State> &slave_bits = y_values.at(i).bits();
|
||||
log_assert(master_bits.size() == slave_bits.size());
|
||||
for (size_t j = 0; j < master_bits.size(); j++)
|
||||
if (master_bits[j] != slave_bits[j])
|
||||
|
|
@ -248,8 +248,8 @@ struct ConstEval
|
|||
RTLIL::Const val_x = const_or(t2, t3, false, false, width);
|
||||
|
||||
for (int i = 0; i < GetSize(val_y); i++)
|
||||
if (val_y.bits[i] == RTLIL::Sx)
|
||||
val_x.bits[i] = RTLIL::Sx;
|
||||
if (val_y.bits()[i] == RTLIL::Sx)
|
||||
val_x.bits()[i] = RTLIL::Sx;
|
||||
|
||||
set(sig_y, val_y);
|
||||
set(sig_x, val_x);
|
||||
|
|
|
|||
|
|
@ -298,11 +298,11 @@ FfData FfData::slice(const std::vector<int> &bits) {
|
|||
res.sig_set.append(sig_set[i]);
|
||||
}
|
||||
if (has_arst)
|
||||
res.val_arst.bits.push_back(val_arst[i]);
|
||||
res.val_arst.bits().push_back(val_arst[i]);
|
||||
if (has_srst)
|
||||
res.val_srst.bits.push_back(val_srst[i]);
|
||||
res.val_srst.bits().push_back(val_srst[i]);
|
||||
if (initvals)
|
||||
res.val_init.bits.push_back(val_init[i]);
|
||||
res.val_init.bits().push_back(val_init[i]);
|
||||
}
|
||||
res.width = GetSize(res.sig_q);
|
||||
return res;
|
||||
|
|
@ -760,7 +760,7 @@ void FfData::flip_bits(const pool<int> &bits) {
|
|||
|
||||
Const mask = Const(State::S0, width);
|
||||
for (auto bit: bits)
|
||||
mask.bits[bit] = State::S1;
|
||||
mask.bits()[bit] = State::S1;
|
||||
|
||||
if (has_clk || has_gclk)
|
||||
sig_d = module->Xor(NEW_ID, sig_d, mask);
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ struct FfInitVals
|
|||
{
|
||||
RTLIL::Const res;
|
||||
for (auto bit : sig)
|
||||
res.bits.push_back((*this)(bit));
|
||||
res.bits().push_back((*this)(bit));
|
||||
return res;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -42,9 +42,9 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai
|
|||
ff.sig_d.append(bit);
|
||||
ff.sig_clr.append(State::Sx);
|
||||
ff.sig_set.append(State::Sx);
|
||||
ff.val_init.bits.push_back(State::Sx);
|
||||
ff.val_srst.bits.push_back(State::Sx);
|
||||
ff.val_arst.bits.push_back(State::Sx);
|
||||
ff.val_init.bits().push_back(State::Sx);
|
||||
ff.val_srst.bits().push_back(State::Sx);
|
||||
ff.val_arst.bits().push_back(State::Sx);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -147,9 +147,9 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai
|
|||
ff.sig_q.append(cur_ff.sig_q[idx]);
|
||||
ff.sig_clr.append(ff.has_sr ? cur_ff.sig_clr[idx] : State::S0);
|
||||
ff.sig_set.append(ff.has_sr ? cur_ff.sig_set[idx] : State::S0);
|
||||
ff.val_arst.bits.push_back(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx);
|
||||
ff.val_srst.bits.push_back(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx);
|
||||
ff.val_init.bits.push_back(cur_ff.val_init[idx]);
|
||||
ff.val_arst.bits().push_back(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx);
|
||||
ff.val_srst.bits().push_back(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx);
|
||||
ff.val_init.bits().push_back(cur_ff.val_init[idx]);
|
||||
found = true;
|
||||
}
|
||||
|
||||
|
|
@ -174,9 +174,9 @@ bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair
|
|||
// These two will be fixed up later.
|
||||
ff.sig_clr.append(State::Sx);
|
||||
ff.sig_set.append(State::Sx);
|
||||
ff.val_init.bits.push_back(bit.data);
|
||||
ff.val_srst.bits.push_back(bit.data);
|
||||
ff.val_arst.bits.push_back(bit.data);
|
||||
ff.val_init.bits().push_back(bit.data);
|
||||
ff.val_srst.bits().push_back(bit.data);
|
||||
ff.val_arst.bits().push_back(bit.data);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -274,9 +274,9 @@ bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair
|
|||
ff.sig_q.append(cur_ff.sig_q[idx]);
|
||||
ff.sig_clr.append(ff.has_sr ? cur_ff.sig_clr[idx] : State::S0);
|
||||
ff.sig_set.append(ff.has_sr ? cur_ff.sig_set[idx] : State::S0);
|
||||
ff.val_arst.bits.push_back(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx);
|
||||
ff.val_srst.bits.push_back(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx);
|
||||
ff.val_init.bits.push_back(cur_ff.val_init[idx]);
|
||||
ff.val_arst.bits().push_back(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx);
|
||||
ff.val_srst.bits().push_back(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx);
|
||||
ff.val_init.bits().push_back(cur_ff.val_init[idx]);
|
||||
found = true;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ struct Macc
|
|||
ports.clear();
|
||||
bit_ports = cell->getPort(ID::B);
|
||||
|
||||
std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
|
||||
std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits();
|
||||
int config_cursor = 0;
|
||||
|
||||
int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
|
||||
|
|
@ -199,7 +199,7 @@ struct Macc
|
|||
|
||||
bool eval(RTLIL::Const &result) const
|
||||
{
|
||||
for (auto &bit : result.bits)
|
||||
for (auto &bit : result.bits())
|
||||
bit = State::S0;
|
||||
|
||||
for (auto &port : ports)
|
||||
|
|
|
|||
|
|
@ -157,10 +157,10 @@ void Mem::emit() {
|
|||
}
|
||||
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
|
||||
{
|
||||
rd_wide_continuation.bits.push_back(State(sub != 0));
|
||||
rd_clk_enable.bits.push_back(State(port.clk_enable));
|
||||
rd_clk_polarity.bits.push_back(State(port.clk_polarity));
|
||||
rd_ce_over_srst.bits.push_back(State(port.ce_over_srst));
|
||||
rd_wide_continuation.bits().push_back(State(sub != 0));
|
||||
rd_clk_enable.bits().push_back(State(port.clk_enable));
|
||||
rd_clk_polarity.bits().push_back(State(port.clk_polarity));
|
||||
rd_ce_over_srst.bits().push_back(State(port.ce_over_srst));
|
||||
rd_clk.append(port.clk);
|
||||
rd_arst.append(port.arst);
|
||||
rd_srst.append(port.srst);
|
||||
|
|
@ -170,17 +170,17 @@ void Mem::emit() {
|
|||
rd_addr.append(addr);
|
||||
log_assert(GetSize(addr) == abits);
|
||||
for (auto idx : wr_port_xlat) {
|
||||
rd_transparency_mask.bits.push_back(State(bool(port.transparency_mask[idx])));
|
||||
rd_collision_x_mask.bits.push_back(State(bool(port.collision_x_mask[idx])));
|
||||
rd_transparency_mask.bits().push_back(State(bool(port.transparency_mask[idx])));
|
||||
rd_collision_x_mask.bits().push_back(State(bool(port.collision_x_mask[idx])));
|
||||
}
|
||||
}
|
||||
rd_data.append(port.data);
|
||||
for (auto &bit : port.arst_value)
|
||||
rd_arst_value.bits.push_back(bit);
|
||||
rd_arst_value.bits().push_back(bit);
|
||||
for (auto &bit : port.srst_value)
|
||||
rd_srst_value.bits.push_back(bit);
|
||||
rd_srst_value.bits().push_back(bit);
|
||||
for (auto &bit : port.init_value)
|
||||
rd_init_value.bits.push_back(bit);
|
||||
rd_init_value.bits().push_back(bit);
|
||||
}
|
||||
if (rd_ports.empty()) {
|
||||
rd_wide_continuation = State::S0;
|
||||
|
|
@ -222,12 +222,12 @@ void Mem::emit() {
|
|||
}
|
||||
for (int sub = 0; sub < (1 << port.wide_log2); sub++)
|
||||
{
|
||||
wr_wide_continuation.bits.push_back(State(sub != 0));
|
||||
wr_clk_enable.bits.push_back(State(port.clk_enable));
|
||||
wr_clk_polarity.bits.push_back(State(port.clk_polarity));
|
||||
wr_wide_continuation.bits().push_back(State(sub != 0));
|
||||
wr_clk_enable.bits().push_back(State(port.clk_enable));
|
||||
wr_clk_polarity.bits().push_back(State(port.clk_polarity));
|
||||
wr_clk.append(port.clk);
|
||||
for (auto idx : wr_port_xlat)
|
||||
wr_priority_mask.bits.push_back(State(bool(port.priority_mask[idx])));
|
||||
wr_priority_mask.bits().push_back(State(bool(port.priority_mask[idx])));
|
||||
SigSpec addr = port.sub_addr(sub);
|
||||
addr.extend_u0(abits, false);
|
||||
wr_addr.append(addr);
|
||||
|
|
@ -427,7 +427,7 @@ void Mem::coalesce_inits() {
|
|||
log_assert(offset + GetSize(init.data) <= GetSize(cdata));
|
||||
for (int i = 0; i < GetSize(init.data); i++)
|
||||
if (init.en[i % width] == State::S1)
|
||||
cdata.bits[i+offset] = init.data.bits[i];
|
||||
cdata.bits()[i+offset] = init.data.bits()[i];
|
||||
init.removed = true;
|
||||
}
|
||||
MemInit new_init;
|
||||
|
|
@ -446,7 +446,7 @@ Const Mem::get_init_data() const {
|
|||
int offset = (init.addr.as_int() - start_offset) * width;
|
||||
for (int i = 0; i < GetSize(init.data); i++)
|
||||
if (0 <= i+offset && i+offset < GetSize(init_data) && init.en[i % width] == State::S1)
|
||||
init_data.bits[i+offset] = init.data.bits[i];
|
||||
init_data.bits()[i+offset] = init.data.bits()[i];
|
||||
}
|
||||
return init_data;
|
||||
}
|
||||
|
|
|
|||
290
kernel/rtlil.cc
290
kernel/rtlil.cc
|
|
@ -202,23 +202,16 @@ const pool<IdString> &RTLIL::builtin_ff_cell_types() {
|
|||
|
||||
RTLIL::Const::Const(const std::string &str)
|
||||
{
|
||||
flags = RTLIL::CONST_FLAG_STRING;
|
||||
bits.reserve(str.size() * 8);
|
||||
for (int i = str.size()-1; i >= 0; i--) {
|
||||
unsigned char ch = str[i];
|
||||
for (int j = 0; j < 8; j++) {
|
||||
bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
|
||||
ch = ch >> 1;
|
||||
}
|
||||
}
|
||||
flags = RTLIL::CONST_FLAG_STRING | CONST_FLAG_STRING_COMPACT;
|
||||
this->str = str;
|
||||
}
|
||||
|
||||
RTLIL::Const::Const(int val, int width)
|
||||
{
|
||||
flags = RTLIL::CONST_FLAG_NONE;
|
||||
bits.reserve(width);
|
||||
bits_.reserve(width);
|
||||
for (int i = 0; i < width; i++) {
|
||||
bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
|
||||
bits_.push_back((val & 1) != 0 ? State::S1 : State::S0);
|
||||
val = val >> 1;
|
||||
}
|
||||
}
|
||||
|
|
@ -226,65 +219,115 @@ RTLIL::Const::Const(int val, int width)
|
|||
RTLIL::Const::Const(RTLIL::State bit, int width)
|
||||
{
|
||||
flags = RTLIL::CONST_FLAG_NONE;
|
||||
bits.reserve(width);
|
||||
bits_.reserve(width);
|
||||
for (int i = 0; i < width; i++)
|
||||
bits.push_back(bit);
|
||||
bits_.push_back(bit);
|
||||
}
|
||||
|
||||
RTLIL::Const::Const(const std::vector<bool> &bits)
|
||||
{
|
||||
flags = RTLIL::CONST_FLAG_NONE;
|
||||
this->bits.reserve(bits.size());
|
||||
this->bits_.reserve(bits.size());
|
||||
for (const auto &b : bits)
|
||||
this->bits.emplace_back(b ? State::S1 : State::S0);
|
||||
this->bits_.emplace_back(b ? State::S1 : State::S0);
|
||||
}
|
||||
|
||||
bool RTLIL::Const::operator <(const RTLIL::Const &other) const
|
||||
{
|
||||
if (bits.size() != other.bits.size())
|
||||
return bits.size() < other.bits.size();
|
||||
for (size_t i = 0; i < bits.size(); i++)
|
||||
if (bits[i] != other.bits[i])
|
||||
return bits[i] < other.bits[i];
|
||||
if ((flags & CONST_FLAG_STRING_COMPACT) != (other.flags & CONST_FLAG_STRING_COMPACT))
|
||||
return decode_string() < other.decode_string();
|
||||
|
||||
if (flags & CONST_FLAG_STRING_COMPACT)
|
||||
return str < other.str;
|
||||
|
||||
if (bits_.size() != other.bits_.size())
|
||||
return bits_.size() < other.bits_.size();
|
||||
for (size_t i = 0; i < bits_.size(); i++)
|
||||
if (bits_[i] != other.bits_[i])
|
||||
return bits_[i] < other.bits_[i];
|
||||
return false;
|
||||
}
|
||||
|
||||
bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
|
||||
{
|
||||
return bits == other.bits;
|
||||
if ((flags & CONST_FLAG_STRING_COMPACT) != (other.flags & CONST_FLAG_STRING_COMPACT))
|
||||
return decode_string() == other.decode_string();
|
||||
|
||||
if (flags & CONST_FLAG_STRING_COMPACT)
|
||||
return str == other.str;
|
||||
return bits_ == other.bits_;
|
||||
}
|
||||
|
||||
bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
|
||||
{
|
||||
return bits != other.bits;
|
||||
if ((flags & CONST_FLAG_STRING_COMPACT) != (other.flags & CONST_FLAG_STRING_COMPACT))
|
||||
return decode_string() != other.decode_string();
|
||||
|
||||
if (flags & CONST_FLAG_STRING_COMPACT)
|
||||
return str != other.str;
|
||||
return bits_ != other.bits_;
|
||||
}
|
||||
|
||||
std::vector<RTLIL::State>& RTLIL::Const::bits()
|
||||
{
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
return bits_;
|
||||
}
|
||||
|
||||
const std::vector<RTLIL::State>& RTLIL::Const::bits() const
|
||||
{
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
return bits_;
|
||||
}
|
||||
|
||||
|
||||
std::vector<RTLIL::State> RTLIL::Const::to_bits() const
|
||||
{
|
||||
if (!(flags & CONST_FLAG_STRING_COMPACT)) {
|
||||
return bits_;
|
||||
}
|
||||
|
||||
std::vector<RTLIL::State> b;
|
||||
b.reserve(str.size() * 8);
|
||||
for (int i = str.size()-1; i >= 0; i--) {
|
||||
unsigned char ch = str[i];
|
||||
for (int j = 0; j < 8; j++) {
|
||||
b.push_back((ch & 1) != 0 ? State::S1 : State::S0);
|
||||
ch = ch >> 1;
|
||||
}
|
||||
}
|
||||
return b;
|
||||
}
|
||||
|
||||
bool RTLIL::Const::as_bool() const
|
||||
{
|
||||
for (size_t i = 0; i < bits.size(); i++)
|
||||
if (bits[i] == State::S1)
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
for (size_t i = 0; i < bits_.size(); i++)
|
||||
if (bits_[i] == State::S1)
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
int RTLIL::Const::as_int(bool is_signed) const
|
||||
{
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
int32_t ret = 0;
|
||||
for (size_t i = 0; i < bits.size() && i < 32; i++)
|
||||
if (bits[i] == State::S1)
|
||||
for (size_t i = 0; i < bits_.size() && i < 32; i++)
|
||||
if (bits_[i] == State::S1)
|
||||
ret |= 1 << i;
|
||||
if (is_signed && bits.back() == State::S1)
|
||||
for (size_t i = bits.size(); i < 32; i++)
|
||||
if (is_signed && bits_.back() == State::S1)
|
||||
for (size_t i = bits_.size(); i < 32; i++)
|
||||
ret |= 1 << i;
|
||||
return ret;
|
||||
}
|
||||
|
||||
std::string RTLIL::Const::as_string() const
|
||||
{
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
std::string ret;
|
||||
ret.reserve(bits.size());
|
||||
for (size_t i = bits.size(); i > 0; i--)
|
||||
switch (bits[i-1]) {
|
||||
ret.reserve(bits_.size());
|
||||
for (size_t i = bits_.size(); i > 0; i--)
|
||||
switch (bits_[i-1]) {
|
||||
case S0: ret += "0"; break;
|
||||
case S1: ret += "1"; break;
|
||||
case Sx: ret += "x"; break;
|
||||
|
|
@ -298,22 +341,25 @@ std::string RTLIL::Const::as_string() const
|
|||
RTLIL::Const RTLIL::Const::from_string(const std::string &str)
|
||||
{
|
||||
Const c;
|
||||
c.bits.reserve(str.size());
|
||||
c.bits_.reserve(str.size());
|
||||
for (auto it = str.rbegin(); it != str.rend(); it++)
|
||||
switch (*it) {
|
||||
case '0': c.bits.push_back(State::S0); break;
|
||||
case '1': c.bits.push_back(State::S1); break;
|
||||
case 'x': c.bits.push_back(State::Sx); break;
|
||||
case 'z': c.bits.push_back(State::Sz); break;
|
||||
case 'm': c.bits.push_back(State::Sm); break;
|
||||
default: c.bits.push_back(State::Sa);
|
||||
case '0': c.bits_.push_back(State::S0); break;
|
||||
case '1': c.bits_.push_back(State::S1); break;
|
||||
case 'x': c.bits_.push_back(State::Sx); break;
|
||||
case 'z': c.bits_.push_back(State::Sz); break;
|
||||
case 'm': c.bits_.push_back(State::Sm); break;
|
||||
default: c.bits_.push_back(State::Sa);
|
||||
}
|
||||
return c;
|
||||
}
|
||||
|
||||
std::string RTLIL::Const::decode_string() const
|
||||
{
|
||||
const int n = GetSize(bits);
|
||||
if (flags & CONST_FLAG_STRING_COMPACT)
|
||||
return str;
|
||||
|
||||
const int n = GetSize(bits_);
|
||||
const int n_over_8 = n / 8;
|
||||
std::string s;
|
||||
s.reserve(n_over_8);
|
||||
|
|
@ -321,7 +367,7 @@ std::string RTLIL::Const::decode_string() const
|
|||
if (i < n) {
|
||||
char ch = 0;
|
||||
for (int j = 0; j < (n - i); j++) {
|
||||
if (bits[i + j] == RTLIL::State::S1) {
|
||||
if (bits_[i + j] == RTLIL::State::S1) {
|
||||
ch |= 1 << j;
|
||||
}
|
||||
}
|
||||
|
|
@ -332,7 +378,7 @@ std::string RTLIL::Const::decode_string() const
|
|||
for (; i >= 0; i -= 8) {
|
||||
char ch = 0;
|
||||
for (int j = 0; j < 8; j++) {
|
||||
if (bits[i + j] == RTLIL::State::S1) {
|
||||
if (bits_[i + j] == RTLIL::State::S1) {
|
||||
ch |= 1 << j;
|
||||
}
|
||||
}
|
||||
|
|
@ -344,9 +390,10 @@ std::string RTLIL::Const::decode_string() const
|
|||
|
||||
bool RTLIL::Const::is_fully_zero() const
|
||||
{
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
cover("kernel.rtlil.const.is_fully_zero");
|
||||
|
||||
for (const auto &bit : bits)
|
||||
for (const auto &bit : bits_)
|
||||
if (bit != RTLIL::State::S0)
|
||||
return false;
|
||||
|
||||
|
|
@ -355,9 +402,10 @@ bool RTLIL::Const::is_fully_zero() const
|
|||
|
||||
bool RTLIL::Const::is_fully_ones() const
|
||||
{
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
cover("kernel.rtlil.const.is_fully_ones");
|
||||
|
||||
for (const auto &bit : bits)
|
||||
for (const auto &bit : bits_)
|
||||
if (bit != RTLIL::State::S1)
|
||||
return false;
|
||||
|
||||
|
|
@ -368,7 +416,10 @@ bool RTLIL::Const::is_fully_def() const
|
|||
{
|
||||
cover("kernel.rtlil.const.is_fully_def");
|
||||
|
||||
for (const auto &bit : bits)
|
||||
if (flags & CONST_FLAG_STRING_COMPACT)
|
||||
return true;
|
||||
|
||||
for (const auto &bit : bits_)
|
||||
if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
|
||||
return false;
|
||||
|
||||
|
|
@ -379,7 +430,10 @@ bool RTLIL::Const::is_fully_undef() const
|
|||
{
|
||||
cover("kernel.rtlil.const.is_fully_undef");
|
||||
|
||||
for (const auto &bit : bits)
|
||||
if (flags & CONST_FLAG_STRING_COMPACT)
|
||||
return false;
|
||||
|
||||
for (const auto &bit : bits_)
|
||||
if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
|
||||
return false;
|
||||
|
||||
|
|
@ -390,7 +444,10 @@ bool RTLIL::Const::is_fully_undef_x_only() const
|
|||
{
|
||||
cover("kernel.rtlil.const.is_fully_undef_x_only");
|
||||
|
||||
for (const auto &bit : bits)
|
||||
if (flags & CONST_FLAG_STRING_COMPACT)
|
||||
return false;
|
||||
|
||||
for (const auto &bit : bits_)
|
||||
if (bit != RTLIL::State::Sx)
|
||||
return false;
|
||||
|
||||
|
|
@ -401,9 +458,12 @@ bool RTLIL::Const::is_onehot(int *pos) const
|
|||
{
|
||||
cover("kernel.rtlil.const.is_onehot");
|
||||
|
||||
if (flags & CONST_FLAG_STRING_COMPACT)
|
||||
return false;
|
||||
|
||||
bool found = false;
|
||||
for (int i = 0; i < GetSize(*this); i++) {
|
||||
auto &bit = bits[i];
|
||||
auto &bit = bits_[i];
|
||||
if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
|
||||
return false;
|
||||
if (bit == RTLIL::State::S1) {
|
||||
|
|
@ -1034,6 +1094,14 @@ namespace {
|
|||
cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
|
||||
}
|
||||
|
||||
void is_param(const RTLIL::IdString& name)
|
||||
{
|
||||
auto it = cell->parameters.find(name);
|
||||
if (it == cell->parameters.end())
|
||||
error(__LINE__);
|
||||
expected_params.insert(name);
|
||||
}
|
||||
|
||||
int param(const RTLIL::IdString& name)
|
||||
{
|
||||
auto it = cell->parameters.find(name);
|
||||
|
|
@ -1063,14 +1131,14 @@ namespace {
|
|||
|
||||
void param_bits(const RTLIL::IdString& name, int width)
|
||||
{
|
||||
param(name);
|
||||
if (GetSize(cell->parameters.at(name).bits) != width)
|
||||
is_param(name);
|
||||
if (GetSize(cell->parameters.at(name).bits()) != width)
|
||||
error(__LINE__);
|
||||
}
|
||||
|
||||
std::string param_string(const RTLIL::IdString &name)
|
||||
{
|
||||
param(name);
|
||||
is_param(name);
|
||||
return cell->parameters.at(name).decode_string();
|
||||
}
|
||||
|
||||
|
|
@ -1212,8 +1280,8 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($macc)) {
|
||||
param(ID::CONFIG);
|
||||
param(ID::CONFIG_WIDTH);
|
||||
is_param(ID::CONFIG);
|
||||
is_param(ID::CONFIG_WIDTH);
|
||||
port(ID::A, param(ID::A_WIDTH));
|
||||
port(ID::B, param(ID::B_WIDTH));
|
||||
port(ID::Y, param(ID::Y_WIDTH));
|
||||
|
|
@ -1241,7 +1309,7 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($slice)) {
|
||||
param(ID::OFFSET);
|
||||
is_param(ID::OFFSET);
|
||||
port(ID::A, param(ID::A_WIDTH));
|
||||
port(ID::Y, param(ID::Y_WIDTH));
|
||||
if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
|
||||
|
|
@ -1293,7 +1361,7 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($lut)) {
|
||||
param(ID::LUT);
|
||||
is_param(ID::LUT);
|
||||
port(ID::A, param(ID::WIDTH));
|
||||
port(ID::Y, 1);
|
||||
check_expected();
|
||||
|
|
@ -1301,8 +1369,8 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($sop)) {
|
||||
param(ID::DEPTH);
|
||||
param(ID::TABLE);
|
||||
is_param(ID::DEPTH);
|
||||
is_param(ID::TABLE);
|
||||
port(ID::A, param(ID::WIDTH));
|
||||
port(ID::Y, 1);
|
||||
check_expected();
|
||||
|
|
@ -1487,15 +1555,15 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($fsm)) {
|
||||
param(ID::NAME);
|
||||
is_param(ID::NAME);
|
||||
param_bool(ID::CLK_POLARITY);
|
||||
param_bool(ID::ARST_POLARITY);
|
||||
param(ID::STATE_BITS);
|
||||
param(ID::STATE_NUM);
|
||||
param(ID::STATE_NUM_LOG2);
|
||||
param(ID::STATE_RST);
|
||||
is_param(ID::STATE_BITS);
|
||||
is_param(ID::STATE_NUM);
|
||||
is_param(ID::STATE_NUM_LOG2);
|
||||
is_param(ID::STATE_RST);
|
||||
param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
|
||||
param(ID::TRANS_NUM);
|
||||
is_param(ID::TRANS_NUM);
|
||||
param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
|
||||
port(ID::CLK, 1);
|
||||
port(ID::ARST, 1);
|
||||
|
|
@ -1506,7 +1574,7 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($memrd)) {
|
||||
param(ID::MEMID);
|
||||
is_param(ID::MEMID);
|
||||
param_bool(ID::CLK_ENABLE);
|
||||
param_bool(ID::CLK_POLARITY);
|
||||
param_bool(ID::TRANSPARENT);
|
||||
|
|
@ -1519,11 +1587,11 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($memrd_v2)) {
|
||||
param(ID::MEMID);
|
||||
is_param(ID::MEMID);
|
||||
param_bool(ID::CLK_ENABLE);
|
||||
param_bool(ID::CLK_POLARITY);
|
||||
param(ID::TRANSPARENCY_MASK);
|
||||
param(ID::COLLISION_X_MASK);
|
||||
is_param(ID::TRANSPARENCY_MASK);
|
||||
is_param(ID::COLLISION_X_MASK);
|
||||
param_bool(ID::CE_OVER_SRST);
|
||||
param_bits(ID::ARST_VALUE, param(ID::WIDTH));
|
||||
param_bits(ID::SRST_VALUE, param(ID::WIDTH));
|
||||
|
|
@ -1539,10 +1607,10 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($memwr)) {
|
||||
param(ID::MEMID);
|
||||
is_param(ID::MEMID);
|
||||
param_bool(ID::CLK_ENABLE);
|
||||
param_bool(ID::CLK_POLARITY);
|
||||
param(ID::PRIORITY);
|
||||
is_param(ID::PRIORITY);
|
||||
port(ID::CLK, 1);
|
||||
port(ID::EN, param(ID::WIDTH));
|
||||
port(ID::ADDR, param(ID::ABITS));
|
||||
|
|
@ -1552,11 +1620,11 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($memwr_v2)) {
|
||||
param(ID::MEMID);
|
||||
is_param(ID::MEMID);
|
||||
param_bool(ID::CLK_ENABLE);
|
||||
param_bool(ID::CLK_POLARITY);
|
||||
param(ID::PORTID);
|
||||
param(ID::PRIORITY_MASK);
|
||||
is_param(ID::PORTID);
|
||||
is_param(ID::PRIORITY_MASK);
|
||||
port(ID::CLK, 1);
|
||||
port(ID::EN, param(ID::WIDTH));
|
||||
port(ID::ADDR, param(ID::ABITS));
|
||||
|
|
@ -1566,8 +1634,8 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($meminit)) {
|
||||
param(ID::MEMID);
|
||||
param(ID::PRIORITY);
|
||||
is_param(ID::MEMID);
|
||||
is_param(ID::PRIORITY);
|
||||
port(ID::ADDR, param(ID::ABITS));
|
||||
port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
|
||||
check_expected();
|
||||
|
|
@ -1575,8 +1643,8 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($meminit_v2)) {
|
||||
param(ID::MEMID);
|
||||
param(ID::PRIORITY);
|
||||
is_param(ID::MEMID);
|
||||
is_param(ID::PRIORITY);
|
||||
port(ID::ADDR, param(ID::ABITS));
|
||||
port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
|
||||
port(ID::EN, param(ID::WIDTH));
|
||||
|
|
@ -1585,10 +1653,10 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($mem)) {
|
||||
param(ID::MEMID);
|
||||
param(ID::SIZE);
|
||||
param(ID::OFFSET);
|
||||
param(ID::INIT);
|
||||
is_param(ID::MEMID);
|
||||
is_param(ID::SIZE);
|
||||
is_param(ID::OFFSET);
|
||||
is_param(ID::INIT);
|
||||
param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
|
||||
param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
|
||||
param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
|
||||
|
|
@ -1607,10 +1675,10 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($mem_v2)) {
|
||||
param(ID::MEMID);
|
||||
param(ID::SIZE);
|
||||
param(ID::OFFSET);
|
||||
param(ID::INIT);
|
||||
is_param(ID::MEMID);
|
||||
is_param(ID::SIZE);
|
||||
is_param(ID::OFFSET);
|
||||
is_param(ID::INIT);
|
||||
param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
|
||||
param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
|
||||
param_bits(ID::RD_TRANSPARENCY_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
|
||||
|
|
@ -1701,12 +1769,12 @@ namespace {
|
|||
param_bool(ID::FULL);
|
||||
param_bool(ID::SRC_DST_PEN);
|
||||
param_bool(ID::SRC_DST_POL);
|
||||
param(ID::T_RISE_MIN);
|
||||
param(ID::T_RISE_TYP);
|
||||
param(ID::T_RISE_MAX);
|
||||
param(ID::T_FALL_MIN);
|
||||
param(ID::T_FALL_TYP);
|
||||
param(ID::T_FALL_MAX);
|
||||
is_param(ID::T_RISE_MIN);
|
||||
is_param(ID::T_RISE_TYP);
|
||||
is_param(ID::T_RISE_MAX);
|
||||
is_param(ID::T_FALL_MIN);
|
||||
is_param(ID::T_FALL_TYP);
|
||||
is_param(ID::T_FALL_MAX);
|
||||
port(ID::EN, 1);
|
||||
port(ID::SRC, param(ID::SRC_WIDTH));
|
||||
port(ID::DST, param(ID::DST_WIDTH));
|
||||
|
|
@ -1722,17 +1790,17 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($specrule)) {
|
||||
param(ID::TYPE);
|
||||
is_param(ID::TYPE);
|
||||
param_bool(ID::SRC_PEN);
|
||||
param_bool(ID::SRC_POL);
|
||||
param_bool(ID::DST_PEN);
|
||||
param_bool(ID::DST_POL);
|
||||
param(ID::T_LIMIT_MIN);
|
||||
param(ID::T_LIMIT_TYP);
|
||||
param(ID::T_LIMIT_MAX);
|
||||
param(ID::T_LIMIT2_MIN);
|
||||
param(ID::T_LIMIT2_TYP);
|
||||
param(ID::T_LIMIT2_MAX);
|
||||
is_param(ID::T_LIMIT_MIN);
|
||||
is_param(ID::T_LIMIT_TYP);
|
||||
is_param(ID::T_LIMIT_MAX);
|
||||
is_param(ID::T_LIMIT2_MIN);
|
||||
is_param(ID::T_LIMIT2_TYP);
|
||||
is_param(ID::T_LIMIT2_MAX);
|
||||
port(ID::SRC_EN, 1);
|
||||
port(ID::DST_EN, 1);
|
||||
port(ID::SRC, param(ID::SRC_WIDTH));
|
||||
|
|
@ -1742,10 +1810,10 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($print)) {
|
||||
param(ID(FORMAT));
|
||||
is_param(ID(FORMAT));
|
||||
param_bool(ID::TRG_ENABLE);
|
||||
param(ID::TRG_POLARITY);
|
||||
param(ID::PRIORITY);
|
||||
is_param(ID::TRG_POLARITY);
|
||||
is_param(ID::PRIORITY);
|
||||
port(ID::EN, 1);
|
||||
port(ID::TRG, param(ID::TRG_WIDTH));
|
||||
port(ID::ARGS, param(ID::ARGS_WIDTH));
|
||||
|
|
@ -1757,10 +1825,10 @@ namespace {
|
|||
std::string flavor = param_string(ID(FLAVOR));
|
||||
if (!(flavor == "assert" || flavor == "assume" || flavor == "live" || flavor == "fair" || flavor == "cover"))
|
||||
error(__LINE__);
|
||||
param(ID(FORMAT));
|
||||
is_param(ID(FORMAT));
|
||||
param_bool(ID::TRG_ENABLE);
|
||||
param(ID::TRG_POLARITY);
|
||||
param(ID::PRIORITY);
|
||||
is_param(ID::TRG_POLARITY);
|
||||
is_param(ID::PRIORITY);
|
||||
port(ID::A, 1);
|
||||
port(ID::EN, 1);
|
||||
port(ID::TRG, param(ID::TRG_WIDTH));
|
||||
|
|
@ -1770,7 +1838,7 @@ namespace {
|
|||
}
|
||||
|
||||
if (cell->type == ID($scopeinfo)) {
|
||||
param(ID::TYPE);
|
||||
is_param(ID::TYPE);
|
||||
check_expected();
|
||||
std::string scope_type = cell->getParam(ID::TYPE).decode_string();
|
||||
if (scope_type != "module" && scope_type != "struct")
|
||||
|
|
@ -1875,8 +1943,8 @@ namespace {
|
|||
{ port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
|
||||
|
||||
if (cell->type.in(ID($set_tag))) {
|
||||
param(ID::WIDTH);
|
||||
param(ID::TAG);
|
||||
is_param(ID::WIDTH);
|
||||
is_param(ID::TAG);
|
||||
port(ID::A, param(ID::WIDTH));
|
||||
port(ID::SET, param(ID::WIDTH));
|
||||
port(ID::CLR, param(ID::WIDTH));
|
||||
|
|
@ -1885,16 +1953,16 @@ namespace {
|
|||
return;
|
||||
}
|
||||
if (cell->type.in(ID($get_tag),ID($original_tag))) {
|
||||
param(ID::WIDTH);
|
||||
param(ID::TAG);
|
||||
is_param(ID::WIDTH);
|
||||
is_param(ID::TAG);
|
||||
port(ID::A, param(ID::WIDTH));
|
||||
port(ID::Y, param(ID::WIDTH));
|
||||
check_expected();
|
||||
return;
|
||||
}
|
||||
if (cell->type.in(ID($overwrite_tag))) {
|
||||
param(ID::WIDTH);
|
||||
param(ID::TAG);
|
||||
is_param(ID::WIDTH);
|
||||
is_param(ID::TAG);
|
||||
port(ID::A, param(ID::WIDTH));
|
||||
port(ID::SET, param(ID::WIDTH));
|
||||
port(ID::CLR, param(ID::WIDTH));
|
||||
|
|
@ -1902,7 +1970,7 @@ namespace {
|
|||
return;
|
||||
}
|
||||
if (cell->type.in(ID($future_ff))) {
|
||||
param(ID::WIDTH);
|
||||
is_param(ID::WIDTH);
|
||||
port(ID::A, param(ID::WIDTH));
|
||||
port(ID::Y, param(ID::WIDTH));
|
||||
check_expected();
|
||||
|
|
@ -3730,7 +3798,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
|
|||
wire = bit.wire;
|
||||
offset = 0;
|
||||
if (wire == NULL)
|
||||
data = RTLIL::Const(bit.data).bits;
|
||||
data = RTLIL::Const(bit.data).bits();
|
||||
else
|
||||
offset = bit.offset;
|
||||
width = 1;
|
||||
|
|
|
|||
|
|
@ -50,8 +50,9 @@ namespace RTLIL
|
|||
enum ConstFlags : unsigned char {
|
||||
CONST_FLAG_NONE = 0,
|
||||
CONST_FLAG_STRING = 1,
|
||||
CONST_FLAG_SIGNED = 2, // only used for parameters
|
||||
CONST_FLAG_REAL = 4 // only used for parameters
|
||||
CONST_FLAG_STRING_COMPACT = 2, // internally efficient string storage
|
||||
CONST_FLAG_SIGNED = 4, // only used for parameters
|
||||
CONST_FLAG_REAL = 8, // only used for parameters
|
||||
};
|
||||
|
||||
struct Const;
|
||||
|
|
@ -657,14 +658,18 @@ namespace RTLIL
|
|||
|
||||
struct RTLIL::Const
|
||||
{
|
||||
private:
|
||||
// TODO unionize
|
||||
std::vector<RTLIL::State> bits_;
|
||||
std::string str; // active on CONST_FLAG_STRING_COMPACT
|
||||
public:
|
||||
int flags;
|
||||
std::vector<RTLIL::State> bits;
|
||||
|
||||
Const() : flags(RTLIL::CONST_FLAG_NONE) {}
|
||||
Const(const std::string &str);
|
||||
Const(int val, int width = 32);
|
||||
Const(RTLIL::State bit, int width = 1);
|
||||
Const(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }
|
||||
Const(const std::vector<RTLIL::State> &bits) : bits_(bits) { flags = CONST_FLAG_NONE; }
|
||||
Const(const std::vector<bool> &bits);
|
||||
Const(const RTLIL::Const &c) = default;
|
||||
RTLIL::Const &operator =(const RTLIL::Const &other) = default;
|
||||
|
|
@ -673,19 +678,22 @@ struct RTLIL::Const
|
|||
bool operator ==(const RTLIL::Const &other) const;
|
||||
bool operator !=(const RTLIL::Const &other) const;
|
||||
|
||||
const std::vector<RTLIL::State>& bits() const;
|
||||
std::vector<RTLIL::State>& bits();
|
||||
bool as_bool() const;
|
||||
int as_int(bool is_signed = false) const;
|
||||
std::string as_string() const;
|
||||
static Const from_string(const std::string &str);
|
||||
std::vector<RTLIL::State> to_bits() const;
|
||||
|
||||
std::string decode_string() const;
|
||||
|
||||
inline int size() const { return bits.size(); }
|
||||
inline bool empty() const { return bits.empty(); }
|
||||
inline RTLIL::State &operator[](int index) { return bits.at(index); }
|
||||
inline const RTLIL::State &operator[](int index) const { return bits.at(index); }
|
||||
inline decltype(bits)::iterator begin() { return bits.begin(); }
|
||||
inline decltype(bits)::iterator end() { return bits.end(); }
|
||||
// (flags & CONST_FLAG_STRING_COMPACT) ? : ;
|
||||
inline size_t size() const { return (flags & CONST_FLAG_STRING_COMPACT) ? 8 * str.size() : bits_.size(); }
|
||||
inline bool empty() const { return (flags & CONST_FLAG_STRING_COMPACT) ? str.empty() : bits_.empty(); }
|
||||
inline RTLIL::State &operator[](int index) { log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); return bits_.at(index); }
|
||||
inline const RTLIL::State &operator[](int index) const { log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); return bits_.at(index); }
|
||||
inline decltype(bits_)::iterator begin() { log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); return bits_.begin(); }
|
||||
inline decltype(bits_)::iterator end() { log_assert(!(flags & CONST_FLAG_STRING_COMPACT)); return bits_.end(); }
|
||||
|
||||
bool is_fully_zero() const;
|
||||
bool is_fully_ones() const;
|
||||
|
|
@ -695,25 +703,34 @@ struct RTLIL::Const
|
|||
bool is_onehot(int *pos = nullptr) const;
|
||||
|
||||
inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
RTLIL::Const ret;
|
||||
ret.bits.reserve(len);
|
||||
ret.bits_.reserve(len);
|
||||
for (int i = offset; i < offset + len; i++)
|
||||
ret.bits.push_back(i < GetSize(bits) ? bits[i] : padding);
|
||||
ret.bits_.push_back(i < GetSize(bits_) ? bits_[i] : padding);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void extu(int width) {
|
||||
bits.resize(width, RTLIL::State::S0);
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
bits_.resize(width, RTLIL::State::S0);
|
||||
}
|
||||
|
||||
void exts(int width) {
|
||||
bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());
|
||||
log_assert(!(flags & CONST_FLAG_STRING_COMPACT));
|
||||
bits_.resize(width, bits_.empty() ? RTLIL::State::Sx : bits_.back());
|
||||
}
|
||||
|
||||
inline unsigned int hash() const {
|
||||
unsigned int h = mkhash_init;
|
||||
for (auto b : bits)
|
||||
h = mkhash(h, b);
|
||||
|
||||
if(flags & CONST_FLAG_STRING_COMPACT) {
|
||||
for (auto c : str)
|
||||
h = mkhash(h, c);
|
||||
} else {
|
||||
for (auto b : bits_)
|
||||
h = mkhash(h, b);
|
||||
}
|
||||
return h;
|
||||
}
|
||||
};
|
||||
|
|
@ -759,8 +776,8 @@ struct RTLIL::SigChunk
|
|||
int width, offset;
|
||||
|
||||
SigChunk() : wire(nullptr), width(0), offset(0) {}
|
||||
SigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {}
|
||||
SigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {}
|
||||
SigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}
|
||||
SigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}
|
||||
SigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}
|
||||
SigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}
|
||||
SigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}
|
||||
|
|
|
|||
|
|
@ -922,7 +922,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
|
|||
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
|
||||
|
||||
std::vector<int> lut;
|
||||
for (auto bit : cell->getParam(ID::LUT).bits)
|
||||
for (auto bit : cell->getParam(ID::LUT).bits())
|
||||
lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
|
||||
while (GetSize(lut) < (1 << GetSize(a)))
|
||||
lut.push_back(ez->CONST_FALSE);
|
||||
|
|
@ -974,7 +974,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
|
|||
int width = cell->getParam(ID::WIDTH).as_int();
|
||||
int depth = cell->getParam(ID::DEPTH).as_int();
|
||||
|
||||
vector<State> table_raw = cell->getParam(ID::TABLE).bits;
|
||||
vector<State> table_raw = cell->getParam(ID::TABLE).bits();
|
||||
while (GetSize(table_raw) < 2*width*depth)
|
||||
table_raw.push_back(State::S0);
|
||||
|
||||
|
|
|
|||
|
|
@ -1126,40 +1126,31 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi
|
|||
design = yosys_design;
|
||||
|
||||
if (command == "auto") {
|
||||
std::string filename_trim = filename;
|
||||
|
||||
auto has_extension = [](const std::string& filename, const std::string& extension) {
|
||||
if (filename.size() >= extension.size()) {
|
||||
return filename.compare(filename.size() - extension.size(), extension.size(), extension) == 0;
|
||||
}
|
||||
return false;
|
||||
};
|
||||
|
||||
if (has_extension(filename_trim, ".gz")) {
|
||||
filename_trim.erase(filename_trim.size() - 3);
|
||||
}
|
||||
|
||||
if (has_extension(filename_trim, ".v")) {
|
||||
command = " -vlog2k";
|
||||
} else if (has_extension(filename_trim, ".sv")) {
|
||||
command = " -sv";
|
||||
} else if (has_extension(filename_trim, ".vhd") || has_extension(filename_trim, ".vhdl")) {
|
||||
command = " -vhdl";
|
||||
} else if (has_extension(filename_trim, ".blif") || has_extension(filename_trim, ".eblif")) {
|
||||
command = "blif";
|
||||
} else if (has_extension(filename_trim, ".json")) {
|
||||
command = "json";
|
||||
} else if (has_extension(filename_trim, ".il")) {
|
||||
command = "rtlil";
|
||||
} else if (has_extension(filename_trim, ".ys")) {
|
||||
command = "script";
|
||||
} else if (has_extension(filename_trim, ".tcl")) {
|
||||
command = "tcl";
|
||||
} else if (filename == "-") {
|
||||
command = "script";
|
||||
} else {
|
||||
log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str());
|
||||
}
|
||||
std::string filename_trim = filename;
|
||||
if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".gz") == 0)
|
||||
filename_trim.erase(filename_trim.size()-3);
|
||||
if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-2, std::string::npos, ".v") == 0)
|
||||
command = " -vlog2k";
|
||||
else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0)
|
||||
command = " -sv";
|
||||
else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0)
|
||||
command = " -vhdl";
|
||||
else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0)
|
||||
command = "blif";
|
||||
else if (filename_trim.size() > 5 && filename_trim.compare(filename_trim.size()-6, std::string::npos, ".eblif") == 0)
|
||||
command = "blif";
|
||||
else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0)
|
||||
command = "json";
|
||||
else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0)
|
||||
command = "rtlil";
|
||||
else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0)
|
||||
command = "script";
|
||||
else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0)
|
||||
command = "tcl";
|
||||
else if (filename == "-")
|
||||
command = "script";
|
||||
else
|
||||
log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str());
|
||||
}
|
||||
|
||||
if (command == "script")
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const
|
|||
const std::string &bits = steps[t].bits;
|
||||
|
||||
RTLIL::Const result(State::Sa, width);
|
||||
result.bits.reserve(width);
|
||||
result.bits().reserve(width);
|
||||
|
||||
int read_begin = GetSize(bits) - 1 - bits_offset;
|
||||
int read_end = max(-1, read_begin - width);
|
||||
|
|
@ -200,7 +200,7 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const
|
|||
default:
|
||||
log_abort();
|
||||
}
|
||||
result.bits[j] = bit;
|
||||
result.bits()[j] = bit;
|
||||
}
|
||||
|
||||
return result;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue