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const: represent string constants as string, assert not accessed as bits

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This commit is contained in:
Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
parent 960bca0196
commit 498e0498c5
81 changed files with 764 additions and 690 deletions
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26
frontends/verific/verific.cc
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@ -237,19 +237,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
RTLIL::Const mkconst_str(const std::string &str)
{
RTLIL::Const val;
std::vector<RTLIL::State> data;
data.reserve(str.size() * 8);
for (size_t i = 0; i < str.size(); i++) {
unsigned char ch = str[str.size() - i - 1];
for (int j = 0; j < 8; j++) {
data.push_back((ch & 1) ? State::S1 : State::S0);
ch = ch >> 1;
}
}
val.bits = data;
val.flags |= RTLIL::CONST_FLAG_STRING;
return val;
return RTLIL::Const(str);
}
static const RTLIL::Const extract_vhdl_boolean(std::string &val)
@ -1742,9 +1730,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (init_nets.count(net)) {
if (init_nets.at(net) == '0')
initval.bits.at(bitidx) = State::S0;
initval.bits().at(bitidx) = State::S0;
if (init_nets.at(net) == '1')
initval.bits.at(bitidx) = State::S1;
initval.bits().at(bitidx) = State::S1;
initval_valid = true;
init_nets.erase(net);
}
@ -1818,12 +1806,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
initval = bit.wire->attributes.at(ID::init);
while (GetSize(initval) < GetSize(bit.wire))
initval.bits.push_back(State::Sx);
initval.bits().push_back(State::Sx);
if (it.second == '0')
initval.bits.at(bit.offset) = State::S0;
initval.bits().at(bit.offset) = State::S0;
if (it.second == '1')
initval.bits.at(bit.offset) = State::S1;
initval.bits().at(bit.offset) = State::S1;
bit.wire->attributes[ID::init] = initval;
}
@ -2010,7 +1998,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
Const qx_init = Const(State::S1, width);
qx_init.bits.resize(2 * width, State::S0);
qx_init.bits().resize(2 * width, State::S0);
clocking.addDff(new_verific_id(inst), sig_dx, sig_qx, qx_init);
module->addXnor(new_verific_id(inst), sig_dx, sig_qx, sig_ox);