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const: represent string constants as string, assert not accessed as bits

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This commit is contained in:
Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
parent 960bca0196
commit 498e0498c5
81 changed files with 764 additions and 690 deletions
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49
frontends/ast/ast.cc
View file

@ -20,10 +20,10 @@
*
* This is the AST frontend library.
*
* The AST frontend library is not a frontend on its own but provides an
* abstract syntax tree (AST) abstraction for the open source Verilog frontend
* at frontends/verilog.
*
* The AST frontend library is not a frontend on it's own but provides a
* generic abstract syntax tree (AST) abstraction for HDL code and can be
* used by HDL frontends. See "ast.h" for an overview of the API and the
* Verilog frontend for an usage example.
*
*/
@ -933,15 +933,7 @@ RTLIL::Const AstNode::asAttrConst() const
{
log_assert(type == AST_CONSTANT);
RTLIL::Const val;
val.bits = bits;
if (is_string) {
val.flags |= RTLIL::CONST_FLAG_STRING;
log_assert(val.decode_string() == str);
}
return val;
return is_string ? RTLIL::Const(str) : RTLIL::Const(bits);
}
RTLIL::Const AstNode::asParaConst() const
@ -987,7 +979,7 @@ uint64_t AstNode::asInt(bool is_signed)
uint64_t ret = 0;
for (int i = 0; i < 64; i++)
if (v.bits.at(i) == RTLIL::State::S1)
if (v.bits().at(i) == RTLIL::State::S1)
ret |= uint64_t(1) << i;
return ret;
@ -1005,15 +997,15 @@ double AstNode::asReal(bool is_signed)
{
RTLIL::Const val(bits);
bool is_negative = is_signed && !val.bits.empty() && val.bits.back() == RTLIL::State::S1;
bool is_negative = is_signed && !val.bits().empty() && val.bits().back() == RTLIL::State::S1;
if (is_negative)
val = const_neg(val, val, false, false, val.bits.size());
val = const_neg(val, val, false, false, val.size());
double v = 0;
for (size_t i = 0; i < val.bits.size(); i++)
for (size_t i = 0; i < val.size(); i++)
// IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
// the net or the variable shall be treated as zero upon conversion.
if (val.bits.at(i) == RTLIL::State::S1)
if (val.bits().at(i) == RTLIL::State::S1)
v += exp2(i);
if (is_negative)
v *= -1;
@ -1036,15 +1028,15 @@ RTLIL::Const AstNode::realAsConst(int width)
#else
if (!std::isfinite(v)) {
#endif
result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
result.bits() = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
} else {
bool is_negative = v < 0;
if (is_negative)
v *= -1;
for (int i = 0; i < width; i++, v /= 2)
result.bits.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
result.bits().push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
if (is_negative)
result = const_neg(result, result, false, false, result.bits.size());
result = const_neg(result, result, false, false, result.size());
}
return result;
}
@ -1741,8 +1733,15 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
static std::string serialize_param_value(const RTLIL::Const &val) {
std::string res;
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_STRING)
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_STRING) {
res.push_back('t');
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_STRING_COMPACT) {
res += stringf("%d", GetSize(val));
res.push_back('\'');
res.append(val.decode_string());
return res;
}
}
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED)
res.push_back('s');
if (val.flags & RTLIL::ConstFlags::CONST_FLAG_REAL)
@ -1750,7 +1749,7 @@ static std::string serialize_param_value(const RTLIL::Const &val) {
res += stringf("%d", GetSize(val));
res.push_back('\'');
for (int i = GetSize(val) - 1; i >= 0; i--) {
switch (val.bits[i]) {
switch (val.bits()[i]) {
case RTLIL::State::S0: res.push_back('0'); break;
case RTLIL::State::S1: res.push_back('1'); break;
case RTLIL::State::Sx: res.push_back('x'); break;
@ -1850,7 +1849,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
} else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0)
child->children[0] = AstNode::mkconst_str(it->second.decode_string());
else
child->children[0] = AstNode::mkconst_bits(it->second.bits, (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
child->children[0] = AstNode::mkconst_bits(it->second.bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
rewritten.insert(it->first);
}
@ -1863,7 +1862,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string()));
else
defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
defparam->children.push_back(AstNode::mkconst_bits(param.second.bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
new_ast->children.push_back(defparam);
}

4
frontends/ast/ast.h
View file

@ -17,9 +17,7 @@
*
* ---
*
* The AST frontend library is not a frontend on its own but provides an
* abstract syntax tree (AST) abstraction for the open source Verilog frontend
* at frontends/verilog.
* This is support code for the Verilog frontend at frontends/verilog
*
*/

10
frontends/ast/genrtlil.cc
View file

@ -735,10 +735,10 @@ struct AST_INTERNAL::ProcessGenerator
for (auto sync : proc->syncs) {
if (sync->type == RTLIL::STp) {
triggers.append(sync->signal);
polarity.bits.push_back(RTLIL::S1);
polarity.bits().push_back(RTLIL::S1);
} else if (sync->type == RTLIL::STn) {
triggers.append(sync->signal);
polarity.bits.push_back(RTLIL::S0);
polarity.bits().push_back(RTLIL::S0);
}
}
@ -832,10 +832,10 @@ struct AST_INTERNAL::ProcessGenerator
for (auto sync : proc->syncs) {
if (sync->type == RTLIL::STp) {
triggers.append(sync->signal);
polarity.bits.push_back(RTLIL::S1);
polarity.bits().push_back(RTLIL::S1);
} else if (sync->type == RTLIL::STn) {
triggers.append(sync->signal);
polarity.bits.push_back(RTLIL::S0);
polarity.bits().push_back(RTLIL::S0);
}
}
@ -892,7 +892,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
for (int i = 0; i < portid; i++) {
int new_bit = port_map[std::make_pair(memid, i)];
priority_mask.bits[new_bit] = orig_priority_mask.bits[i];
priority_mask.bits()[new_bit] = orig_priority_mask.bits()[i];
}
action.priority_mask = priority_mask;
sync->mem_write_actions.push_back(action);

66
frontends/ast/simplify.cc
View file

@ -1660,8 +1660,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (v->type == AST_CONSTANT && v->bits_only_01()) {
RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint);
RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1);
log_assert(match.bits.size() == 1);
if (match.bits.front() == RTLIL::State::S1) {
log_assert(match.size() == 1);
if (match.bits().front() == RTLIL::State::S1) {
while (i+1 < GetSize(children))
delete children[++i];
goto keep_const_cond;
@ -1963,7 +1963,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (children[1]->type != AST_CONSTANT)
input_error("Right operand of to_bits expression is not constant!\n");
RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed);
newNode = mkconst_bits(new_value.bits, children[1]->is_signed);
newNode = mkconst_bits(new_value.bits(), children[1]->is_signed);
goto apply_newNode;
}
@ -2126,7 +2126,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n",
children[0]->realvalue, log_signal(constvalue));
delete children[0];
children[0] = mkconst_bits(constvalue.bits, sign_hint);
children[0] = mkconst_bits(constvalue.bits(), sign_hint);
fixup_hierarchy_flags();
did_something = true;
}
@ -2135,7 +2135,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
RTLIL::SigSpec sig(children[0]->bits);
sig.extend_u0(width, children[0]->is_signed);
AstNode *old_child_0 = children[0];
children[0] = mkconst_bits(sig.as_const().bits, is_signed);
children[0] = mkconst_bits(sig.as_const().bits(), is_signed);
delete old_child_0;
fixup_hierarchy_flags();
}
@ -3435,8 +3435,8 @@ skip_dynamic_range_lvalue_expansion:;
delete buf;
uint32_t result = 0;
for (size_t i = 0; i < arg_value.bits.size(); i++)
if (arg_value.bits.at(i) == RTLIL::State::S1)
for (size_t i = 0; i < arg_value.size(); i++)
if (arg_value.bits().at(i) == RTLIL::State::S1)
result = i + 1;
newNode = mkconst_int(result, true);
@ -4115,14 +4115,14 @@ replace_fcall_later:;
case AST_BIT_NOT:
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = RTLIL::const_not(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
newNode = mkconst_bits(y.bits, sign_hint);
newNode = mkconst_bits(y.bits(), sign_hint);
}
break;
case AST_TO_SIGNED:
case AST_TO_UNSIGNED:
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = children[0]->bitsAsConst(width_hint, sign_hint);
newNode = mkconst_bits(y.bits, type == AST_TO_SIGNED);
newNode = mkconst_bits(y.bits(), type == AST_TO_SIGNED);
}
break;
if (0) { case AST_BIT_AND: const_func = RTLIL::const_and; }
@ -4132,7 +4132,7 @@ replace_fcall_later:;
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
newNode = mkconst_bits(y.bits, sign_hint);
newNode = mkconst_bits(y.bits(), sign_hint);
}
break;
if (0) { case AST_REDUCE_AND: const_func = RTLIL::const_reduce_and; }
@ -4142,13 +4142,13 @@ replace_fcall_later:;
if (0) { case AST_REDUCE_BOOL: const_func = RTLIL::const_reduce_bool; }
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, false, false, -1);
newNode = mkconst_bits(y.bits, false);
newNode = mkconst_bits(y.bits(), false);
}
break;
case AST_LOGIC_NOT:
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = RTLIL::const_logic_not(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1);
newNode = mkconst_bits(y.bits, false);
newNode = mkconst_bits(y.bits(), false);
} else
if (children[0]->isConst()) {
newNode = mkconst_int(children[0]->asReal(sign_hint) == 0, false, 1);
@ -4159,7 +4159,7 @@ replace_fcall_later:;
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), RTLIL::Const(children[1]->bits),
children[0]->is_signed, children[1]->is_signed, -1);
newNode = mkconst_bits(y.bits, false);
newNode = mkconst_bits(y.bits(), false);
} else
if (children[0]->isConst() && children[1]->isConst()) {
if (type == AST_LOGIC_AND)
@ -4176,7 +4176,7 @@ replace_fcall_later:;
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint);
newNode = mkconst_bits(y.bits, sign_hint);
newNode = mkconst_bits(y.bits(), sign_hint);
} else
if (type == AST_POW && children[0]->isConst() && children[1]->isConst()) {
newNode = new AstNode(AST_REALVALUE);
@ -4196,7 +4196,7 @@ replace_fcall_later:;
bool cmp_signed = children[0]->is_signed && children[1]->is_signed;
RTLIL::Const y = const_func(children[0]->bitsAsConst(cmp_width, cmp_signed),
children[1]->bitsAsConst(cmp_width, cmp_signed), cmp_signed, cmp_signed, 1);
newNode = mkconst_bits(y.bits, false);
newNode = mkconst_bits(y.bits(), false);
} else
if (children[0]->isConst() && children[1]->isConst()) {
bool cmp_signed = (children[0]->type == AST_REALVALUE || children[0]->is_signed) && (children[1]->type == AST_REALVALUE || children[1]->is_signed);
@ -4221,7 +4221,7 @@ replace_fcall_later:;
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
children[1]->bitsAsConst(width_hint, sign_hint), sign_hint, sign_hint, width_hint);
newNode = mkconst_bits(y.bits, sign_hint);
newNode = mkconst_bits(y.bits(), sign_hint);
} else
if (children[0]->isConst() && children[1]->isConst()) {
newNode = new AstNode(AST_REALVALUE);
@ -4240,7 +4240,7 @@ replace_fcall_later:;
if (0) { case AST_NEG: const_func = RTLIL::const_neg; }
if (children[0]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint), dummy_arg, sign_hint, false, width_hint);
newNode = mkconst_bits(y.bits, sign_hint);
newNode = mkconst_bits(y.bits(), sign_hint);
} else
if (children[0]->isConst()) {
newNode = new AstNode(AST_REALVALUE);
@ -4268,10 +4268,10 @@ replace_fcall_later:;
newNode->realvalue = choice->asReal(sign_hint);
} else {
RTLIL::Const y = choice->bitsAsConst(width_hint, sign_hint);
if (choice->is_string && y.bits.size() % 8 == 0 && sign_hint == false)
newNode = mkconst_str(y.bits);
if (choice->is_string && y.size() % 8 == 0 && sign_hint == false)
newNode = mkconst_str(y.bits());
else
newNode = mkconst_bits(y.bits, sign_hint);
newNode = mkconst_bits(y.bits(), sign_hint);
}
} else
if (choice->isConst()) {
@ -4280,11 +4280,11 @@ replace_fcall_later:;
} else if (children[1]->type == AST_CONSTANT && children[2]->type == AST_CONSTANT) {
RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
log_assert(a.bits.size() == b.bits.size());
for (size_t i = 0; i < a.bits.size(); i++)
if (a.bits[i] != b.bits[i])
a.bits[i] = RTLIL::State::Sx;
newNode = mkconst_bits(a.bits, sign_hint);
log_assert(a.size() == b.size());
for (size_t i = 0; i < a.size(); i++)
if (a.bits()[i] != b.bits()[i])
a.bits()[i] = RTLIL::State::Sx;
newNode = mkconst_bits(a.bits(), sign_hint);
} else if (children[1]->isConst() && children[2]->isConst()) {
newNode = new AstNode(AST_REALVALUE);
if (children[1]->asReal(sign_hint) == children[2]->asReal(sign_hint))
@ -4305,7 +4305,7 @@ replace_fcall_later:;
val = children[1]->bitsAsUnsizedConst(width);
else
val = children[1]->bitsAsConst(width);
newNode = mkconst_bits(val.bits, children[1]->is_signed);
newNode = mkconst_bits(val.bits(), children[1]->is_signed);
}
break;
case AST_CONCAT:
@ -4890,7 +4890,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
target->str = str;
target->id2ast = id2ast;
target->was_checked = true;
block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).bits, false)));
block->children.push_back(new AstNode(AST_ASSIGN_EQ, target, mkconst_bits(data.extract(i*wordsz + pos, clen).bits(), false)));
pos = epos;
}
}
@ -5245,7 +5245,7 @@ bool AstNode::is_simple_const_expr()
bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &variables, AstNode *fcall, bool must_succeed)
{
if (type == AST_IDENTIFIER && variables.count(str)) {
int offset = variables.at(str).offset, width = variables.at(str).val.bits.size();
int offset = variables.at(str).offset, width = variables.at(str).val.size();
if (!children.empty()) {
if (children.size() != 1 || children.at(0)->type != AST_RANGE) {
if (!must_succeed)
@ -5268,7 +5268,7 @@ bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
offset -= variables.at(str).offset;
if (variables.at(str).range_swapped)
offset = -offset;
std::vector<RTLIL::State> &var_bits = variables.at(str).val.bits;
std::vector<RTLIL::State> &var_bits = variables.at(str).val.bits();
std::vector<RTLIL::State> new_bits(var_bits.begin() + offset, var_bits.begin() + offset + width);
AstNode *newNode = mkconst_bits(new_bits, variables.at(str).is_signed);
newNode->cloneInto(this);
@ -5399,7 +5399,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
}
if (stmt->children.at(0)->children.empty()) {
variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size());
variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.size());
} else {
AstNode *range = stmt->children.at(0)->children.at(0);
if (!range->range_valid) {
@ -5410,12 +5410,12 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
int offset = min(range->range_left, range->range_right);
int width = std::abs(range->range_left - range->range_right) + 1;
varinfo_t &v = variables[stmt->children.at(0)->str];
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size());
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.size());
for (int i = 0; i < width; i++) {
int index = i + offset - v.offset;
if (v.range_swapped)
index = -index;
v.val.bits.at(index) = r.bits.at(i);
v.val.bits().at(index) = r.bits().at(i);
}
}
@ -5558,7 +5558,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed)
log_abort();
}
result = AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed);
result = AstNode::mkconst_bits(variables.at(str).val.bits(), variables.at(str).is_signed);
finished:
delete block;

20
frontends/blif/blifparse.cc
View file

@ -149,7 +149,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (buffer[0] == '.')
{
if (lutptr) {
for (auto &bit : lutptr->bits)
for (auto &bit : lutptr->bits())
if (bit == RTLIL::State::Sx)
bit = lut_default_state;
lutptr = NULL;
@ -321,9 +321,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
const_v = Const(str);
} else {
int n = strlen(v);
const_v.bits.resize(n);
const_v.bits().resize(n);
for (int i = 0; i < n; i++)
const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0;
const_v.bits()[i] = v[n-i-1] != '0' ? State::S1 : State::S0;
}
if (!strcmp(cmd, ".attr")) {
if (obj_attributes == nullptr) {
@ -566,16 +566,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
for (int i = 0; i < input_len; i++)
switch (input[i]) {
case '0':
sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits().push_back(State::S1);
sopcell->parameters[ID::TABLE].bits().push_back(State::S0);
break;
case '1':
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
sopcell->parameters[ID::TABLE].bits().push_back(State::S0);
sopcell->parameters[ID::TABLE].bits().push_back(State::S1);
break;
default:
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits().push_back(State::S0);
sopcell->parameters[ID::TABLE].bits().push_back(State::S0);
break;
}
@ -605,7 +605,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto try_next_value;
}
}
lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
lutptr->bits().at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
try_next_value:;
}

2
frontends/rtlil/rtlil_parser.y
View file

@ -437,7 +437,7 @@ constant:
bits.pop_back();
$$ = new RTLIL::Const;
for (auto it = bits.begin(); it != bits.end(); it++)
$$->bits.push_back(*it);
$$->bits().push_back(*it);
free($1);
} |
TOK_INT {

26
frontends/verific/verific.cc
View file

@ -237,19 +237,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
RTLIL::Const mkconst_str(const std::string &str)
{
RTLIL::Const val;
std::vector<RTLIL::State> data;
data.reserve(str.size() * 8);
for (size_t i = 0; i < str.size(); i++) {
unsigned char ch = str[str.size() - i - 1];
for (int j = 0; j < 8; j++) {
data.push_back((ch & 1) ? State::S1 : State::S0);
ch = ch >> 1;
}
}
val.bits = data;
val.flags |= RTLIL::CONST_FLAG_STRING;
return val;
return RTLIL::Const(str);
}
static const RTLIL::Const extract_vhdl_boolean(std::string &val)
@ -1742,9 +1730,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (init_nets.count(net)) {
if (init_nets.at(net) == '0')
initval.bits.at(bitidx) = State::S0;
initval.bits().at(bitidx) = State::S0;
if (init_nets.at(net) == '1')
initval.bits.at(bitidx) = State::S1;
initval.bits().at(bitidx) = State::S1;
initval_valid = true;
init_nets.erase(net);
}
@ -1818,12 +1806,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
initval = bit.wire->attributes.at(ID::init);
while (GetSize(initval) < GetSize(bit.wire))
initval.bits.push_back(State::Sx);
initval.bits().push_back(State::Sx);
if (it.second == '0')
initval.bits.at(bit.offset) = State::S0;
initval.bits().at(bit.offset) = State::S0;
if (it.second == '1')
initval.bits.at(bit.offset) = State::S1;
initval.bits().at(bit.offset) = State::S1;
bit.wire->attributes[ID::init] = initval;
}
@ -2010,7 +1998,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
Const qx_init = Const(State::S1, width);
qx_init.bits.resize(2 * width, State::S0);
qx_init.bits().resize(2 * width, State::S0);
clocking.addDff(new_verific_id(inst), sig_dx, sig_qx, qx_init);
module->addXnor(new_verific_id(inst), sig_dx, sig_qx, sig_ox);