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const: represent string constants as string, assert not accessed as bits

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This commit is contained in:
Emil J. Tywoniak 2024-07-29 16:38:32 +02:00
parent 960bca0196
commit 498e0498c5
81 changed files with 764 additions and 690 deletions
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2
backends/blif/blif.cc
View file

@ -387,7 +387,7 @@ struct BlifDumper
auto &inputs = cell->getPort(ID::A);
auto width = cell->parameters.at(ID::WIDTH).as_int();
auto depth = cell->parameters.at(ID::DEPTH).as_int();
vector<State> table = cell->parameters.at(ID::TABLE).bits;
vector<State> table = cell->parameters.at(ID::TABLE).bits();
while (GetSize(table) < 2*width*depth)
table.push_back(State::S0);
log_assert(inputs.size() == width);

6
backends/btor/btor.cc
View file

@ -711,9 +711,9 @@ struct BtorWorker
Const initval;
for (int i = 0; i < GetSize(sig_q); i++)
if (initbits.count(sig_q[i]))
initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
initval.bits().push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
else
initval.bits.push_back(State::Sx);
initval.bits().push_back(State::Sx);
int nid_init_val = -1;
@ -1042,7 +1042,7 @@ struct BtorWorker
Const c(bit.data);
while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
c.bits.push_back(sig[i+GetSize(c)].data);
c.bits().push_back(sig[i+GetSize(c)].data);
if (consts.count(c) == 0) {
int sid = get_bv_sid(GetSize(c));

10
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -864,7 +864,7 @@ struct CxxrtlWorker {
if (!module->has_attribute(ID(cxxrtl_template)))
return {};
if (module->attributes.at(ID(cxxrtl_template)).flags != RTLIL::CONST_FLAG_STRING)
if (!(module->attributes.at(ID(cxxrtl_template)).flags & RTLIL::CONST_FLAG_STRING))
log_cmd_error("Attribute `cxxrtl_template' of module `%s' is not a string.\n", log_id(module));
std::vector<std::string> param_names = split_by(module->get_string_attribute(ID(cxxrtl_template)), " \t");
@ -1665,15 +1665,15 @@ struct CxxrtlWorker {
switch (bit) {
case RTLIL::S0:
case RTLIL::S1:
compare_mask.bits.push_back(RTLIL::S1);
compare_value.bits.push_back(bit);
compare_mask.bits().push_back(RTLIL::S1);
compare_value.bits().push_back(bit);
break;
case RTLIL::Sx:
case RTLIL::Sz:
case RTLIL::Sa:
compare_mask.bits.push_back(RTLIL::S0);
compare_value.bits.push_back(RTLIL::S0);
compare_mask.bits().push_back(RTLIL::S0);
compare_value.bits().push_back(RTLIL::S0);
break;
default:

2
backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
View file

@ -750,7 +750,7 @@ std::ostream &operator<<(std::ostream &os, const value<Bits> &val) {
auto old_flags = os.flags(std::ios::right);
auto old_width = os.width(0);
auto old_fill = os.fill('0');
os << val.bits << '\'' << std::hex;
os << val.bits() << '\'' << std::hex;
for (size_t n = val.chunks - 1; n != (size_t)-1; n--) {
if (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)
os.width((Bits % value<Bits>::chunk::bits + 3) / 4);

14
backends/edif/edif.cc
View file

@ -334,20 +334,20 @@ struct EdifBackend : public Backend {
auto add_prop = [&](IdString name, Const val) {
if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
*f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
else if (val.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
else {
std::string hex_string = "";
for (size_t i = 0; i < val.bits.size(); i += 4) {
for (size_t i = 0; i < val.size(); i += 4) {
int digit_value = 0;
if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
if (i+0 < val.size() && val.bits().at(i+0) == RTLIL::State::S1) digit_value |= 1;
if (i+1 < val.size() && val.bits().at(i+1) == RTLIL::State::S1) digit_value |= 2;
if (i+2 < val.size() && val.bits().at(i+2) == RTLIL::State::S1) digit_value |= 4;
if (i+3 < val.size() && val.bits().at(i+3) == RTLIL::State::S1) digit_value |= 8;
char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
hex_string = std::string(digit_str) + hex_string;
}
*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits()), hex_string.c_str());
}
};
for (auto module : sorted_modules)

6
backends/firrtl/firrtl.cc
View file

@ -149,7 +149,7 @@ std::string dump_const(const RTLIL::Const &data)
// Numeric (non-real) parameter.
else
{
int width = data.bits.size();
int width = data.size();
// If a standard 32-bit int, then emit standard int value like "56" or
// "-56". Firrtl supports negative-valued int literals.
@ -163,7 +163,7 @@ std::string dump_const(const RTLIL::Const &data)
for (int i = 0; i < width; i++)
{
switch (data.bits[i])
switch (data.bits()[i])
{
case State::S0: break;
case State::S1: int_val |= (1 << i); break;
@ -205,7 +205,7 @@ std::string dump_const(const RTLIL::Const &data)
for (int i = width - 1; i >= 0; i--)
{
log_assert(i < width);
switch (data.bits[i])
switch (data.bits()[i])
{
case State::S0: res_str += "0"; break;
case State::S1: res_str += "1"; break;

8
backends/intersynth/intersynth.cc
View file

@ -176,11 +176,11 @@ struct IntersynthBackend : public Backend {
}
}
for (auto &param : cell->parameters) {
celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first));
if (param.second.bits.size() != 32) {
celltype_code += stringf(" cfg:%d %s", int(param.second.size()), log_id(param.first));
if (param.second.size() != 32) {
node_code += stringf(" %s '", log_id(param.first));
for (int i = param.second.bits.size()-1; i >= 0; i--)
node_code += param.second.bits[i] == State::S1 ? "1" : "0";
for (int i = param.second.size()-1; i >= 0; i--)
node_code += param.second.bits()[i] == State::S1 ? "1" : "0";
} else
node_code += stringf(" %s 0x%x", log_id(param.first), param.second.as_int());
}

2
backends/jny/jny.cc
View file

@ -334,7 +334,7 @@ struct JnyWriter
f << "\"" << escape_string(str) << "\"";
} else if ((v.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) == RTLIL::ConstFlags::CONST_FLAG_SIGNED) {
f << stringf("\"%dsd %d\"", v.size(), v.as_int(true));
f << stringf("\"%zusd %d\"", v.size(), v.as_int(true));
} else if ((v.flags & RTLIL::ConstFlags::CONST_FLAG_REAL) == RTLIL::ConstFlags::CONST_FLAG_REAL) {
} else {

12
backends/rtlil/rtlil_backend.cc
View file

@ -33,13 +33,13 @@ YOSYS_NAMESPACE_BEGIN
void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint)
{
if (width < 0)
width = data.bits.size() - offset;
if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
width = data.size() - offset;
if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.size()) {
if (width == 32 && autoint) {
int32_t val = 0;
for (int i = 0; i < width; i++) {
log_assert(offset+i < (int)data.bits.size());
switch (data.bits[offset+i]) {
log_assert(offset+i < (int)data.size());
switch (data.bits()[offset+i]) {
case State::S0: break;
case State::S1: val |= 1 << i; break;
default: val = -1; break;
@ -55,8 +55,8 @@ void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi
f << "x";
} else {
for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
log_assert(i < (int)data.size());
switch (data.bits()[i]) {
case State::S0: f << stringf("0"); break;
case State::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break;

2
backends/simplec/simplec.cc
View file

@ -657,7 +657,7 @@ struct SimplecWorker
{
SigSpec sig = sigmaps.at(module)(w);
Const val = w->attributes.at(ID::init);
val.bits.resize(GetSize(sig), State::Sx);
val.bits().resize(GetSize(sig), State::Sx);
for (int i = 0; i < GetSize(sig); i++)
if (val[i] == State::S0 || val[i] == State::S1) {

2
backends/smt2/smt2.cc
View file

@ -1077,7 +1077,7 @@ struct Smt2Worker
RTLIL::SigSpec sig = sigmap(wire);
Const val = wire->attributes.at(ID::init);
val.bits.resize(GetSize(sig), State::Sx);
val.bits().resize(GetSize(sig), State::Sx);
if (bvmode && GetSize(sig) > 1) {
Const mask(State::S1, GetSize(sig));
bool use_mask = false;

24
backends/verilog/verilog_backend.cc
View file

@ -191,7 +191,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
{
bool set_signed = (data.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
if (width < 0)
width = data.bits.size() - offset;
width = data.size() - offset;
if (width == 0) {
// See IEEE 1364-2005 Clause 5.1.14.
f << "{0{1'b0}}";
@ -199,14 +199,14 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
}
if (nostr)
goto dump_hex;
if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.size()) {
if (width == 32 && !no_decimal && !nodec) {
int32_t val = 0;
for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size());
if (data.bits[i] != State::S0 && data.bits[i] != State::S1)
log_assert(i < (int)data.size());
if (data.bits()[i] != State::S0 && data.bits()[i] != State::S1)
goto dump_hex;
if (data.bits[i] == State::S1)
if (data.bits()[i] == State::S1)
val |= 1 << (i - offset);
}
if (decimal)
@ -221,8 +221,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
goto dump_bin;
vector<char> bin_digits, hex_digits;
for (int i = offset; i < offset+width; i++) {
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
log_assert(i < (int)data.size());
switch (data.bits()[i]) {
case State::S0: bin_digits.push_back('0'); break;
case State::S1: bin_digits.push_back('1'); break;
case RTLIL::Sx: bin_digits.push_back('x'); break;
@ -275,8 +275,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
if (width == 0)
f << stringf("0");
for (int i = offset+width-1; i >= offset; i--) {
log_assert(i < (int)data.bits.size());
switch (data.bits[i]) {
log_assert(i < (int)data.size());
switch (data.bits()[i]) {
case State::S0: f << stringf("0"); break;
case State::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break;
@ -318,10 +318,10 @@ void dump_reg_init(std::ostream &f, SigSpec sig)
for (auto bit : active_sigmap(sig)) {
if (active_initdata.count(bit)) {
initval.bits.push_back(active_initdata.at(bit));
initval.bits().push_back(active_initdata.at(bit));
gotinit = true;
} else {
initval.bits.push_back(State::Sx);
initval.bits().push_back(State::Sx);
}
}
@ -751,7 +751,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
if (port.wide_log2) {
Const addr_lo;
for (int i = 0; i < port.wide_log2; i++)
addr_lo.bits.push_back(State(sub >> i & 1));
addr_lo.bits().push_back(State(sub >> i & 1));
os << "{";
os << temp_id;
os << ", ";