mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 03:35:40 +00:00
Code Activity

kernel: add SwitchRule signal_src

Browse source 
(cherry picked from commit 53585db9f7)
This commit is contained in:
Emil J. Tywoniak 2026-01-26 11:59:39 +01:00
parent cbf9b0b5d4
commit 4985df71cb
2 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/ast/genrtlil.cc
View file

@ -694,6 +694,7 @@ struct AST_INTERNAL::ProcessGenerator
sw->module = current_module;
set_src_attr(sw, ast);
sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
sw->signal_src = current_module->design->twines.add(Twine{ast->children[0]->loc_string()});
current_case->switches.push_back(sw);
for (auto &attr : ast->attributes) {