diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 5be054516..2f1e34a3a 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -694,6 +694,7 @@ struct AST_INTERNAL::ProcessGenerator
 				sw->module = current_module;
 				set_src_attr(sw, ast);
 				sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
+				sw->signal_src = current_module->design->twines.add(Twine{ast->children[0]->loc_string()});
 				current_case->switches.push_back(sw);
 
 				for (auto &attr : ast->attributes) {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 014dafcd2..44dc1fc46 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -2557,6 +2557,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
 	RTLIL::Module *module = nullptr;
 
 	RTLIL::SigSpec signal;
+	TwineRef signal_src = Twine::Null;
 	std::vector<RTLIL::CaseRule*> cases;
 
 	~SwitchRule();