End of file fix

tests/various/attrib05_port_conn.v

@@ -18,4 +18,3 @@ module foo(clk, rst, inp, out);
 
   bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
 endmodule
-

tests/various/attrib07_func_call.v

@@ -18,4 +18,3 @@ module foo(clk, rst, inp_a, inp_b, out);
     else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
 
 endmodule
-

tests/various/bug3515.ys

@@ -28,4 +28,3 @@ hierarchy -top mod_and_or
 opt
 extract -map ./bug3515.v
 select -assert-count 2 t:$and
-

tests/various/bug4909.ys

@@ -41,4 +41,3 @@ EOF
 
 prep
 splitcells
-

tests/various/deminout_unused.ys

@@ -11,4 +11,3 @@ proc
 tribuf
 deminout
 select -assert-count 1 i:x o:x %i
-

tests/various/dynamic_part_select/latch_1990_gate.v

@@ -3,4 +3,3 @@ module latch_1990_gate
   (output wire [1:0] x);
    assign x = 2'b10;
 endmodule // latch_1990_gate
-

tests/various/dynamic_part_select/reversed.v

@@ -11,4 +11,3 @@ module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
       dout[(WIDTH-ctrl*sel)-:SLICE] <= din;
    end
 endmodule
-

tests/various/reg_wire_error.sv

@@ -71,4 +71,3 @@ begin
 end
 
 endmodule
-

tests/various/scopeinfo.ys

@@ -107,4 +107,4 @@ select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/r:TYPE=module
 select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_inst_attr=inst_attr_deep %i
 select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_module_attr=module_attr_deep %i
 select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_src %i
-select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i

tests/various/sim_const.ys

@@ -10,4 +10,3 @@ EOT
 proc
 sim -clock clk -n 1 -w top
 select -assert-count 1 a:init=2'b10 top/q %i
-

tests/various/stat_hierarchy.ys

@@ -58,5 +58,3 @@ logger -expect log "2   94.349        -        -   sg13g2_dfrbp_1" 2
 logger -expect log "2   94.349        2        - submodules" 2
 logger -expect-no-warnings
 stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top -hierarchy
-
-

tests/various/stat_high_level.ys

@@ -88,5 +88,3 @@ logger -expect log "2       51        -        -   \$reduce_xor" 2
 logger -expect log "8       66        2        5 cells" 2
 logger -expect-no-warnings
 stat -liberty ./stat_area_by_width.lib -top \top -hierarchy
-
-

tests/various/stat_high_level2.ys

@@ -87,5 +87,3 @@ logger -expect log "3     37.5        3     37.5 cells" 1
 logger -expect log "8       80        2        5 cells" 2
 logger -expect-no-warnings
 stat -liberty ./stat_area_by_width.lib -top \top -hierarchy
-
-