diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml index c758bf1f6..ce2780d6f 100644 --- a/.github/ISSUE_TEMPLATE/config.yml +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -5,4 +5,3 @@ contact_links: - name: IRC Channel url: https://web.libera.chat/#yosys about: "#yosys on irc.libera.chat" - diff --git a/.github/ISSUE_TEMPLATE/feature_request.yml b/.github/ISSUE_TEMPLATE/feature_request.yml index 49d86f341..19785d22a 100644 --- a/.github/ISSUE_TEMPLATE/feature_request.yml +++ b/.github/ISSUE_TEMPLATE/feature_request.yml @@ -22,4 +22,3 @@ body: description: "A clear and detailed description of the feature." validations: required: true - diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index d8d929f3f..428735733 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -6,4 +6,4 @@ _Explain how this is achieved._ _Make sure your change comes with tests. If not possible, share how a reviewer might evaluate it._ -_These template prompts can be deleted when you're done responding to them._ \ No newline at end of file +_These template prompts can be deleted when you're done responding to them._ diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index a1229d164..d6c77fcf1 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -98,4 +98,4 @@ jobs: echo "Some jobs failed or were cancelled" exit 1 fi - - run: echo "All good" \ No newline at end of file + - run: echo "All good" diff --git a/CHANGELOG b/CHANGELOG index 61b221bc9..543209a83 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1802,4 +1802,3 @@ Yosys 0.1.0 .. Yosys 0.2.0 - Added "design -stash/-copy-from/-copy-to" - Added "copy" command - Added "splice" command - diff --git a/README.md b/README.md index e27486a84..61062243b 100644 --- a/README.md +++ b/README.md @@ -303,4 +303,3 @@ DOCS (e.g.) This will build/rebuild yosys as necessary before generating the website documentation from the yosys help commands. To build for pdf instead of html, use the `docs-latexpdf` target. - diff --git a/backends/btor/test_cells.sh b/backends/btor/test_cells.sh index fc7f5b75c..dc044ec29 100755 --- a/backends/btor/test_cells.sh +++ b/backends/btor/test_cells.sh @@ -27,4 +27,3 @@ for fn in test_*.il; do done echo "OK." - diff --git a/backends/cxxrtl/runtime/README.txt b/backends/cxxrtl/runtime/README.txt index 9ae7051cd..f6e2d6c92 100644 --- a/backends/cxxrtl/runtime/README.txt +++ b/backends/cxxrtl/runtime/README.txt @@ -15,4 +15,4 @@ file of the simulation toplevel). The interfaces declared in `cxxrtl*.h` (without `capi`) are unstable and may change without notice. For clarity, all of the files in this directory and its subdirectories have unique names regardless -of the directory where they are placed. \ No newline at end of file +of the directory where they are placed. diff --git a/backends/edif/runtest.py b/backends/edif/runtest.py index 826876a86..7af6433c1 100644 --- a/backends/edif/runtest.py +++ b/backends/edif/runtest.py @@ -118,4 +118,3 @@ os.system("set -x; ./test_gold > test_gold.out") os.system("set -x; ./test_gate > test_gate.out") os.system("set -x; md5sum test_gold.out test_gate.out") - diff --git a/backends/simplec/test00_uut.v b/backends/simplec/test00_uut.v index 92329a6f9..15ff4391d 100644 --- a/backends/simplec/test00_uut.v +++ b/backends/simplec/test00_uut.v @@ -11,4 +11,3 @@ endmodule module unit_y(input [31:0] a, b, c, output [31:0] y); assign y = a & (b | c); endmodule - diff --git a/backends/smt2/test_cells.sh b/backends/smt2/test_cells.sh index 33c1b9989..bf13b5fb3 100644 --- a/backends/smt2/test_cells.sh +++ b/backends/smt2/test_cells.sh @@ -52,4 +52,3 @@ echo "" echo " All tests passed." echo "" exit 0 - diff --git a/backends/smv/test_cells.sh b/backends/smv/test_cells.sh index f2c5ff09d..2497edc6b 100644 --- a/backends/smv/test_cells.sh +++ b/backends/smv/test_cells.sh @@ -30,4 +30,3 @@ for fn in test_*.il; do done grep '^-- invariant .* is false' *.out || echo 'All OK.' - diff --git a/docs/source/appendix/env_vars.rst b/docs/source/appendix/env_vars.rst index 7e10fad86..1be00288e 100644 --- a/docs/source/appendix/env_vars.rst +++ b/docs/source/appendix/env_vars.rst @@ -29,4 +29,3 @@ Yosys environment variables ``YOSYS_ABORT_ON_LOG_ERROR`` Can be used for debugging Yosys internals. Setting it to 1 causes abort() to be called when Yosys terminates with an error message. - diff --git a/docs/source/cell/word_logic.rst b/docs/source/cell/word_logic.rst index 32945d560..9f04e9b99 100644 --- a/docs/source/cell/word_logic.rst +++ b/docs/source/cell/word_logic.rst @@ -43,4 +43,4 @@ values. .. autocellgroup:: logic :members: :source: - :linenos: \ No newline at end of file + :linenos: diff --git a/docs/source/code_examples/intro/mycells.v b/docs/source/code_examples/intro/mycells.v index 802f58718..87eed4ada 100644 --- a/docs/source/code_examples/intro/mycells.v +++ b/docs/source/code_examples/intro/mycells.v @@ -20,4 +20,3 @@ output reg Q; always @(posedge C) Q <= D; endmodule - diff --git a/docs/source/code_examples/macc/Makefile b/docs/source/code_examples/macc/Makefile index 6bd7dd116..a49083fd3 100644 --- a/docs/source/code_examples/macc/Makefile +++ b/docs/source/code_examples/macc/Makefile @@ -16,4 +16,3 @@ macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys .PHONY: clean clean: @rm -f *.dot - diff --git a/docs/source/code_examples/macc/macc_xilinx_test.ys b/docs/source/code_examples/macc/macc_xilinx_test.ys index 47bf399b2..aab4eb811 100644 --- a/docs/source/code_examples/macc/macc_xilinx_test.ys +++ b/docs/source/code_examples/macc/macc_xilinx_test.ys @@ -50,4 +50,3 @@ show -prefix macc_xilinx_test2e -format dot -notitle test2 design -load __macc_xilinx_xmap show -prefix macc_xilinx_xmap -format dot -notitle - diff --git a/docs/source/code_examples/macro_commands/synth_ice40.ys b/docs/source/code_examples/macro_commands/synth_ice40.ys index 07d960a64..e9b36bb35 100644 --- a/docs/source/code_examples/macro_commands/synth_ice40.ys +++ b/docs/source/code_examples/macro_commands/synth_ice40.ys @@ -88,4 +88,4 @@ check: stat check -noinit blackbox =A:whitebox - \ No newline at end of file + diff --git a/docs/source/code_examples/opt/opt_merge.ys b/docs/source/code_examples/opt/opt_merge.ys index 38434ca3a..2cb43a860 100644 --- a/docs/source/code_examples/opt/opt_merge.ys +++ b/docs/source/code_examples/opt/opt_merge.ys @@ -15,4 +15,3 @@ opt_merge after clean show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut - diff --git a/docs/source/code_examples/opt/opt_muxtree.ys b/docs/source/code_examples/opt/opt_muxtree.ys index b9d394c08..b5e4396d4 100644 --- a/docs/source/code_examples/opt/opt_muxtree.ys +++ b/docs/source/code_examples/opt/opt_muxtree.ys @@ -14,4 +14,3 @@ opt_muxtree after clean show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut - diff --git a/docs/source/code_examples/scrambler/scrambler.ys b/docs/source/code_examples/scrambler/scrambler.ys index f14caa6f7..c340f4b76 100644 --- a/docs/source/code_examples/scrambler/scrambler.ys +++ b/docs/source/code_examples/scrambler/scrambler.ys @@ -19,4 +19,3 @@ eval -set in 1 -show out eval -set in 270369 -show out sat -set out 632435482 - diff --git a/docs/source/code_examples/synth_flow/Makefile b/docs/source/code_examples/synth_flow/Makefile index 583c6a421..83a5f5b97 100644 --- a/docs/source/code_examples/synth_flow/Makefile +++ b/docs/source/code_examples/synth_flow/Makefile @@ -17,4 +17,3 @@ examples: .PHONY: clean clean: @rm -f *.dot - diff --git a/docs/source/using_yosys/more_scripting/data_flow_tracking.rst b/docs/source/using_yosys/more_scripting/data_flow_tracking.rst index aa13a2e69..fa8d1be00 100644 --- a/docs/source/using_yosys/more_scripting/data_flow_tracking.rst +++ b/docs/source/using_yosys/more_scripting/data_flow_tracking.rst @@ -111,4 +111,4 @@ For example, an AND gate will propagate a given tag on one input, if the other input is either 1 or carries a tag of the same group. So if one input is ``0, "key:a"`` and the other is ``0, "key:b"`` the result would be ``0, "key:a", "key:b"``, rather than simply ``0``. Note that if we add an unrelated -``"overflow"`` tag to the first input, it would still not be propagated. \ No newline at end of file +``"overflow"`` tag to the first input, it would still not be propagated. diff --git a/docs/source/using_yosys/synthesis/abc.rst b/docs/source/using_yosys/synthesis/abc.rst index ba12cabc1..086205f63 100644 --- a/docs/source/using_yosys/synthesis/abc.rst +++ b/docs/source/using_yosys/synthesis/abc.rst @@ -178,4 +178,3 @@ of carry chains and DSPs, it avoids optimising for a path that isn't the actual critical path, while the generally-longer paths result in ABC9 being able to reduce design area by mapping other logic to slower cells with greater logic density. - diff --git a/docs/source/using_yosys/synthesis/extract.rst b/docs/source/using_yosys/synthesis/extract.rst index 73957bb55..8c346412a 100644 --- a/docs/source/using_yosys/synthesis/extract.rst +++ b/docs/source/using_yosys/synthesis/extract.rst @@ -228,4 +228,4 @@ Unwrap in ``test2``: :end-before: end part e .. figure:: /_images/code_examples/macc/macc_xilinx_test2e.* - :class: width-helper invert-helper \ No newline at end of file + :class: width-helper invert-helper diff --git a/docs/source/using_yosys/synthesis/index.rst b/docs/source/using_yosys/synthesis/index.rst index 60581668f..6ca8b02d5 100644 --- a/docs/source/using_yosys/synthesis/index.rst +++ b/docs/source/using_yosys/synthesis/index.rst @@ -31,4 +31,3 @@ for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and extract abc cell_libs - diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst index 9b81fb6dc..b498bcb1d 100644 --- a/docs/source/using_yosys/synthesis/memory.rst +++ b/docs/source/using_yosys/synthesis/memory.rst @@ -787,4 +787,3 @@ Asynchronous writes end assign read_data = mem[read_addr]; - diff --git a/docs/source/yosys_internals/extending_yosys/index.rst b/docs/source/yosys_internals/extending_yosys/index.rst index 72843ecd6..d7ef48b08 100644 --- a/docs/source/yosys_internals/extending_yosys/index.rst +++ b/docs/source/yosys_internals/extending_yosys/index.rst @@ -14,4 +14,3 @@ of interest for developers looking to customise Yosys builds. advanced_bugpoint contributing test_suites - diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index 58274c864..f506f5c87 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -194,4 +194,3 @@ compiler versions. For up to date information, including OS versions, refer to .. code-block:: console cmake --build build --target test-unit - diff --git a/docs/source/yosys_internals/flow/index.rst b/docs/source/yosys_internals/flow/index.rst index c7ab0ebcc..e5afa2540 100644 --- a/docs/source/yosys_internals/flow/index.rst +++ b/docs/source/yosys_internals/flow/index.rst @@ -16,4 +16,3 @@ These scripts contain three types of commands: overview control_and_data verilog_frontend - diff --git a/docs/source/yosys_internals/formats/index.rst b/docs/source/yosys_internals/formats/index.rst index 611370ebc..22d9e964a 100644 --- a/docs/source/yosys_internals/formats/index.rst +++ b/docs/source/yosys_internals/formats/index.rst @@ -56,4 +56,3 @@ constructs must be called from the synthesis script first. .. [1] In Yosys the term pass is only used to refer to commands that operate on the RTLIL data structure. - diff --git a/examples/basys3/README b/examples/basys3/README index 0ce717294..77fbef15c 100644 --- a/examples/basys3/README +++ b/examples/basys3/README @@ -16,4 +16,3 @@ Programming board: All of the above: bash run.sh - diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc index 8cdaa1996..7b6736588 100644 --- a/examples/basys3/example.xdc +++ b/examples/basys3/example.xdc @@ -21,4 +21,3 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] - diff --git a/examples/cmos/README b/examples/cmos/README index c459b4b54..7033c9b82 100644 --- a/examples/cmos/README +++ b/examples/cmos/README @@ -10,4 +10,3 @@ Each test bench can be run separately by either running: The later case also includes pure verilog simulation using the iverilog and gtkwave for comparison. - diff --git a/examples/cmos/cmos_cells.sp b/examples/cmos/cmos_cells.sp index 673b20d08..f23d978cb 100644 --- a/examples/cmos/cmos_cells.sp +++ b/examples/cmos/cmos_cells.sp @@ -36,4 +36,3 @@ X1 nC D t DLATCH X2 C t Q DLATCH X3 C nC NOT .ENDS DFF - diff --git a/examples/cmos/cmos_cells.v b/examples/cmos/cmos_cells.v index 27278facb..9a855ab8c 100644 --- a/examples/cmos/cmos_cells.v +++ b/examples/cmos/cmos_cells.v @@ -41,4 +41,3 @@ always @(posedge C, posedge S, posedge R) else Q <= D; endmodule - diff --git a/examples/cmos/cmos_cells_digital.sp b/examples/cmos/cmos_cells_digital.sp index e1cb82a2f..89f844094 100644 --- a/examples/cmos/cmos_cells_digital.sp +++ b/examples/cmos/cmos_cells_digital.sp @@ -28,4 +28,3 @@ Alatch D E null null Q nQ latch1 .model dff1 d_dff Adff D C null null Q nQ dff1 .ENDS DFF - diff --git a/examples/cmos/counter_digital.ys b/examples/cmos/counter_digital.ys index a5e728e02..eef353e98 100644 --- a/examples/cmos/counter_digital.ys +++ b/examples/cmos/counter_digital.ys @@ -13,4 +13,3 @@ abc -liberty cmos_cells.lib;; write_verilog synth.v write_spice -neg 0s -pos 1s synth.sp - diff --git a/examples/cmos/testbench.sh b/examples/cmos/testbench.sh index 856169ab9..6928b71a2 100644 --- a/examples/cmos/testbench.sh +++ b/examples/cmos/testbench.sh @@ -4,4 +4,3 @@ set -ex ../../yosys counter.ys ngspice testbench.sp - diff --git a/examples/cmos/testbench_digital.sh b/examples/cmos/testbench_digital.sh index 2e70e874c..1a27925b1 100644 --- a/examples/cmos/testbench_digital.sh +++ b/examples/cmos/testbench_digital.sh @@ -12,4 +12,3 @@ iverilog -o counter_tb counter.v counter_tb.v # requires ngspice with xspice support enabled: ngspice testbench_digital.sp - diff --git a/examples/cxx-api/demomain.cc b/examples/cxx-api/demomain.cc index c63edbdf0..7ab9324fa 100644 --- a/examples/cxx-api/demomain.cc +++ b/examples/cxx-api/demomain.cc @@ -19,4 +19,3 @@ int main() Yosys::yosys_shutdown(); return 0; } - diff --git a/examples/gowin/README b/examples/gowin/README index 0194e9f09..75076fde5 100644 --- a/examples/gowin/README +++ b/examples/gowin/README @@ -14,4 +14,3 @@ gowinTool_linux directory 3.) edit gowinTool_linux/bin/gwlicense.ini. Set lic="..." to the full path to the license file. - diff --git a/examples/gowin/demo.cst b/examples/gowin/demo.cst index c8f89dcf8..2be79f694 100644 --- a/examples/gowin/demo.cst +++ b/examples/gowin/demo.cst @@ -7,4 +7,4 @@ IO_LOC "leds[3]" 82; IO_LOC "leds[4]" 83; IO_LOC "leds[5]" 84; IO_LOC "leds[6]" 85; -IO_LOC "leds[7]" 86; \ No newline at end of file +IO_LOC "leds[7]" 86; diff --git a/examples/intel/DE2i-150/quartus_compile/de2i.qsf b/examples/intel/DE2i-150/quartus_compile/de2i.qsf index 5a230155f..99245b607 100644 --- a/examples/intel/DE2i-150/quartus_compile/de2i.qsf +++ b/examples/intel/DE2i-150/quartus_compile/de2i.qsf @@ -1096,4 +1096,4 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/examples/intel/MAX10/runme_postsynth b/examples/intel/MAX10/runme_postsynth index 657c05fa8..70bad061d 100644 --- a/examples/intel/MAX10/runme_postsynth +++ b/examples/intel/MAX10/runme_postsynth @@ -2,4 +2,3 @@ iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v) vvp -N verif_post - diff --git a/examples/intel/asicworld_lfsr/runme_postsynth b/examples/intel/asicworld_lfsr/runme_postsynth index ad5ca39d4..56a232eb3 100755 --- a/examples/intel/asicworld_lfsr/runme_postsynth +++ b/examples/intel/asicworld_lfsr/runme_postsynth @@ -2,4 +2,3 @@ iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v) vvp -N verif_post - diff --git a/examples/intel/asicworld_lfsr/runme_presynth b/examples/intel/asicworld_lfsr/runme_presynth index 3ed6618d3..9a83b1bbd 100755 --- a/examples/intel/asicworld_lfsr/runme_presynth +++ b/examples/intel/asicworld_lfsr/runme_presynth @@ -2,4 +2,4 @@ iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\ -vvp -N presynth \ No newline at end of file +vvp -N presynth diff --git a/examples/osu035/Makefile b/examples/osu035/Makefile index 2bb8162b3..ce3c36269 100644 --- a/examples/osu035/Makefile +++ b/examples/osu035/Makefile @@ -10,4 +10,3 @@ osu035_stdcells.lib: clean: rm -f osu035_stdcells.lib rm -f example.yslog example.edif - diff --git a/examples/smtbmc/Makefile b/examples/smtbmc/Makefile index af937ea74..54dd2dac4 100644 --- a/examples/smtbmc/Makefile +++ b/examples/smtbmc/Makefile @@ -74,4 +74,3 @@ clean: rm -f glift_mux.ys .PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9 clean - diff --git a/examples/smtbmc/demo9.v b/examples/smtbmc/demo9.v index f0b91e2ca..bbfbf11b8 100644 --- a/examples/smtbmc/demo9.v +++ b/examples/smtbmc/demo9.v @@ -10,4 +10,3 @@ module demo9; cover(1); end endmodule - diff --git a/frontends/ast/dpicall.cc b/frontends/ast/dpicall.cc index b4e4c6f15..3b1d13b09 100644 --- a/frontends/ast/dpicall.cc +++ b/frontends/ast/dpicall.cc @@ -161,4 +161,3 @@ std::unique_ptr AST::dpi_call(AstSrcLocType, const std::string&, c YOSYS_NAMESPACE_END #endif /* YOSYS_ENABLE_LIBFFI */ - diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 2eae64fa1..220c317ec 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -691,4 +691,3 @@ struct BlifFrontend : public Frontend { } BlifFrontend; YOSYS_NAMESPACE_END - diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 447f438a8..96db2f640 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -836,5 +836,3 @@ skip_cell:; } LibertyFrontend; YOSYS_NAMESPACE_END - - diff --git a/frontends/verific/README b/frontends/verific/README index 921873af3..0e8b76f35 100644 --- a/frontends/verific/README +++ b/frontends/verific/README @@ -34,4 +34,3 @@ should be something like this: SBY [example] summary: engine_0 (smtbmc yices) returned PASS for induction SBY [example] summary: successful proof by k-induction. SBY [example] DONE (PASS, rc=0) - diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 62a7f7bbb..7b45370ae 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -713,4 +713,3 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { <*>. { BEGIN(0); return char_tok(*YYText(), out_loc); } %% - diff --git a/kernel/calc.cc b/kernel/calc.cc index 84ac100ab..685326f82 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -712,4 +712,3 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar } YOSYS_NAMESPACE_END - diff --git a/kernel/cellhelp.py b/kernel/cellhelp.py index 741558730..f834ead83 100644 --- a/kernel/cellhelp.py +++ b/kernel/cellhelp.py @@ -97,4 +97,3 @@ for line in fileinput.input(): print(simHelper) # new simHelper = SimHelper() - diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h index 5ac9d1c3e..d5ca316b1 100644 --- a/kernel/compressor_tree.h +++ b/kernel/compressor_tree.h @@ -114,4 +114,4 @@ FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode); YOSYS_NAMESPACE_END -#endif // COMPRESSOR_TREE_H \ No newline at end of file +#endif // COMPRESSOR_TREE_H diff --git a/kernel/json.cc b/kernel/json.cc index 738746267..dc3a110cf 100644 --- a/kernel/json.cc +++ b/kernel/json.cc @@ -169,4 +169,3 @@ void PrettyJson::entry_json(const char *name, const Json &value) this->name(name); this->value(value); } - diff --git a/kernel/mem.cc b/kernel/mem.cc index 2f7f16c7a..63f07aad0 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -1915,4 +1915,4 @@ RTLIL::Const::iterator MemContents::_range_write(RTLIL::Const::iterator it, RTLI auto it_next = std::next(it, _data_width); std::fill(to_end, it_next, State::S0); return it_next; -} \ No newline at end of file +} diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index cfd5d8af8..9dff6fa45 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -401,4 +401,3 @@ struct DesignPass : public Pass { } DesignPass; YOSYS_NAMESPACE_END - diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index c1355da25..d96c269ce 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -282,4 +282,3 @@ struct OptLutInsPass : public Pass { } OptLutInsPass; PRIVATE_NAMESPACE_END - diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index fe5157934..f25eb8a8c 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -347,4 +347,3 @@ struct OptMemFeedbackPass : public Pass { } OptMemFeedbackPass; PRIVATE_NAMESPACE_END - diff --git a/passes/opt/opt_mem_priority.cc b/passes/opt/opt_mem_priority.cc index a9b145bea..352a3f919 100644 --- a/passes/opt/opt_mem_priority.cc +++ b/passes/opt/opt_mem_priority.cc @@ -106,4 +106,3 @@ struct OptMemPriorityPass : public Pass { } OptMemPriorityPass; PRIVATE_NAMESPACE_END - diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index d70299ab8..2ba01d26b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -650,4 +650,3 @@ struct WreducePass : public Pass { } WreducePass; PRIVATE_NAMESPACE_END - diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc index e79d24e96..2535d716b 100644 --- a/passes/proc/proc_memwr.cc +++ b/passes/proc/proc_memwr.cc @@ -117,4 +117,3 @@ struct ProcMemWrPass : public Pass { } ProcMemWrPass; PRIVATE_NAMESPACE_END - diff --git a/passes/sat/example.v b/passes/sat/example.v index aa0ddb6e3..ee6545fab 100644 --- a/passes/sat/example.v +++ b/passes/sat/example.v @@ -82,4 +82,3 @@ always @(posedge clk) assign y = counter == 12; endmodule - diff --git a/passes/sat/example.ys b/passes/sat/example.ys index cc72faac0..b6615eee9 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -11,4 +11,3 @@ sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004 sat -prove y 1'b0 -show rst,counter,y -ignore_unknown_cells example004 sat -prove y 1'b0 -tempinduct -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 - diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc index 39217f817..2c5d51386 100644 --- a/passes/techmap/arith_tree.cc +++ b/passes/techmap/arith_tree.cc @@ -487,4 +487,4 @@ struct ArithTreePass : public Pass { } } ArithTreePass; -PRIVATE_NAMESPACE_END \ No newline at end of file +PRIVATE_NAMESPACE_END diff --git a/passes/techmap/filterlib.cc b/passes/techmap/filterlib.cc index 05cfa6d24..f553527d3 100644 --- a/passes/techmap/filterlib.cc +++ b/passes/techmap/filterlib.cc @@ -1,4 +1,3 @@ #define FILTERLIB #include "libparse.cc" - diff --git a/passes/techmap/liberty_cache.h b/passes/techmap/liberty_cache.h index 8ae89947f..01a7bf395 100644 --- a/passes/techmap/liberty_cache.h +++ b/passes/techmap/liberty_cache.h @@ -142,4 +142,4 @@ inline std::string convert_liberty_files_to_merged_scl(const std::vector DSP48E1.PCIN # (see above for explanation) select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i - diff --git a/tests/arith_tree/arith_tree_alu_macc_equiv.ys b/tests/arith_tree/arith_tree_alu_macc_equiv.ys index 165bf5975..da2552107 100644 --- a/tests/arith_tree/arith_tree_alu_macc_equiv.ys +++ b/tests/arith_tree/arith_tree_alu_macc_equiv.ys @@ -104,4 +104,4 @@ equiv_opt -assert arith_tree design -load postopt select -assert-min 1 t:$fa select -assert-count 1 t:$add -design -reset \ No newline at end of file +design -reset diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys index 6bb960ae4..a657d4338 100644 --- a/tests/arith_tree/arith_tree_final_adder.ys +++ b/tests/arith_tree/arith_tree_final_adder.ys @@ -67,4 +67,3 @@ select -assert-none t:$add select -assert-min 1 t:$_AND_ select -assert-min 1 t:$_XOR_ design -reset - diff --git a/tests/asicworld/code_hdl_models_up_counter.v b/tests/asicworld/code_hdl_models_up_counter.v index e05302182..45dd08f16 100644 --- a/tests/asicworld/code_hdl_models_up_counter.v +++ b/tests/asicworld/code_hdl_models_up_counter.v @@ -26,4 +26,3 @@ end endmodule - diff --git a/tests/asicworld/code_verilog_tutorial_counter_tb.v b/tests/asicworld/code_verilog_tutorial_counter_tb.v index 33d540509..e2902d1e5 100644 --- a/tests/asicworld/code_verilog_tutorial_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_counter_tb.v @@ -98,4 +98,3 @@ if (count_compare != count) begin end endmodule - diff --git a/tests/bram/generate_mk.py b/tests/bram/generate_mk.py index 09f5c650b..5b320543b 100644 --- a/tests/bram/generate_mk.py +++ b/tests/bram/generate_mk.py @@ -324,4 +324,3 @@ def create_tests(): ) gen_tests_makefile.generate_custom(create_tests) - diff --git a/tests/errors/syntax_err01.v b/tests/errors/syntax_err01.v index 68e9b1d50..44e23dc13 100644 --- a/tests/errors/syntax_err01.v +++ b/tests/errors/syntax_err01.v @@ -1,4 +1,3 @@ module a; integer [31:0]w; endmodule - diff --git a/tests/errors/syntax_err02.v b/tests/errors/syntax_err02.v index c72e976a8..78b076d2d 100644 --- a/tests/errors/syntax_err02.v +++ b/tests/errors/syntax_err02.v @@ -4,4 +4,3 @@ task to ( ); endtask endmodule - diff --git a/tests/errors/syntax_err03.v b/tests/errors/syntax_err03.v index 6eec44ade..ec43bcc09 100644 --- a/tests/errors/syntax_err03.v +++ b/tests/errors/syntax_err03.v @@ -4,4 +4,3 @@ task to ( ); endtask endmodule - diff --git a/tests/errors/syntax_err04.v b/tests/errors/syntax_err04.v index d488e5dbb..dce45a49b 100644 --- a/tests/errors/syntax_err04.v +++ b/tests/errors/syntax_err04.v @@ -1,4 +1,3 @@ module a; wire [3]x; endmodule - diff --git a/tests/errors/syntax_err05.v b/tests/errors/syntax_err05.v index 8a1f11532..0d134b692 100644 --- a/tests/errors/syntax_err05.v +++ b/tests/errors/syntax_err05.v @@ -1,4 +1,3 @@ module a; input x[2:0]; endmodule - diff --git a/tests/errors/syntax_err06.v b/tests/errors/syntax_err06.v index b35a1dea2..ca1dc5ba7 100644 --- a/tests/errors/syntax_err06.v +++ b/tests/errors/syntax_err06.v @@ -3,4 +3,3 @@ initial begin : label1 end: label2 endmodule - diff --git a/tests/errors/syntax_err07.v b/tests/errors/syntax_err07.v index 62bcc6b3e..207fd8a93 100644 --- a/tests/errors/syntax_err07.v +++ b/tests/errors/syntax_err07.v @@ -3,4 +3,3 @@ wire [5:0]x; wire [3:0]y; assign y = (4)55; endmodule - diff --git a/tests/errors/syntax_err08.v b/tests/errors/syntax_err08.v index d41bfd6c9..28617ab75 100644 --- a/tests/errors/syntax_err08.v +++ b/tests/errors/syntax_err08.v @@ -3,4 +3,3 @@ wire [5:0]x; wire [3:0]y; assign y = x 55; endmodule - diff --git a/tests/errors/syntax_err09.v b/tests/errors/syntax_err09.v index 1e472eb94..9db022768 100644 --- a/tests/errors/syntax_err09.v +++ b/tests/errors/syntax_err09.v @@ -1,3 +1,2 @@ module a(input wire x = 1'b0); endmodule - diff --git a/tests/errors/syntax_err13.v b/tests/errors/syntax_err13.v index b5c942fca..35843df58 100644 --- a/tests/errors/syntax_err13.v +++ b/tests/errors/syntax_err13.v @@ -1,4 +1,3 @@ module a #(p = 0) (); endmodule - diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py index 9a44821d3..40bc9188f 100644 --- a/tests/functional/rtlil_cells.py +++ b/tests/functional/rtlil_cells.py @@ -378,4 +378,4 @@ def generate_test_cases(per_cell, rnd): names.append(f'{cell.name}-{name}' if name != '' else cell.name) if per_cell is not None and len(seen_names) >= per_cell: break - return (names, tests) \ No newline at end of file + return (names, tests) diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py index c23be440e..73e28b2b2 100644 --- a/tests/functional/smt_vcd.py +++ b/tests/functional/smt_vcd.py @@ -185,4 +185,4 @@ def simulate_smt(smt_file_path, vcd_path, num_steps, rnd): try: simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd) finally: - smt_io.p_close() \ No newline at end of file + smt_io.p_close() diff --git a/tests/hana/README b/tests/hana/README index 2081fb10f..0ff6855cf 100644 --- a/tests/hana/README +++ b/tests/hana/README @@ -1,4 +1,3 @@ These test cases are copied from the hana project: https://sourceforge.net/projects/sim-sim/ - diff --git a/tests/hana/hana_vlib.v b/tests/hana/hana_vlib.v index fc82f1389..a8921bcfd 100644 --- a/tests/hana/hana_vlib.v +++ b/tests/hana/hana_vlib.v @@ -1136,4 +1136,3 @@ module INC64 #(parameter SIZE = 64) (input [SIZE-1:0] in, output [SIZE:0] out); assign out = in + 1; endmodule - diff --git a/tests/hana/test_simulation_decoder.v b/tests/hana/test_simulation_decoder.v index ef9045aad..2a102a903 100644 --- a/tests/hana/test_simulation_decoder.v +++ b/tests/hana/test_simulation_decoder.v @@ -216,4 +216,3 @@ always @(in or enable) endcase end endmodule - diff --git a/tests/hana/test_simulation_vlib.v b/tests/hana/test_simulation_vlib.v index 7d3af09c2..cdf3c56db 100644 --- a/tests/hana/test_simulation_vlib.v +++ b/tests/hana/test_simulation_vlib.v @@ -62,4 +62,3 @@ VCC synth_VCC_1(.out( synth_net_4)); VCC synth_VCC_2(.out(synth_net_10)); endmodule - diff --git a/tests/liberty/XNOR2X1.lib b/tests/liberty/XNOR2X1.lib index 0bb285ef7..67ae8b706 100644 --- a/tests/liberty/XNOR2X1.lib +++ b/tests/liberty/XNOR2X1.lib @@ -334,4 +334,4 @@ library (ls05_stdcells) { } } } -} \ No newline at end of file +} diff --git a/tests/liberty/idranges.lib b/tests/liberty/idranges.lib index 7149f19ee..890161403 100644 --- a/tests/liberty/idranges.lib +++ b/tests/liberty/idranges.lib @@ -3,4 +3,3 @@ library("foobar") { bar : baz[0] ; } } - diff --git a/tests/liberty/non-ascii.lib b/tests/liberty/non-ascii.lib index 1ac636e34..92e9f7b77 100644 --- a/tests/liberty/non-ascii.lib +++ b/tests/liberty/non-ascii.lib @@ -11,4 +11,4 @@ library(dummy) { function : "A" ; } } -} \ No newline at end of file +} diff --git a/tests/liberty/retention.lib b/tests/liberty/retention.lib index d2f1aa325..5a38b6623 100644 --- a/tests/liberty/retention.lib +++ b/tests/liberty/retention.lib @@ -54,4 +54,4 @@ library (retention) { direction : input; } } -} \ No newline at end of file +} diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib index f7c20750a..a58bb7fe1 100644 --- a/tests/liberty/semicolmissing.lib +++ b/tests/liberty/semicolmissing.lib @@ -68,5 +68,3 @@ library(supergate) { } } /* end */ - - diff --git a/tests/memlib/generate_mk.py b/tests/memlib/generate_mk.py index 13b62b1d8..230d2ebd6 100644 --- a/tests/memlib/generate_mk.py +++ b/tests/memlib/generate_mk.py @@ -1588,4 +1588,3 @@ extra = [ "endif", ] gen_tests_makefile.generate_custom(create_tests, extra) - diff --git a/tests/memlib/memlib_lut.txt b/tests/memlib/memlib_lut.txt index 9f6d84123..7b99dcd61 100644 --- a/tests/memlib/memlib_lut.txt +++ b/tests/memlib/memlib_lut.txt @@ -25,4 +25,3 @@ ram distributed \RAM_LUT { clock anyedge; } } - diff --git a/tests/memlib/memlib_wide_write.v b/tests/memlib/memlib_wide_write.v index afed6d00c..25502b61d 100644 --- a/tests/memlib/memlib_wide_write.v +++ b/tests/memlib/memlib_wide_write.v @@ -26,4 +26,3 @@ always @(posedge PORT_A_CLK) begin end endmodule - diff --git a/tests/memories/amber23_sram_byte_en.v b/tests/memories/amber23_sram_byte_en.v index 3554af887..317994d9a 100644 --- a/tests/memories/amber23_sram_byte_en.v +++ b/tests/memories/amber23_sram_byte_en.v @@ -81,4 +81,3 @@ always @(posedge i_clk) end endmodule - diff --git a/tests/memories/read_arst.v b/tests/memories/read_arst.v index 6100cc4a7..72b584e0c 100644 --- a/tests/memories/read_arst.v +++ b/tests/memories/read_arst.v @@ -24,4 +24,3 @@ always @(posedge clk, posedge reset) begin end endmodule - diff --git a/tests/memories/wide_read_async.v b/tests/memories/wide_read_async.v index aecdb1938..dd6f25dcb 100644 --- a/tests/memories/wide_read_async.v +++ b/tests/memories/wide_read_async.v @@ -24,4 +24,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/memories/wide_read_mixed.v b/tests/memories/wide_read_mixed.v index c36db3d31..64a32c2a2 100644 --- a/tests/memories/wide_read_mixed.v +++ b/tests/memories/wide_read_mixed.v @@ -43,4 +43,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/memories/wide_read_sync.v b/tests/memories/wide_read_sync.v index 54ba3f256..447161186 100644 --- a/tests/memories/wide_read_sync.v +++ b/tests/memories/wide_read_sync.v @@ -29,4 +29,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/memories/wide_read_trans.v b/tests/memories/wide_read_trans.v index fe3293500..f7d827f79 100644 --- a/tests/memories/wide_read_trans.v +++ b/tests/memories/wide_read_trans.v @@ -37,4 +37,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/opt/opt_dff_qd.ys b/tests/opt/opt_dff_qd.ys index c6232643f..bf4be9749 100644 --- a/tests/opt/opt_dff_qd.ys +++ b/tests/opt/opt_dff_qd.ys @@ -47,4 +47,3 @@ select -assert-count 6 t:$_DFFE_??_ select -assert-count 4 t:$_DLATCH_?_ select -assert-count 4 t:$_SR_??_ select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i - diff --git a/tests/opt/opt_dff_srst.ys b/tests/opt/opt_dff_srst.ys index 4a77de0b8..2b660bfc7 100644 --- a/tests/opt/opt_dff_srst.ys +++ b/tests/opt/opt_dff_srst.ys @@ -110,4 +110,3 @@ select -assert-count 2 t:$_DFF_P_ select -assert-count 4 t:$_DFFE_PP_ design -reset - diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 61b54a92f..72288591e 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -374,4 +374,4 @@ EOF scratchpad -set opt.did_something false opt_expr -scratchpad -assert opt.did_something false \ No newline at end of file +scratchpad -assert opt.did_something false diff --git a/tests/opt/opt_expr_mux_undef.ys b/tests/opt/opt_expr_mux_undef.ys index 83c29e07b..499ceeca8 100644 --- a/tests/opt/opt_expr_mux_undef.ys +++ b/tests/opt/opt_expr_mux_undef.ys @@ -287,4 +287,3 @@ select -assert-none t:$_MUX16_ select -assert-count 1 o:out %ci* ########## - diff --git a/tests/opt/opt_merge_properties.ys b/tests/opt/opt_merge_properties.ys index dddc13bfb..bbe70900b 100644 --- a/tests/opt/opt_merge_properties.ys +++ b/tests/opt/opt_merge_properties.ys @@ -13,4 +13,3 @@ chformal -lower clean opt_merge select -assert-count 2 t:$cover - diff --git a/tests/opt/opt_share_bug2538.ys b/tests/opt/opt_share_bug2538.ys index 7261c6695..dfecc3b35 100644 --- a/tests/opt/opt_share_bug2538.ys +++ b/tests/opt/opt_share_bug2538.ys @@ -17,4 +17,3 @@ EOT proc alumacc equiv_opt -assert opt_share - diff --git a/tests/pyosys/test_sigspec_it.py b/tests/pyosys/test_sigspec_it.py index 2876e7725..c875b1928 100644 --- a/tests/pyosys/test_sigspec_it.py +++ b/tests/pyosys/test_sigspec_it.py @@ -25,4 +25,3 @@ module = d.module(r"\spm") for conn_from, conn_to in module.connections_: for bit_from, bit_to in zip(conn_from, conn_to): print(f"assign {_dump_sigbit(bit_from)} = {_dump_sigbit(bit_to)};") - diff --git a/tests/rtlil/.gitignore b/tests/rtlil/.gitignore index abe251a76..36445e53c 100644 --- a/tests/rtlil/.gitignore +++ b/tests/rtlil/.gitignore @@ -1 +1 @@ -/temp \ No newline at end of file +/temp diff --git a/tests/sat/alu.v b/tests/sat/alu.v index 9826fe05d..820740b7d 100644 --- a/tests/sat/alu.v +++ b/tests/sat/alu.v @@ -76,4 +76,3 @@ module alu( result <= tmp[7:0]; end endmodule - diff --git a/tests/sat/asserts_seq.v b/tests/sat/asserts_seq.v index 9715104f3..3fcf2d659 100644 --- a/tests/sat/asserts_seq.v +++ b/tests/sat/asserts_seq.v @@ -84,4 +84,3 @@ module test_005(clk, a, a_old, b); assert(a_old != b); end endmodule - diff --git a/tests/sat/asserts_seq.ys b/tests/sat/asserts_seq.ys index db94f94ea..f73fdee90 100644 --- a/tests/sat/asserts_seq.ys +++ b/tests/sat/asserts_seq.ys @@ -12,4 +12,3 @@ sat -falsify -prove-asserts -seq 2 test_002 sat -falsify -prove-asserts -seq 2 test_003 sat -falsify -prove-asserts -seq 2 test_004 sat -verify -prove-asserts -seq 2 test_005 - diff --git a/tests/sat/counters-repeat.v b/tests/sat/counters-repeat.v index 2ea45499a..340fc8d94 100644 --- a/tests/sat/counters-repeat.v +++ b/tests/sat/counters-repeat.v @@ -35,4 +35,3 @@ module counter2(clk, rst, ping); assign ping = &count; endmodule - diff --git a/tests/sat/counters-repeat.ys b/tests/sat/counters-repeat.ys index b3dcfe08a..f9b096300 100644 --- a/tests/sat/counters-repeat.ys +++ b/tests/sat/counters-repeat.ys @@ -7,4 +7,3 @@ miter -equiv -make_assert -make_outputs counter1 counter2 miter cd miter; flatten; opt sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs - diff --git a/tests/sat/counters.v b/tests/sat/counters.v index 09e273044..fd4451495 100644 --- a/tests/sat/counters.v +++ b/tests/sat/counters.v @@ -32,4 +32,3 @@ module counter2(clk, rst, ping); assign ping = &count; endmodule - diff --git a/tests/sat/counters.ys b/tests/sat/counters.ys index 330895f82..89f03d214 100644 --- a/tests/sat/counters.ys +++ b/tests/sat/counters.ys @@ -7,4 +7,3 @@ miter -equiv -make_assert -make_outputs counter1 counter2 miter cd miter; flatten; opt sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs - diff --git a/tests/sat/expose_dff.v b/tests/sat/expose_dff.v index 708e2da3a..28db5d103 100644 --- a/tests/sat/expose_dff.v +++ b/tests/sat/expose_dff.v @@ -30,4 +30,3 @@ always @(posedge clk, negedge rst_n) else y <= a != 0; endmodule - diff --git a/tests/sat/expose_dff.ys b/tests/sat/expose_dff.ys index 95556840a..aa5d9f352 100644 --- a/tests/sat/expose_dff.ys +++ b/tests/sat/expose_dff.ys @@ -12,4 +12,3 @@ flatten miter34; opt miter34 sat -verify -prove trigger 0 miter12 sat -verify -prove trigger 0 miter34 - diff --git a/tests/sat/share.v b/tests/sat/share.v index 29e423137..0aed31be3 100644 --- a/tests/sat/share.v +++ b/tests/sat/share.v @@ -52,4 +52,3 @@ module test_3( if (9 <= s && s < 12) y3 <= b / a; end endmodule - diff --git a/tests/sdc/alu_sub.v b/tests/sdc/alu_sub.v index d66cad18e..3f971417a 100644 --- a/tests/sdc/alu_sub.v +++ b/tests/sdc/alu_sub.v @@ -59,4 +59,3 @@ module alu( result <= tmp[7:0]; end endmodule - diff --git a/tests/sdc/side-effects.sdc b/tests/sdc/side-effects.sdc index 2c2126f84..890f5652f 100644 --- a/tests/sdc/side-effects.sdc +++ b/tests/sdc/side-effects.sdc @@ -1,2 +1,2 @@ puts "This should print something:" -puts [get_ports {A[0]}] \ No newline at end of file +puts [get_ports {A[0]}] diff --git a/tests/sim/assume_x_first_step.ys b/tests/sim/assume_x_first_step.ys index 3922e06f6..20c759950 100644 --- a/tests/sim/assume_x_first_step.ys +++ b/tests/sim/assume_x_first_step.ys @@ -1,2 +1,2 @@ read_verilog simple_assign.v -sim -r simple_assign.vcd -scope simple_assign \ No newline at end of file +sim -r simple_assign.vcd -scope simple_assign diff --git a/tests/sim/simple_assign.vcd b/tests/sim/simple_assign.vcd index c4494fadf..b84cd54a9 100644 --- a/tests/sim/simple_assign.vcd +++ b/tests/sim/simple_assign.vcd @@ -10,4 +10,4 @@ b1 n1 b1 n2 #10 b0 n1 -b0 n2 \ No newline at end of file +b0 n2 diff --git a/tests/sim/vcd_var_reference_whitespace.ys b/tests/sim/vcd_var_reference_whitespace.ys index 8e17821d2..26e3f5dec 100644 --- a/tests/sim/vcd_var_reference_whitespace.ys +++ b/tests/sim/vcd_var_reference_whitespace.ys @@ -1,3 +1,3 @@ read_rtlil vector_assign.il sim -r var_reference_without_whitespace.vcd -scope tb.uut -sim -r var_reference_with_whitespace.vcd -scope tb.uut \ No newline at end of file +sim -r var_reference_with_whitespace.vcd -scope tb.uut diff --git a/tests/simple/aes_kexp128.v b/tests/simple/aes_kexp128.v index 3ee034789..90efcc251 100644 --- a/tests/simple/aes_kexp128.v +++ b/tests/simple/aes_kexp128.v @@ -21,4 +21,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/simple/arraycells.v b/tests/simple/arraycells.v index fd85a1195..e54870f90 100644 --- a/tests/simple/arraycells.v +++ b/tests/simple/arraycells.v @@ -12,4 +12,3 @@ module aoi12(a, b, c, y); output y; assign y = ~((a & b) | c); endmodule - diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v index d6e36fb80..38bda4c0d 100644 --- a/tests/simple/attrib01_module.v +++ b/tests/simple/attrib01_module.v @@ -18,4 +18,3 @@ module attrib01_foo(clk, rst, inp, out); attrib01_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v index 989213b77..0c6b1545f 100644 --- a/tests/simple/attrib02_port_decl.v +++ b/tests/simple/attrib02_port_decl.v @@ -22,4 +22,3 @@ module attrib02_foo(clk, rst, inp, out); attrib02_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v index d2ae98978..4a84b25df 100644 --- a/tests/simple/attrib03_parameter.v +++ b/tests/simple/attrib03_parameter.v @@ -25,4 +25,3 @@ module attrib03_foo(clk, rst, inp, out); attrib03_bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v index 98826e971..76118d56d 100644 --- a/tests/simple/attrib04_net_var.v +++ b/tests/simple/attrib04_net_var.v @@ -29,4 +29,3 @@ module attrib04_foo(clk, rst, inp, out); attrib04_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED index 8cc471f4e..3e256e912 100644 --- a/tests/simple/attrib05_port_conn.v.DISABLED +++ b/tests/simple/attrib05_port_conn.v.DISABLED @@ -18,4 +18,3 @@ module attrib05_foo(clk, rst, inp, out); attrib05_bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); endmodule - diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v index 2bc136f9a..8331172b6 100644 --- a/tests/simple/attrib06_operator_suffix.v +++ b/tests/simple/attrib06_operator_suffix.v @@ -20,4 +20,3 @@ module attrib06_foo(clk, rst, inp_a, inp_b, out); attrib06_bar bar_instance (clk, rst, inp_a, inp_b, out); endmodule - diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED index 282fc5da7..5b76aefc1 100644 --- a/tests/simple/attrib07_func_call.v.DISABLED +++ b/tests/simple/attrib07_func_call.v.DISABLED @@ -18,4 +18,3 @@ module attri07_foo(clk, rst, inp_a, inp_b, out); else out <= attrib07_do_add (* combinational_adder *) (inp_a, inp_b); endmodule - diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v index 759e67c7b..582f3876d 100644 --- a/tests/simple/attrib08_mod_inst.v +++ b/tests/simple/attrib08_mod_inst.v @@ -19,4 +19,3 @@ module attrib08_foo(clk, rst, inp, out); (* my_module_instance = 99 *) attrib08_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v index a72b81dda..d569749ca 100644 --- a/tests/simple/attrib09_case.v +++ b/tests/simple/attrib09_case.v @@ -23,4 +23,3 @@ module attrib09_foo(clk, rst, inp, out); attrib09_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v index 7765d6e2a..528513b9f 100644 --- a/tests/simple/dff_different_styles.v +++ b/tests/simple/dff_different_styles.v @@ -101,5 +101,3 @@ always @(posedge clk, posedge preset, posedge clear) begin q <= d; end endmodule - - diff --git a/tests/simple/fsm.v b/tests/simple/fsm.v index 2dba14bb0..26dbd7624 100644 --- a/tests/simple/fsm.v +++ b/tests/simple/fsm.v @@ -66,4 +66,3 @@ begin end endmodule - diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v index b03044fde..b76543372 100644 --- a/tests/simple/hierarchy.v +++ b/tests/simple/hierarchy.v @@ -24,4 +24,3 @@ assign y2 = b; assign y3 = c; assign y4 = d; endmodule - diff --git a/tests/simple/i2c_master_tests.v b/tests/simple/i2c_master_tests.v index 3aa596632..958c5b0e9 100644 --- a/tests/simple/i2c_master_tests.v +++ b/tests/simple/i2c_master_tests.v @@ -59,4 +59,3 @@ module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt); cmd_stop <= #1 cmd; endmodule - diff --git a/tests/simple/loops.v b/tests/simple/loops.v index d7743a422..ffd6245b2 100644 --- a/tests/simple/loops.v +++ b/tests/simple/loops.v @@ -76,4 +76,3 @@ begin end endmodule - diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v index 88d0553b9..11ba27015 100644 --- a/tests/simple/mem_arst.v +++ b/tests/simple/mem_arst.v @@ -38,4 +38,3 @@ module MyMem #( end endmodule - diff --git a/tests/simple/memory.v b/tests/simple/memory.v index a6a280992..4f720a484 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -317,4 +317,3 @@ module memtest13 ( end end endmodule - diff --git a/tests/simple/muxtree.v b/tests/simple/muxtree.v index 1fb1cea5e..b02bbb06d 100644 --- a/tests/simple/muxtree.v +++ b/tests/simple/muxtree.v @@ -80,4 +80,3 @@ module select_leaves(input R, C, D, output reg Q); else Q <= Q ? Q : D ? D : Q; endmodule - diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v index 569a28adb..2b0d144c2 100644 --- a/tests/simple/omsp_dbg_uart.v +++ b/tests/simple/omsp_dbg_uart.v @@ -31,4 +31,3 @@ assign cmd_valid = (uart_state==RX_CMD) & xfer_done; assign xfer_done = uart_state!=RX_SYNC; endmodule - diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v index 23cb276f2..a404c07da 100644 --- a/tests/simple/paramods.v +++ b/tests/simple/paramods.v @@ -50,4 +50,3 @@ output [width-1:0] out; assign out = in + step; endmodule - diff --git a/tests/simple/process.v b/tests/simple/process.v index 8cb4c870e..3be002bbb 100644 --- a/tests/simple/process.v +++ b/tests/simple/process.v @@ -81,4 +81,3 @@ end else begin end endmodule - diff --git a/tests/simple/rotate.v b/tests/simple/rotate.v index a2fe00055..e1fd2e408 100644 --- a/tests/simple/rotate.v +++ b/tests/simple/rotate.v @@ -45,4 +45,3 @@ end endfunction endmodule - diff --git a/tests/simple/specify.v b/tests/simple/specify.v index 2c784ef6d..a8b87f53b 100644 --- a/tests/simple/specify.v +++ b/tests/simple/specify.v @@ -28,4 +28,3 @@ specparam c=1:2:3; endspecify endmodule - diff --git a/tests/simple/usb_phy_tests.v b/tests/simple/usb_phy_tests.v index bc45e71a5..dcc5ace4f 100644 --- a/tests/simple/usb_phy_tests.v +++ b/tests/simple/usb_phy_tests.v @@ -33,4 +33,3 @@ always @* end endmodule - diff --git a/tests/simple/values.v b/tests/simple/values.v index afcd251fc..c69b57176 100644 --- a/tests/simple/values.v +++ b/tests/simple/values.v @@ -41,4 +41,3 @@ always @* endcase endmodule - diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index 5fcedbff1..e36c971f7 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -79,4 +79,3 @@ endmodule // output signed [5:0] y; // assign y = -(5'd27); // endmodule - diff --git a/tests/smv/run-single.sh b/tests/smv/run-single.sh index 62ed2cee3..452187425 100644 --- a/tests/smv/run-single.sh +++ b/tests/smv/run-single.sh @@ -30,4 +30,3 @@ set -ex ../../yosys -l $1.log -q $1.ys NuSMV -bmc $1.smv >> $1.log grep "^-- invariant .* is true" $1.log - diff --git a/tests/smv/run-test.sh b/tests/smv/run-test.sh index c8264ac8a..7df3b65f1 100755 --- a/tests/smv/run-test.sh +++ b/tests/smv/run-test.sh @@ -16,4 +16,3 @@ all: $(addsuffix .ok,$(basename $(wildcard temp/test_*.il))) EOT ${MAKE:-make} -f temp/makefile - diff --git a/tests/sva/Makefile b/tests/sva/Makefile index d8c206664..a562012db 100644 --- a/tests/sva/Makefile +++ b/tests/sva/Makefile @@ -13,4 +13,3 @@ clean: rm -rf $(addsuffix _pass.sby,$(TESTS)) $(addsuffix _pass,$(TESTS)) rm -rf $(addsuffix _fail.sby,$(TESTS)) $(addsuffix _fail,$(TESTS)) rm -rf $(addsuffix .fst,$(TESTS)) - diff --git a/tests/sva/runtest.sh b/tests/sva/runtest.sh index 6a855188f..ee97e2d47 100644 --- a/tests/sva/runtest.sh +++ b/tests/sva/runtest.sh @@ -87,4 +87,3 @@ fi { set +x; } &>/dev/null touch $prefix.ok - diff --git a/tests/svtypes/enum_simple.ys b/tests/svtypes/enum_simple.ys index 36922f5e0..26a39943b 100644 --- a/tests/svtypes/enum_simple.ys +++ b/tests/svtypes/enum_simple.ys @@ -2,4 +2,3 @@ read_verilog -sv enum_simple.sv hierarchy; proc; opt; async2sync sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all - diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv index cd7b7953e..93af0040f 100644 --- a/tests/svtypes/typedef_scopes.sv +++ b/tests/svtypes/typedef_scopes.sv @@ -69,4 +69,3 @@ module other; between_t a = 8'h42; always @(*) assert(a == 8'h42); endmodule - diff --git a/tests/techmap/bmuxmap_pmux.ys b/tests/techmap/bmuxmap_pmux.ys index dd6a80131..89452813e 100644 --- a/tests/techmap/bmuxmap_pmux.ys +++ b/tests/techmap/bmuxmap_pmux.ys @@ -41,5 +41,3 @@ EOT hierarchy -auto-top equiv_opt -assert bmuxmap -pmux - - diff --git a/tests/techmap/bug5495.sh b/tests/techmap/bug5495.sh index d1ade0fb2..f8244efbe 100755 --- a/tests/techmap/bug5495.sh +++ b/tests/techmap/bug5495.sh @@ -9,4 +9,3 @@ if ! timeout 10 ${YOSYS} bug5495.v -p 'hierarchy; techmap; abc -script bug5495.a echo "Yosys failed to complete" exit 1 fi - diff --git a/tests/techmap/clockgate.lib b/tests/techmap/clockgate.lib index 584325108..5ec5b1e4a 100644 --- a/tests/techmap/clockgate.lib +++ b/tests/techmap/clockgate.lib @@ -110,4 +110,4 @@ library(test) { direction : input; } } -} \ No newline at end of file +} diff --git a/tests/techmap/clockgate.v b/tests/techmap/clockgate.v index 3b4936852..8b5637103 100644 --- a/tests/techmap/clockgate.v +++ b/tests/techmap/clockgate.v @@ -41,4 +41,4 @@ module dffe_wide_11( input clk, en, if ( en ) q1 <= d1; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/techmap/clockgate_bad.il b/tests/techmap/clockgate_bad.il index c967b04e6..ec4f7789a 100644 --- a/tests/techmap/clockgate_bad.il +++ b/tests/techmap/clockgate_bad.il @@ -28,4 +28,4 @@ module \bad2 connect \EN \en connect \Q \q1 end -end \ No newline at end of file +end diff --git a/tests/techmap/clockgate_neg.lib b/tests/techmap/clockgate_neg.lib index 5068f9c9a..e964adb5b 100644 --- a/tests/techmap/clockgate_neg.lib +++ b/tests/techmap/clockgate_neg.lib @@ -52,4 +52,4 @@ library(test) { direction : input; } } -} \ No newline at end of file +} diff --git a/tests/techmap/clockgate_pos.lib b/tests/techmap/clockgate_pos.lib index bab9e7cc7..02f5c251b 100644 --- a/tests/techmap/clockgate_pos.lib +++ b/tests/techmap/clockgate_pos.lib @@ -52,4 +52,4 @@ library(test) { direction : input; } } -} \ No newline at end of file +} diff --git a/tests/techmap/clockgate_wide.v b/tests/techmap/clockgate_wide.v index 687fd7104..4e1f600c4 100644 --- a/tests/techmap/clockgate_wide.v +++ b/tests/techmap/clockgate_wide.v @@ -5,4 +5,4 @@ module dffe_wide_11( input clk, input [1:0] en, if ( en[0] ) q1 <= d1; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/techmap/dfflibmap_dffsr_not_next.lib b/tests/techmap/dfflibmap_dffsr_not_next.lib index 579dedb10..f95096bc5 100644 --- a/tests/techmap/dfflibmap_dffsr_not_next.lib +++ b/tests/techmap/dfflibmap_dffsr_not_next.lib @@ -25,4 +25,4 @@ library (test_not_next) { preset : "!RN"; } } -} \ No newline at end of file +} diff --git a/tests/techmap/dfflibmap_formal.ys b/tests/techmap/dfflibmap_formal.ys index e5e61cd62..afa2c4d9d 100644 --- a/tests/techmap/dfflibmap_formal.ys +++ b/tests/techmap/dfflibmap_formal.ys @@ -265,4 +265,4 @@ flatten opt_clean -purge equiv_make top top_unmapped equiv equiv_induct -set-assumes equiv -equiv_status -assert equiv \ No newline at end of file +equiv_status -assert equiv diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v index 762e2938e..4cf706a97 100644 --- a/tests/techmap/mem_simple_4x1_map.v +++ b/tests/techmap/mem_simple_4x1_map.v @@ -149,4 +149,3 @@ module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); end endgenerate endmodule - diff --git a/tests/tools/cmp_tbdata.c b/tests/tools/cmp_tbdata.c index c0b12cd9b..a6bc9dae7 100644 --- a/tests/tools/cmp_tbdata.c +++ b/tests/tools/cmp_tbdata.c @@ -66,4 +66,3 @@ int main(int argc, char **argv) fclose(f2); return 0; } - diff --git a/tests/tools/profiler.pl b/tests/tools/profiler.pl index 456f634bc..99155eec7 100755 --- a/tests/tools/profiler.pl +++ b/tests/tools/profiler.pl @@ -52,4 +52,3 @@ printf "\nFull journal of headers:\n"; for (my $i = 0; $i <= $#lines_text; $i++) { printf "%3d %08.2f %s\n", $lines_depth[$i], $lines_time[$i], $lines_text[$i]; } - diff --git a/tests/tools/txt2tikztiming.py b/tests/tools/txt2tikztiming.py index 9c6cd3a19..e608ece99 100755 --- a/tests/tools/txt2tikztiming.py +++ b/tests/tools/txt2tikztiming.py @@ -103,4 +103,3 @@ for t in sorted(time_val.keys()): if last_time < stop_time: print("%f%s" % ((stop_time - last_time)*args.s, last_value), end='') print('') - diff --git a/tests/tools/vcd2txt.pl b/tests/tools/vcd2txt.pl index 92d3d1652..34758f290 100755 --- a/tests/tools/vcd2txt.pl +++ b/tests/tools/vcd2txt.pl @@ -58,4 +58,3 @@ for my $node (keys $vcd) { } } } - diff --git a/tests/various/attrib05_port_conn.v b/tests/various/attrib05_port_conn.v index e20e66319..75e2ebcb7 100644 --- a/tests/various/attrib05_port_conn.v +++ b/tests/various/attrib05_port_conn.v @@ -18,4 +18,3 @@ module foo(clk, rst, inp, out); bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); endmodule - diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v index 8c9fb2926..a91bcec1d 100644 --- a/tests/various/attrib07_func_call.v +++ b/tests/various/attrib07_func_call.v @@ -18,4 +18,3 @@ module foo(clk, rst, inp_a, inp_b, out); else out <= do_add (* combinational_adder *) (inp_a, inp_b); endmodule - diff --git a/tests/various/bug3515.ys b/tests/various/bug3515.ys index 783a75bb4..d086ad4e0 100644 --- a/tests/various/bug3515.ys +++ b/tests/various/bug3515.ys @@ -28,4 +28,3 @@ hierarchy -top mod_and_or opt extract -map ./bug3515.v select -assert-count 2 t:$and - diff --git a/tests/various/bug4909.ys b/tests/various/bug4909.ys index bf8cfb45b..f0cb33097 100644 --- a/tests/various/bug4909.ys +++ b/tests/various/bug4909.ys @@ -41,4 +41,3 @@ EOF prep splitcells - diff --git a/tests/various/deminout_unused.ys b/tests/various/deminout_unused.ys index 5ed00509d..67f322b47 100644 --- a/tests/various/deminout_unused.ys +++ b/tests/various/deminout_unused.ys @@ -11,4 +11,3 @@ proc tribuf deminout select -assert-count 1 i:x o:x %i - diff --git a/tests/various/dynamic_part_select/latch_1990_gate.v b/tests/various/dynamic_part_select/latch_1990_gate.v index a46183f23..36402a0ad 100644 --- a/tests/various/dynamic_part_select/latch_1990_gate.v +++ b/tests/various/dynamic_part_select/latch_1990_gate.v @@ -3,4 +3,3 @@ module latch_1990_gate (output wire [1:0] x); assign x = 2'b10; endmodule // latch_1990_gate - diff --git a/tests/various/dynamic_part_select/reversed.v b/tests/various/dynamic_part_select/reversed.v index 0268fa6bb..ff5808afb 100644 --- a/tests/various/dynamic_part_select/reversed.v +++ b/tests/various/dynamic_part_select/reversed.v @@ -11,4 +11,3 @@ module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) dout[(WIDTH-ctrl*sel)-:SLICE] <= din; end endmodule - diff --git a/tests/various/reg_wire_error.sv b/tests/various/reg_wire_error.sv index fe5ff3abd..6d90fda32 100644 --- a/tests/various/reg_wire_error.sv +++ b/tests/various/reg_wire_error.sv @@ -71,4 +71,3 @@ begin end endmodule - diff --git a/tests/various/scopeinfo.ys b/tests/various/scopeinfo.ys index f8d4ca31b..a261ddb45 100644 --- a/tests/various/scopeinfo.ys +++ b/tests/various/scopeinfo.ys @@ -107,4 +107,4 @@ select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/r:TYPE=module select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_inst_attr=inst_attr_deep %i select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_module_attr=module_attr_deep %i select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_src %i -select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i \ No newline at end of file +select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys index d778b92cd..69502cf09 100644 --- a/tests/various/sim_const.ys +++ b/tests/various/sim_const.ys @@ -10,4 +10,3 @@ EOT proc sim -clock clk -n 1 -w top select -assert-count 1 a:init=2'b10 top/q %i - diff --git a/tests/various/stat_area_by_width.lib b/tests/various/stat_area_by_width.lib index 1e98aa488..9dff055c9 100644 --- a/tests/various/stat_area_by_width.lib +++ b/tests/various/stat_area_by_width.lib @@ -22,4 +22,4 @@ cell ( "$bmux" ) { double_area_parameterised ( " 3.0, 6.0, 9.0, 12.0, 15.0, 18.0, 21.0, 24.0, 27.0, 30.0, 33.0, 36.0, 39.0, 42.0, 45.0, 48.0, 51.0, 54.0, 57.0, 60.0, 63.0, 66.0, 69.0, 72.0, 75.0, 78.0, 81.0, 84.0, 87.0, 90.0, 93.0, 96.0, 99.0, 102.0, 105.0, 108.0, 111.0, 114.0, 117.0, 120.0, 123.0, 126.0, 129.0, 132.0, 135.0, 138.0, 141.0, 144.0, 147.0, 150.0, 153.0, 156.0, 159.0, 162.0, 165.0, 168.0, 171.0, 174.0, 177.0, 180.0, 183.0, 186.0, 189.0, 192.0, 195.0, 198.0, 201.0, 204.0, 207.0, 210.0, 213.0, 216.0, 219.0, 222.0, 225.0, 228.0, 231.0, 234.0, 237.0, 240.0, 243.0, 246.0, 249.0, 252.0, 255.0, 258.0, 261.0, 264.0, 267.0, 270.0, 273.0, 276.0, 279.0, 282.0, 285.0, 288.0, 291.0, 294.0, 297.0, 300.0, 303.0, 306.0, 309.0, 312.0, 315.0, 318.0, 321.0, 324.0, 327.0, 330.0, 333.0, 336.0, 339.0, 342.0, 345.0, 348.0, 351.0, 354.0, 357.0, 360.0, 363.0, 366.0, 369.0, 372.0, 375.0, 378.0, 381.0, 384.0,", " 6.0, 12.0, 18.0, 24.0, 30.0, 36.0, 42.0, 48.0, 54.0, 60.0, 66.0, 72.0, 78.0, 84.0, 90.0, 96.0, 102.0, 108.0, 114.0, 120.0, 126.0, 132.0, 138.0, 144.0, 150.0, 156.0, 162.0, 168.0, 174.0, 180.0, 186.0, 192.0, 198.0, 204.0, 210.0, 216.0, 222.0, 228.0, 234.0, 240.0, 246.0, 252.0, 258.0, 264.0, 270.0, 276.0, 282.0, 288.0, 294.0, 300.0, 306.0, 312.0, 318.0, 324.0, 330.0, 336.0, 342.0, 348.0, 354.0, 360.0, 366.0, 372.0, 378.0, 384.0, 390.0, 396.0, 402.0, 408.0, 414.0, 420.0, 426.0, 432.0, 438.0, 444.0, 450.0, 456.0, 462.0, 468.0, 474.0, 480.0, 486.0, 492.0, 498.0, 504.0, 510.0, 516.0, 522.0, 528.0, 534.0, 540.0, 546.0, 552.0, 558.0, 564.0, 570.0, 576.0, 582.0, 588.0, 594.0, 600.0, 606.0, 612.0, 618.0, 624.0, 630.0, 636.0, 642.0, 648.0, 654.0, 660.0, 666.0, 672.0, 678.0, 684.0, 690.0, 696.0, 702.0, 708.0, 714.0, 720.0, 726.0, 732.0, 738.0, 744.0, 750.0, 756.0, 762.0, 768.0,", " 9.0, 18.0, 27.0, 36.0, 45.0, 54.0, 63.0, 72.0, 81.0, 90.0, 99.0, 108.0, 117.0, 126.0, 135.0, 144.0, 153.0, 162.0, 171.0, 180.0, 189.0, 198.0, 207.0, 216.0, 225.0, 234.0, 243.0, 252.0, 261.0, 270.0, 279.0, 288.0, 297.0, 306.0, 315.0, 324.0, 333.0, 342.0, 351.0, 360.0, 369.0, 378.0, 387.0, 396.0, 405.0, 414.0, 423.0, 432.0, 441.0, 450.0, 459.0, 468.0, 477.0, 486.0, 495.0, 504.0, 513.0, 522.0, 531.0, 540.0, 549.0, 558.0, 567.0, 576.0, 585.0, 594.0, 603.0, 612.0, 621.0, 630.0, 639.0, 648.0, 657.0, 666.0, 675.0, 684.0, 693.0, 702.0, 711.0, 720.0, 729.0, 738.0, 747.0, 756.0, 765.0, 774.0, 783.0, 792.0, 801.0, 810.0, 819.0, 828.0, 837.0, 846.0, 855.0, 864.0, 873.0, 882.0, 891.0, 900.0, 909.0, 918.0, 927.0, 936.0, 945.0, 954.0, 963.0, 972.0, 981.0, 990.0, 999.0, 1008.0, 1017.0, 1026.0, 1035.0, 1044.0, 1053.0, 1062.0, 1071.0, 1080.0, 1089.0, 1098.0, 1107.0, 1116.0, 1125.0, 1134.0, 1143.0, 1152.0,", " 12.0, 24.0, 36.0, 48.0, 60.0, 72.0, 84.0, 96.0, 108.0, 120.0, 132.0, 144.0, 156.0, 168.0, 180.0, 192.0, 204.0, 216.0, 228.0, 240.0, 252.0, 264.0, 276.0, 288.0, 300.0, 312.0, 324.0, 336.0, 348.0, 360.0, 372.0, 384.0, 396.0, 408.0, 420.0, 432.0, 444.0, 456.0, 468.0, 480.0, 492.0, 504.0, 516.0, 528.0, 540.0, 552.0, 564.0, 576.0, 588.0, 600.0, 612.0, 624.0, 636.0, 648.0, 660.0, 672.0, 684.0, 696.0, 708.0, 720.0, 732.0, 744.0, 756.0, 768.0, 780.0, 792.0, 804.0, 816.0, 828.0, 840.0, 852.0, 864.0, 876.0, 888.0, 900.0, 912.0, 924.0, 936.0, 948.0, 960.0, 972.0, 984.0, 996.0, 1008.0, 1020.0, 1032.0, 1044.0, 1056.0, 1068.0, 1080.0, 1092.0, 1104.0, 1116.0, 1128.0, 1140.0, 1152.0, 1164.0, 1176.0, 1188.0, 1200.0, 1212.0, 1224.0, 1236.0, 1248.0, 1260.0, 1272.0, 1284.0, 1296.0, 1308.0, 1320.0, 1332.0, 1344.0, 1356.0, 1368.0, 1380.0, 1392.0, 1404.0, 1416.0, 1428.0, 1440.0, 1452.0, 1464.0, 1476.0, 1488.0, 1500.0, 1512.0, 1524.0, 1536.0,", " 15.0, 30.0, 45.0, 60.0, 75.0, 90.0, 105.0, 120.0, 135.0, 150.0, 165.0, 180.0, 195.0, 210.0, 225.0, 240.0, 255.0, 270.0, 285.0, 300.0, 315.0, 330.0, 345.0, 360.0, 375.0, 390.0, 405.0, 420.0, 435.0, 450.0, 465.0, 480.0, 495.0, 510.0, 525.0, 540.0, 555.0, 570.0, 585.0, 600.0, 615.0, 630.0, 645.0, 660.0, 675.0, 690.0, 705.0, 720.0, 735.0, 750.0, 765.0, 780.0, 795.0, 810.0, 825.0, 840.0, 855.0, 870.0, 885.0, 900.0, 915.0, 930.0, 945.0, 960.0, 975.0, 990.0, 1005.0, 1020.0, 1035.0, 1050.0, 1065.0, 1080.0, 1095.0, 1110.0, 1125.0, 1140.0, 1155.0, 1170.0, 1185.0, 1200.0, 1215.0, 1230.0, 1245.0, 1260.0, 1275.0, 1290.0, 1305.0, 1320.0, 1335.0, 1350.0, 1365.0, 1380.0, 1395.0, 1410.0, 1425.0, 1440.0, 1455.0, 1470.0, 1485.0, 1500.0, 1515.0, 1530.0, 1545.0, 1560.0, 1575.0, 1590.0, 1605.0, 1620.0, 1635.0, 1650.0, 1665.0, 1680.0, 1695.0, 1710.0, 1725.0, 1740.0, 1755.0, 1770.0, 1785.0, 1800.0, 1815.0, 1830.0, 1845.0, 1860.0, 1875.0, 1890.0, 1905.0, 1920.0,", " 18.0, 36.0, 54.0, 72.0, 90.0, 108.0, 126.0, 144.0, 162.0, 180.0, 198.0, 216.0, 234.0, 252.0, 270.0, 288.0, 306.0, 324.0, 342.0, 360.0, 378.0, 396.0, 414.0, 432.0, 450.0, 468.0, 486.0, 504.0, 522.0, 540.0, 558.0, 576.0, 594.0, 612.0, 630.0, 648.0, 666.0, 684.0, 702.0, 720.0, 738.0, 756.0, 774.0, 792.0, 810.0, 828.0, 846.0, 864.0, 882.0, 900.0, 918.0, 936.0, 954.0, 972.0, 990.0, 1008.0, 1026.0, 1044.0, 1062.0, 1080.0, 1098.0, 1116.0, 1134.0, 1152.0, 1170.0, 1188.0, 1206.0, 1224.0, 1242.0, 1260.0, 1278.0, 1296.0, 1314.0, 1332.0, 1350.0, 1368.0, 1386.0, 1404.0, 1422.0, 1440.0, 1458.0, 1476.0, 1494.0, 1512.0, 1530.0, 1548.0, 1566.0, 1584.0, 1602.0, 1620.0, 1638.0, 1656.0, 1674.0, 1692.0, 1710.0, 1728.0, 1746.0, 1764.0, 1782.0, 1800.0, 1818.0, 1836.0, 1854.0, 1872.0, 1890.0, 1908.0, 1926.0, 1944.0, 1962.0, 1980.0, 1998.0, 2016.0, 2034.0, 2052.0, 2070.0, 2088.0, 2106.0, 2124.0, 2142.0, 2160.0, 2178.0, 2196.0, 2214.0, 2232.0, 2250.0, 2268.0, 2286.0, 2304.0,", " 21.0, 42.0, 63.0, 84.0, 105.0, 126.0, 147.0, 168.0, 189.0, 210.0, 231.0, 252.0, 273.0, 294.0, 315.0, 336.0, 357.0, 378.0, 399.0, 420.0, 441.0, 462.0, 483.0, 504.0, 525.0, 546.0, 567.0, 588.0, 609.0, 630.0, 651.0, 672.0, 693.0, 714.0, 735.0, 756.0, 777.0, 798.0, 819.0, 840.0, 861.0, 882.0, 903.0, 924.0, 945.0, 966.0, 987.0, 1008.0, 1029.0, 1050.0, 1071.0, 1092.0, 1113.0, 1134.0, 1155.0, 1176.0, 1197.0, 1218.0, 1239.0, 1260.0, 1281.0, 1302.0, 1323.0, 1344.0, 1365.0, 1386.0, 1407.0, 1428.0, 1449.0, 1470.0, 1491.0, 1512.0, 1533.0, 1554.0, 1575.0, 1596.0, 1617.0, 1638.0, 1659.0, 1680.0, 1701.0, 1722.0, 1743.0, 1764.0, 1785.0, 1806.0, 1827.0, 1848.0, 1869.0, 1890.0, 1911.0, 1932.0, 1953.0, 1974.0, 1995.0, 2016.0, 2037.0, 2058.0, 2079.0, 2100.0, 2121.0, 2142.0, 2163.0, 2184.0, 2205.0, 2226.0, 2247.0, 2268.0, 2289.0, 2310.0, 2331.0, 2352.0, 2373.0, 2394.0, 2415.0, 2436.0, 2457.0, 2478.0, 2499.0, 2520.0, 2541.0, 2562.0, 2583.0, 2604.0, 2625.0, 2646.0, 2667.0, 2688.0,", " 24.0, 48.0, 72.0, 96.0, 120.0, 144.0, 168.0, 192.0, 216.0, 240.0, 264.0, 288.0, 312.0, 336.0, 360.0, 384.0, 408.0, 432.0, 456.0, 480.0, 504.0, 528.0, 552.0, 576.0, 600.0, 624.0, 648.0, 672.0, 696.0, 720.0, 744.0, 768.0, 792.0, 816.0, 840.0, 864.0, 888.0, 912.0, 936.0, 960.0, 984.0, 1008.0, 1032.0, 1056.0, 1080.0, 1104.0, 1128.0, 1152.0, 1176.0, 1200.0, 1224.0, 1248.0, 1272.0, 1296.0, 1320.0, 1344.0, 1368.0, 1392.0, 1416.0, 1440.0, 1464.0, 1488.0, 1512.0, 1536.0, 1560.0, 1584.0, 1608.0, 1632.0, 1656.0, 1680.0, 1704.0, 1728.0, 1752.0, 1776.0, 1800.0, 1824.0, 1848.0, 1872.0, 1896.0, 1920.0, 1944.0, 1968.0, 1992.0, 2016.0, 2040.0, 2064.0, 2088.0, 2112.0, 2136.0, 2160.0, 2184.0, 2208.0, 2232.0, 2256.0, 2280.0, 2304.0, 2328.0, 2352.0, 2376.0, 2400.0, 2424.0, 2448.0, 2472.0, 2496.0, 2520.0, 2544.0, 2568.0, 2592.0, 2616.0, 2640.0, 2664.0, 2688.0, 2712.0, 2736.0, 2760.0, 2784.0, 2808.0, 2832.0, 2856.0, 2880.0, 2904.0, 2928.0, 2952.0, 2976.0, 3000.0, 3024.0, 3048.0, 3072.0,", " 27.0, 54.0, 81.0, 108.0, 135.0, 162.0, 189.0, 216.0, 243.0, 270.0, 297.0, 324.0, 351.0, 378.0, 405.0, 432.0, 459.0, 486.0, 513.0, 540.0, 567.0, 594.0, 621.0, 648.0, 675.0, 702.0, 729.0, 756.0, 783.0, 810.0, 837.0, 864.0, 891.0, 918.0, 945.0, 972.0, 999.0, 1026.0, 1053.0, 1080.0, 1107.0, 1134.0, 1161.0, 1188.0, 1215.0, 1242.0, 1269.0, 1296.0, 1323.0, 1350.0, 1377.0, 1404.0, 1431.0, 1458.0, 1485.0, 1512.0, 1539.0, 1566.0, 1593.0, 1620.0, 1647.0, 1674.0, 1701.0, 1728.0, 1755.0, 1782.0, 1809.0, 1836.0, 1863.0, 1890.0, 1917.0, 1944.0, 1971.0, 1998.0, 2025.0, 2052.0, 2079.0, 2106.0, 2133.0, 2160.0, 2187.0, 2214.0, 2241.0, 2268.0, 2295.0, 2322.0, 2349.0, 2376.0, 2403.0, 2430.0, 2457.0, 2484.0, 2511.0, 2538.0, 2565.0, 2592.0, 2619.0, 2646.0, 2673.0, 2700.0, 2727.0, 2754.0, 2781.0, 2808.0, 2835.0, 2862.0, 2889.0, 2916.0, 2943.0, 2970.0, 2997.0, 3024.0, 3051.0, 3078.0, 3105.0, 3132.0, 3159.0, 3186.0, 3213.0, 3240.0, 3267.0, 3294.0, 3321.0, 3348.0, 3375.0, 3402.0, 3429.0, 3456.0,", " 30.0, 60.0, 90.0, 120.0, 150.0, 180.0, 210.0, 240.0, 270.0, 300.0, 330.0, 360.0, 390.0, 420.0, 450.0, 480.0, 510.0, 540.0, 570.0, 600.0, 630.0, 660.0, 690.0, 720.0, 750.0, 780.0, 810.0, 840.0, 870.0, 900.0, 930.0, 960.0, 990.0, 1020.0, 1050.0, 1080.0, 1110.0, 1140.0, 1170.0, 1200.0, 1230.0, 1260.0, 1290.0, 1320.0, 1350.0, 1380.0, 1410.0, 1440.0, 1470.0, 1500.0, 1530.0, 1560.0, 1590.0, 1620.0, 1650.0, 1680.0, 1710.0, 1740.0, 1770.0, 1800.0, 1830.0, 1860.0, 1890.0, 1920.0, 1950.0, 1980.0, 2010.0, 2040.0, 2070.0, 2100.0, 2130.0, 2160.0, 2190.0, 2220.0, 2250.0, 2280.0, 2310.0, 2340.0, 2370.0, 2400.0, 2430.0, 2460.0, 2490.0, 2520.0, 2550.0, 2580.0, 2610.0, 2640.0, 2670.0, 2700.0, 2730.0, 2760.0, 2790.0, 2820.0, 2850.0, 2880.0, 2910.0, 2940.0, 2970.0, 3000.0, 3030.0, 3060.0, 3090.0, 3120.0, 3150.0, 3180.0, 3210.0, 3240.0, 3270.0, 3300.0, 3330.0, 3360.0, 3390.0, 3420.0, 3450.0, 3480.0, 3510.0, 3540.0, 3570.0, 3600.0, 3630.0, 3660.0, 3690.0, 3720.0, 3750.0, 3780.0, 3810.0, 3840.0,", " 33.0, 66.0, 99.0, 132.0, 165.0, 198.0, 231.0, 264.0, 297.0, 330.0, 363.0, 396.0, 429.0, 462.0, 495.0, 528.0, 561.0, 594.0, 627.0, 660.0, 693.0, 726.0, 759.0, 792.0, 825.0, 858.0, 891.0, 924.0, 957.0, 990.0, 1023.0, 1056.0, 1089.0, 1122.0, 1155.0, 1188.0, 1221.0, 1254.0, 1287.0, 1320.0, 1353.0, 1386.0, 1419.0, 1452.0, 1485.0, 1518.0, 1551.0, 1584.0, 1617.0, 1650.0, 1683.0, 1716.0, 1749.0, 1782.0, 1815.0, 1848.0, 1881.0, 1914.0, 1947.0, 1980.0, 2013.0, 2046.0, 2079.0, 2112.0, 2145.0, 2178.0, 2211.0, 2244.0, 2277.0, 2310.0, 2343.0, 2376.0, 2409.0, 2442.0, 2475.0, 2508.0, 2541.0, 2574.0, 2607.0, 2640.0, 2673.0, 2706.0, 2739.0, 2772.0, 2805.0, 2838.0, 2871.0, 2904.0, 2937.0, 2970.0, 3003.0, 3036.0, 3069.0, 3102.0, 3135.0, 3168.0, 3201.0, 3234.0, 3267.0, 3300.0, 3333.0, 3366.0, 3399.0, 3432.0, 3465.0, 3498.0, 3531.0, 3564.0, 3597.0, 3630.0, 3663.0, 3696.0, 3729.0, 3762.0, 3795.0, 3828.0, 3861.0, 3894.0, 3927.0, 3960.0, 3993.0, 4026.0, 4059.0, 4092.0, 4125.0, 4158.0, 4191.0, 4224.0,", " 36.0, 72.0, 108.0, 144.0, 180.0, 216.0, 252.0, 288.0, 324.0, 360.0, 396.0, 432.0, 468.0, 504.0, 540.0, 576.0, 612.0, 648.0, 684.0, 720.0, 756.0, 792.0, 828.0, 864.0, 900.0, 936.0, 972.0, 1008.0, 1044.0, 1080.0, 1116.0, 1152.0, 1188.0, 1224.0, 1260.0, 1296.0, 1332.0, 1368.0, 1404.0, 1440.0, 1476.0, 1512.0, 1548.0, 1584.0, 1620.0, 1656.0, 1692.0, 1728.0, 1764.0, 1800.0, 1836.0, 1872.0, 1908.0, 1944.0, 1980.0, 2016.0, 2052.0, 2088.0, 2124.0, 2160.0, 2196.0, 2232.0, 2268.0, 2304.0, 2340.0, 2376.0, 2412.0, 2448.0, 2484.0, 2520.0, 2556.0, 2592.0, 2628.0, 2664.0, 2700.0, 2736.0, 2772.0, 2808.0, 2844.0, 2880.0, 2916.0, 2952.0, 2988.0, 3024.0, 3060.0, 3096.0, 3132.0, 3168.0, 3204.0, 3240.0, 3276.0, 3312.0, 3348.0, 3384.0, 3420.0, 3456.0, 3492.0, 3528.0, 3564.0, 3600.0, 3636.0, 3672.0, 3708.0, 3744.0, 3780.0, 3816.0, 3852.0, 3888.0, 3924.0, 3960.0, 3996.0, 4032.0, 4068.0, 4104.0, 4140.0, 4176.0, 4212.0, 4248.0, 4284.0, 4320.0, 4356.0, 4392.0, 4428.0, 4464.0, 4500.0, 4536.0, 4572.0, 4608.0,", " 39.0, 78.0, 117.0, 156.0, 195.0, 234.0, 273.0, 312.0, 351.0, 390.0, 429.0, 468.0, 507.0, 546.0, 585.0, 624.0, 663.0, 702.0, 741.0, 780.0, 819.0, 858.0, 897.0, 936.0, 975.0, 1014.0, 1053.0, 1092.0, 1131.0, 1170.0, 1209.0, 1248.0, 1287.0, 1326.0, 1365.0, 1404.0, 1443.0, 1482.0, 1521.0, 1560.0, 1599.0, 1638.0, 1677.0, 1716.0, 1755.0, 1794.0, 1833.0, 1872.0, 1911.0, 1950.0, 1989.0, 2028.0, 2067.0, 2106.0, 2145.0, 2184.0, 2223.0, 2262.0, 2301.0, 2340.0, 2379.0, 2418.0, 2457.0, 2496.0, 2535.0, 2574.0, 2613.0, 2652.0, 2691.0, 2730.0, 2769.0, 2808.0, 2847.0, 2886.0, 2925.0, 2964.0, 3003.0, 3042.0, 3081.0, 3120.0, 3159.0, 3198.0, 3237.0, 3276.0, 3315.0, 3354.0, 3393.0, 3432.0, 3471.0, 3510.0, 3549.0, 3588.0, 3627.0, 3666.0, 3705.0, 3744.0, 3783.0, 3822.0, 3861.0, 3900.0, 3939.0, 3978.0, 4017.0, 4056.0, 4095.0, 4134.0, 4173.0, 4212.0, 4251.0, 4290.0, 4329.0, 4368.0, 4407.0, 4446.0, 4485.0, 4524.0, 4563.0, 4602.0, 4641.0, 4680.0, 4719.0, 4758.0, 4797.0, 4836.0, 4875.0, 4914.0, 4953.0, 4992.0,", ) ; } -} \ No newline at end of file +} diff --git a/tests/various/stat_hierarchy.ys b/tests/various/stat_hierarchy.ys index f41165629..93cd5e8e1 100644 --- a/tests/various/stat_hierarchy.ys +++ b/tests/various/stat_hierarchy.ys @@ -58,5 +58,3 @@ logger -expect log "2 94.349 - - sg13g2_dfrbp_1" 2 logger -expect log "2 94.349 2 - submodules" 2 logger -expect-no-warnings stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top -hierarchy - - diff --git a/tests/various/stat_high_level.ys b/tests/various/stat_high_level.ys index 03e5e957e..9f94bf764 100644 --- a/tests/various/stat_high_level.ys +++ b/tests/various/stat_high_level.ys @@ -88,5 +88,3 @@ logger -expect log "2 51 - - \$reduce_xor" 2 logger -expect log "8 66 2 5 cells" 2 logger -expect-no-warnings stat -liberty ./stat_area_by_width.lib -top \top -hierarchy - - diff --git a/tests/various/stat_high_level2.ys b/tests/various/stat_high_level2.ys index 63d59da95..3493c1239 100644 --- a/tests/various/stat_high_level2.ys +++ b/tests/various/stat_high_level2.ys @@ -87,5 +87,3 @@ logger -expect log "3 37.5 3 37.5 cells" 1 logger -expect log "8 80 2 5 cells" 2 logger -expect-no-warnings stat -liberty ./stat_area_by_width.lib -top \top -hierarchy - - diff --git a/tests/verific/case.sv b/tests/verific/case.sv index ed8529b91..a03a9d1f8 100644 --- a/tests/verific/case.sv +++ b/tests/verific/case.sv @@ -25,4 +25,3 @@ module top ( endcase end endmodule - diff --git a/tests/verific/rom_case.ys b/tests/verific/rom_case.ys index 253cc0766..49719d2db 100644 --- a/tests/verific/rom_case.ys +++ b/tests/verific/rom_case.ys @@ -75,4 +75,4 @@ dump memory_libmap -lib ../memlib/memlib_block_sdp.txt memory_map stat -select -assert-count 1 t:RAM_BLOCK_SDP \ No newline at end of file +select -assert-count 1 t:RAM_BLOCK_SDP diff --git a/tests/verilog/for_loop_signed_index.ys b/tests/verilog/for_loop_signed_index.ys index a2bde3395..87e6b14cb 100644 --- a/tests/verilog/for_loop_signed_index.ys +++ b/tests/verilog/for_loop_signed_index.ys @@ -53,4 +53,4 @@ EOT hierarchy -top unsigned_index proc -sat -set a 1 -prove y 0 -verify \ No newline at end of file +sat -set a 1 -prove y 0 -verify diff --git a/tests/verilog/issue4402.ys b/tests/verilog/issue4402.ys index 4fcf816a3..f5ddca7d2 100644 --- a/tests/verilog/issue4402.ys +++ b/tests/verilog/issue4402.ys @@ -29,4 +29,4 @@ proc write_verilog temp/issue4402_syn.v # Port declaration must include the signed keyword. -! grep -q "input signed wire0" temp/issue4402_syn.v \ No newline at end of file +! grep -q "input signed wire0" temp/issue4402_syn.v diff --git a/tests/verilog/issue5745.ys b/tests/verilog/issue5745.ys index 938ead63a..1e16b8373 100644 --- a/tests/verilog/issue5745.ys +++ b/tests/verilog/issue5745.ys @@ -15,4 +15,4 @@ endmodule EOT chparam -set p2 11 hierarchy -top mod -sat -prove k 1 -verify \ No newline at end of file +sat -prove k 1 -verify diff --git a/tests/verilog/unreachable_case_sign.ys b/tests/verilog/unreachable_case_sign.ys index 569c8a313..48f7993f7 100644 --- a/tests/verilog/unreachable_case_sign.ys +++ b/tests/verilog/unreachable_case_sign.ys @@ -32,4 +32,3 @@ EOT prep -top top async2sync sim -n 3 -clock clk - diff --git a/tests/vloghtb/run-test.sh b/tests/vloghtb/run-test.sh index 29f7c2680..11b93f890 100755 --- a/tests/vloghtb/run-test.sh +++ b/tests/vloghtb/run-test.sh @@ -12,4 +12,3 @@ rm -rf log_test_* ${MAKE:-make} EXIT_ON_ERROR=1 YOSYS_BIN=$PWD/../../yosys YOSYS_SCRIPT="proc;;" check_yosys ${MAKE:-make} -f test_makefile MODE=share ${MAKE:-make} -f test_makefile MODE=mapopt - diff --git a/tests/vloghtb/test_makefile b/tests/vloghtb/test_makefile index 174dbbc2c..0d87d5045 100644 --- a/tests/vloghtb/test_makefile +++ b/tests/vloghtb/test_makefile @@ -6,4 +6,3 @@ run: $(addprefix log_test_$(MODE)/,$(addsuffix .txt,$(TESTS))) log_test_$(MODE)/%.txt: rtl/%.v @bash test_$(MODE).sh $< -