mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-01 21:18:55 +00:00
Code Activity

End of file fix

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-23 07:23:41 +02:00
parent 3ac58b3ac1
commit 48a3dcc02a
304 changed files with 64 additions and 321 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/techmap/clockgate_wide.v
View file

@ -5,4 +5,4 @@ module dffe_wide_11( input clk, input [1:0] en,
if ( en[0] )
q1 <= d1;
end
endmodule
endmodule