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End of file fix
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304 changed files with 64 additions and 321 deletions
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@ -2,4 +2,3 @@
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read_verilog -sv enum_simple.sv
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hierarchy; proc; opt; async2sync
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sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all
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@ -69,4 +69,3 @@ module other;
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between_t a = 8'h42;
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always @(*) assert(a == 8'h42);
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endmodule
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