End of file fix

tests/arch/analogdevices/asym_ram_sdp.ys

@@ -47,4 +47,3 @@ chparam -set SIZEA 768
 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
 synth_analogdevices -top asym_ram_sdp_read_wider -noiopad
 select -assert-count 2 t:RBRAM2
-

tests/arch/analogdevices/dffs.ys

@@ -38,4 +38,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:FFRE
 select -assert-none t:FFRE %% t:* %D
-

tests/arch/analogdevices/dsp_abc9.ys

@@ -39,4 +39,3 @@ techmap -autoproc -wb -map +/analogdevices/cells_sim.v
 opt -full -fine
 select -assert-count 0 t:* t:$assert %d
 sat -verify -prove-asserts
-

tests/arch/common/blockram.v

@@ -325,4 +325,3 @@ module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
     );
 
 endmodule // double_sync_ram_tdp
-

tests/arch/common/memory_attributes/attributes_test.v

@@ -85,4 +85,3 @@ module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
 
    assign data_out = data_out_r;
 endmodule // distributed_ram
-

tests/arch/ecp5/add_sub.ys

@@ -9,4 +9,3 @@ select -assert-max 26 t:LUT4
 select -assert-count 10 t:PFUMX
 select -assert-count 6 t:L6MUX21
 select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D
-

tests/arch/ecp5/dffs.ys

@@ -16,4 +16,4 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
-select -assert-none t:TRELLIS_FF %% t:* %D
+select -assert-none t:TRELLIS_FF %% t:* %D

tests/arch/efinix/add_sub.ys

@@ -7,4 +7,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:EFX_ADD
 select -assert-count 4  t:EFX_LUT4
 select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
-

tests/arch/gowin/add_sub.ys

@@ -10,4 +10,3 @@ select -assert-count 8 t:IBUF
 select -assert-count 1 t:GND
 select -assert-count 1 t:VCC
 select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D
-

tests/arch/gowin/compare.ys

@@ -5,5 +5,3 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 5 t:ALU
-
-

tests/arch/gowin/tribuf.ys

@@ -11,4 +11,4 @@ cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:TBUF
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:IBUF
-select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
+select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D

tests/arch/ice40/add_sub.ys

@@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 10 t:SB_LUT4
 select -assert-count 6 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
-

tests/arch/ice40/dffs.ys

@@ -16,4 +16,4 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFFE %% t:* %D
+select -assert-none t:SB_DFFE %% t:* %D

tests/arch/intel_alm/add_sub.ys

@@ -6,4 +6,3 @@ cd top # Constrain all select calls below inside the top module
 stat
 select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
-

tests/arch/intel_alm/adffs.ys

@@ -45,4 +45,3 @@ select -assert-count 1 t:MISTRAL_FF
 select -assert-count 2 t:MISTRAL_NOT
 
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
-

tests/arch/intel_alm/blockram.ys

@@ -5,4 +5,3 @@ cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D
-

tests/arch/intel_alm/counter.ys

@@ -10,4 +10,3 @@ select -assert-count 2 t:MISTRAL_NOT
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/dffs.ys

@@ -18,4 +18,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/fsm.ys

@@ -19,4 +19,3 @@ select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
 select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
 select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
 select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
-

tests/arch/intel_alm/logic.ys

@@ -9,4 +9,3 @@ select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 6 t:MISTRAL_ALUT2
 select -assert-count 2 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
-

tests/arch/intel_alm/lutram.ys

@@ -37,4 +37,3 @@ select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
-

tests/arch/intel_alm/mul.ys

@@ -32,4 +32,3 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:MISTRAL_MUL27X27
 select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
-

tests/arch/intel_alm/mux.ys

@@ -42,4 +42,3 @@ select -assert-max 1 t:MISTRAL_ALUT3
 select -assert-max 2 t:MISTRAL_ALUT5
 select -assert-max 5 t:MISTRAL_ALUT6
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
-

tests/arch/intel_alm/shifter.ys

@@ -7,4 +7,3 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_FF %% t:* %D
-

tests/arch/intel_alm/tribuf.ys

@@ -10,4 +10,3 @@ cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-

tests/arch/microchip/.gitignore

@@ -1,2 +1 @@
 *.vm
-

tests/arch/microchip/dff.ys

@@ -73,4 +73,4 @@ synth_microchip -top dffs -family polarfire -noiopad
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CLKBUF
 select -assert-count 1 t:CFG1
-select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
+select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D

tests/arch/microchip/dff_opt.ys

@@ -39,4 +39,4 @@ synth_microchip -top dff_opt -family polarfire -noiopad
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CFG4
 select -assert-count 1 t:CLKBUF
-select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D
+select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D

tests/arch/microchip/ram_SDP.ys

@@ -47,4 +47,4 @@ hierarchy -top sync_ram_sdp
 chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
 synth_microchip -top sync_ram_sdp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/ram_TDP.ys

@@ -61,4 +61,4 @@ chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
 synth_microchip -top sync_ram_tdp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-count 2 t:CFG1
-select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
+select -assert-none t:RAM1K20 t:CFG1 %% t:* %D

tests/arch/microchip/reduce.ys

@@ -25,4 +25,3 @@ EOT
 synth_microchip -top reduce -family polarfire -noiopad
 select -assert-count 1 t:XOR8
 select -assert-none t:XOR8 %% t:* %D
-

tests/arch/microchip/simple_ram.ys

@@ -19,4 +19,4 @@ hierarchy -top sync_ram_sp
 chparam -set DATA_WIDTH 20 -set ADDRESS_WIDTH 10
 synth_microchip -top sync_ram_sp -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
-select -assert-none t:RAM1K20 %% t:* %D
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/widemux.ys

@@ -38,4 +38,4 @@ equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 3 t:CFG3
-select -assert-none t:CFG3 %% t:* %D
+select -assert-none t:CFG3 %% t:* %D

tests/arch/xilinx/asym_ram_sdp.ys

@@ -47,4 +47,3 @@ chparam -set SIZEA 768
 chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
 synth_xilinx -top asym_ram_sdp_read_wider -noiopad
 select -assert-count 1 t:RAMB18E1
-

tests/arch/xilinx/asym_ram_sdp_read_wider.v

@@ -69,4 +69,4 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
 		end
 	end
 	assign doB = readB;
-endmodule
+endmodule

tests/arch/xilinx/asym_ram_sdp_write_wider.v

@@ -68,4 +68,4 @@ module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
 			end
 		end
 	end
-endmodule
+endmodule

tests/arch/xilinx/dffs.ys

@@ -42,4 +42,3 @@ cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
 select -assert-none t:BUFG t:FDRE %% t:* %D
-

tests/arch/xilinx/dsp_cascade.ys

@@ -87,4 +87,3 @@ select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)
 select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i
-