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End of file fix

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:23:41 +02:00
parent 3ac58b3ac1
commit 48a3dcc02a
304 changed files with 64 additions and 321 deletions
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1
techlibs/gowin/adc.v
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@ -257,4 +257,3 @@ module ADCA (
parameter CSR_OFFSET = -12'd1180; // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
endmodule

1
techlibs/gowin/arith_map.v
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@ -64,4 +64,3 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
end endgenerate
assign X = AA ^ BB ^ {Y_WIDTH{BI}};
endmodule

2
techlibs/gowin/cells_sim.v
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@ -2151,5 +2151,3 @@ module EMCU (
);
endmodule

1
techlibs/gowin/cells_xtra.py
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@ -103,4 +103,3 @@ if __name__ == '__main__':
with open(f'adc.v', 'r') as fin:
for l in fin:
fout.write(l);

1
techlibs/gowin/cells_xtra_gw5a.v
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@ -2787,4 +2787,3 @@ module ADCA (
parameter CSR_OFFSET = -12'd1180; // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
endmodule