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Added SAT generator and simple sat_solve command

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Clifford Wolf 2013-06-07 13:59:13 +02:00
parent 3371563f2f
commit 46fbe9d262
7 changed files with 400 additions and 3 deletions
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passes/sat/example.ys Normal file
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read_verilog example.v
techmap; opt
sat_solve -show a -set y 1'b1