mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 22:23:23 +00:00
Code Activity

write_verilog: write module ports in order

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-14 14:34:50 +02:00
parent 6900818105
commit 45452c18b2
1 changed files with 3 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/verilog/verilog_backend.cc
View file

@ -2356,7 +2356,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
}
for (auto w : module->wires())
std::vector<Wire*> wires = module->wires();
std::sort(wires.begin(), wires.end(), [](Wire *a, Wire *b) { return a->port_id < b->port_id; });
for (auto w : wires)
dump_wire(f, indent + " ", w);
for (auto &mem : Mem::get_all_memories(module))