From 45452c18b2d9fcaa8d7fa0d63ab7b5623be1b81c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 14 May 2025 14:34:50 +0200 Subject: [PATCH] write_verilog: write module ports in order --- backends/verilog/verilog_backend.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 19be9914e..b4c267872 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2356,7 +2356,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) f << indent + " " << "reg " << id(initial_id) << " = 0;\n"; } - for (auto w : module->wires()) + std::vector wires = module->wires(); + std::sort(wires.begin(), wires.end(), [](Wire *a, Wire *b) { return a->port_id < b->port_id; }); + for (auto w : wires) dump_wire(f, indent + " ", w); for (auto &mem : Mem::get_all_memories(module))