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add tests

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N. Engelhardt 2025-10-14 15:48:16 +02:00
parent 1f11b2c529
commit 4513783a02
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tests/verific/import_warning_operator.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port (
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(3 downto 0)
);
end top;
architecture Behavioral of top is
begin
y <= a nor b;
end Behavioral;