add tests

tests/verific/ext_ramnet_err.sv

@@ -0,0 +1,13 @@
+module sub_rom (input clk, input [3:0] addr, output reg [7:0] data);
+    reg [7:0] mem [0:15];
+
+    always @(posedge clk)
+        data <= mem[addr];
+endmodule
+
+module top (input clk, input [3:0] addr, output [7:0] data, input [3:0] f_addr, input [7:0] f_data);
+    sub_rom u_sub_rom (clk, addr, data);
+
+    always @(posedge clk) 
+        assume(u_sub_rom.mem[f_addr] == f_data);
+endmodule

tests/verific/ext_ramnet_err.ys

@@ -0,0 +1,5 @@
+logger -expect error "ext_ramnet_err.sv:\d+.\d+-\d+.\d+: Memory net '\S+' missing, possibly no driver, use verific -flatten." 1
+verific -sv ext_ramnet_err.sv
+verific -import top
+logger -check-expected
+design -reset

tests/verific/import_warning_operator.vhd

@@ -0,0 +1,15 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity top is
+    Port (
+        a   : in  STD_LOGIC_VECTOR(3 downto 0);
+        b   : in  STD_LOGIC_VECTOR(3 downto 0);
+        y   : out STD_LOGIC_VECTOR(3 downto 0)
+    );
+end top;
+
+architecture Behavioral of top is
+begin
+    y <= a nor b;
+end Behavioral;

tests/verific/import_warning_operator.ys

@@ -0,0 +1,5 @@
+logger -expect warning "import_warning_operator.vhd:\d+.\d+-\d+.\d+: Unsupported Verific operator: nor_4 (fallback to gate level implementation provided by verific)" 1
+verific -vhdl import_warning_operator.vhd
+verific -import top
+logger -check-expected
+design -reset