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refactor
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parent
741e088e3a
commit
436d698525
3 changed files with 58 additions and 52 deletions
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@ -90,6 +90,7 @@ namespace RTLIL
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PD_INOUT = 3
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};
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struct Detail;
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struct Const;
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struct AttrObject;
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struct NamedObject;
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@ -1494,6 +1495,8 @@ struct RTLIL::Design
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#endif
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};
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using CellPort = std::pair<Cell*, IdString>;
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struct RTLIL::Module : public RTLIL::NamedObject
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{
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Hasher::hash_t hashidx_;
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@ -1547,7 +1550,7 @@ public:
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std::vector<RTLIL::IdString> ports;
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void fixup_ports();
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pool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;
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pool<CellPort> bufNormQueue;
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void bufNormalize();
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template<typename T> void rewrite_sigspecs(T &functor);
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@ -1870,6 +1873,7 @@ protected:
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friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
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RTLIL::Cell *driverCell_ = nullptr;
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RTLIL::IdString driverPort_;
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friend struct Detail;
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public:
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// do not simply copy wires
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@ -1883,6 +1887,7 @@ public:
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bool driverKnown() const { return driverCell_ != nullptr; }
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RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };
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RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };
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void drive(Cell* cell);
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int from_hdl_index(int hdl_index) {
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int zero_index = hdl_index - start_offset;
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