mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-06 18:01:08 +00:00
bufnorm: fix priority when connecting new driver to existing inout wire
This commit is contained in:
parent
1770a7a11b
commit
741e088e3a
1 changed files with 2 additions and 1 deletions
|
@ -4269,8 +4269,9 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
|
|||
if (pd == PD_OUTPUT) {
|
||||
pair<RTLIL::Cell*, RTLIL::IdString> other_key(w->driverCell_, w->driverPort_);
|
||||
module->bufNormQueue.insert(other_key);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
w->driverCell_ = this;
|
||||
w->driverPort_ = portname;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue