Yosys sync

tests/various/keep_hierarchy.ys

@@ -0,0 +1,53 @@
+read_verilog <<EOF
+(* blackbox *)
+(* gate_cost_equivalent=150 *)
+module macro;
+endmodule
+
+module branch1;
+	macro inst1();
+	macro inst2();
+	macro inst3();
+endmodule
+
+module branch2;
+	macro inst1();
+	macro inst2();
+	macro inst3();
+	macro inst4();
+endmodule
+
+// branch3_submod on its own doesn't meet the threshold
+module branch3_submod();
+	wire [2:0] y;
+	wire [2:0] a;
+	wire [2:0] b;
+	assign y = a * b;
+endmodule
+
+// on the other hand four branch3_submods do
+module branch3;
+	branch3_submod inst1();
+	branch3_submod inst2();
+	branch3_submod inst3();
+	branch3_submod inst4();
+endmodule
+
+// wrapper should have zero cost when branch3 is marked
+// keep_hierarchy
+module branch3_wrapper;
+	branch3 inst();
+endmodule
+
+module top;
+	branch1 inst1();
+	branch2 inst2();
+	branch3_wrapper wrapper();
+endmodule
+EOF
+
+hierarchy -top top
+keep_hierarchy -min_cost 500
+select -assert-mod-count 2 A:keep_hierarchy
+select -assert-any A:keep_hierarchy branch2 %i
+select -assert-any A:keep_hierarchy branch3 %i

tests/various/wrapcell.ys

@@ -0,0 +1,25 @@
+read_verilog <<EOF
+module top(
+	input [1:0] a,
+	input [2:0] b,
+	output [2:0] y,
+	input [2:0] a2,
+	input [3:0] b2,
+	output [3:0] y2,
+ 	input [1:0] a3,
+ 	input [2:0] b3,
+ 	output [2:0] y3
+);
+	assign y = a | (*keep*) b;
+	assign y2 = a2 | (*keep*) b2;
+	assign y3 = a3 | (*keep*) b3;
+endmodule
+EOF
+
+wreduce
+wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}
+select -assert-count 2 top/t:OR_2_3_3
+select -assert-count 1 top/t:OR_3_4_4
+select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 %% top/t:* %D
+select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
+select -assert-mod-count 2 A:bar=w3 A:bar=w4