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Yosys sync

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This commit is contained in:
Akash Levy 2024-12-04 14:16:55 -08:00
commit 4356eae4c9
54 changed files with 1651 additions and 1040 deletions
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13
passes/techmap/techmap.cc
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@ -1038,6 +1038,9 @@ struct TechmapPass : public Pass {
log(" map file. Note that the Verilog frontend is also called with the\n");
log(" '-nooverwrite' option set.\n");
log("\n");
log(" -dont_map <celltype>\n");
log(" leave the given cell type unmapped by ignoring any mapping rules for it\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log("match cells with a type that match the text value of this attribute. Otherwise\n");
log("the module name will be used to match the cell. Multiple space-separated cell\n");
@ -1169,6 +1172,7 @@ struct TechmapPass : public Pass {
simplemap_get_mappers(worker.simplemap_mappers);
std::vector<std::string> map_files;
std::vector<RTLIL::IdString> dont_map;
std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
int max_iter = -1;
@ -1210,6 +1214,10 @@ struct TechmapPass : public Pass {
worker.ignore_wb = true;
continue;
}
if (args[argidx] == "-dont_map" && argidx+1 < args.size()) {
dont_map.push_back(RTLIL::escape_id(args[++argidx]));
continue;
}
break;
}
extra_args(args, argidx, design);
@ -1266,6 +1274,11 @@ struct TechmapPass : public Pass {
celltypeMap[module_name].insert(module->name);
}
}
// Erase any rules disabled with a -dont_map argument
for (auto type : dont_map)
celltypeMap.erase(type);
log_debug("Cell type mappings to use:\n");
for (auto &i : celltypeMap) {
i.second.sort(RTLIL::sort_by_id_str());