mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-27 08:28:45 +00:00
Yosys sync
This commit is contained in:
Akash Levy
commit
4356eae4c9
54 changed files with 1651 additions and 1040 deletions
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@ -57,6 +57,7 @@ synth -top my_design -booth
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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#include "kernel/macc.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -207,12 +208,33 @@ struct BoothPassWorker {
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void run()
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{
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for (auto cell : module->selected_cells()) {
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if (cell->type != ID($mul))
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continue;
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SigSpec A, B, Y;
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bool is_signed;
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if (cell->type == ID($mul)) {
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A = cell->getPort(ID::A);
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B = cell->getPort(ID::B);
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Y = cell->getPort(ID::Y);
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log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
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is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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} else if (cell->type == ID($macc)) {
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Macc macc;
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macc.from_cell(cell);
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if (!macc.is_simple_product()) {
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log_debug("Not mapping cell %s: not a simple macc cell\n", log_id(cell));
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continue;
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}
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A = macc.ports[0].in_a;
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B = macc.ports[0].in_b;
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is_signed = macc.ports[0].is_signed;
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Y = cell->getPort(ID::Y);
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} else {
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continue;
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}
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SigSpec A = cell->getPort(ID::A);
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SigSpec B = cell->getPort(ID::B);
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SigSpec Y = cell->getPort(ID::Y);
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int x_sz = GetSize(A), y_sz = GetSize(B), z_sz = GetSize(Y);
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if (x_sz < 4 || y_sz < 4 || z_sz < 8) {
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@ -221,9 +243,6 @@ struct BoothPassWorker {
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continue;
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}
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log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
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bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
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log("Mapping cell %s to %s Booth multiplier\n", log_id(cell), is_signed ? "signed" : "unsigned");
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// To simplify the generator size the arguments
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@ -40,29 +40,15 @@ ClockGateCell icg_from_arg(std::string& name, std::string& str) {
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}
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static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
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find_icgs(std::string filename, std::vector<std::string> const& dont_use_cells) {
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std::ifstream f;
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f.open(filename.c_str());
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if (f.fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", filename.c_str(), strerror(errno));
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LibertyParser libparser(f);
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f.close();
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auto ast = libparser.ast;
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find_icgs(std::vector<const LibertyAst *> cells, std::vector<std::string> const& dont_use_cells) {
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// We will pick the most suitable ICG absed on tie_lo count and area
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struct ICGRankable : public ClockGateCell { double area; };
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std::optional<ICGRankable> best_pos;
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std::optional<ICGRankable> best_neg;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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// This is a lot of boilerplate, isn't it?
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for (auto cell : ast->children)
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for (auto cell : cells)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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@ -223,7 +209,7 @@ struct ClockgatePass : public Pass {
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log(" cell with ports named <ce>, <clk>, <gclk>.\n");
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log(" The ICG's clock enable pin must be active high.\n");
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log(" -liberty <filename>\n");
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log(" If specified, ICGs will be selected from the liberty file\n");
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log(" If specified, ICGs will be selected from the liberty files\n");
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log(" if available. Priority is given to cells with fewer tie_lo\n");
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log(" inputs and smaller size. This removes the need to manually\n");
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log(" specify -pos or -neg and -tie_lo.\n");
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@ -281,7 +267,7 @@ struct ClockgatePass : public Pass {
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std::optional<ClockGateCell> pos_icg_desc;
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std::optional<ClockGateCell> neg_icg_desc;
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std::vector<std::string> tie_lo_pins;
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std::string liberty_file;
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std::vector<std::string> liberty_files;
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std::vector<std::string> dont_use_cells;
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int min_net_size = 0;
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@ -291,18 +277,23 @@ struct ClockgatePass : public Pass {
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auto name = args[++argidx];
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auto rest = args[++argidx];
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pos_icg_desc = icg_from_arg(name, rest);
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continue;
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}
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if (args[argidx] == "-neg" && argidx+2 < args.size()) {
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auto name = args[++argidx];
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auto rest = args[++argidx];
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neg_icg_desc = icg_from_arg(name, rest);
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continue;
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}
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if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) {
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tie_lo_pins.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
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liberty_file = args[++argidx];
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std::string liberty_file = args[++argidx];
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rewrite_filename(liberty_file);
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liberty_files.push_back(liberty_file);
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continue;
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}
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if (args[argidx] == "-dont_use" && argidx+1 < args.size()) {
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dont_use_cells.push_back(args[++argidx]);
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@ -310,13 +301,25 @@ struct ClockgatePass : public Pass {
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}
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if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
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min_net_size = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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if (!liberty_file.empty())
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if (!liberty_files.empty()) {
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LibertyMergedCells merged;
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for (auto path : liberty_files) {
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std::ifstream f;
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f.open(path.c_str());
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if (f.fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", path.c_str(), strerror(errno));
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LibertyParser p(f);
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merged.merge(p);
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f.close();
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}
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std::tie(pos_icg_desc, neg_icg_desc) =
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find_icgs(liberty_file, dont_use_cells);
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else {
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find_icgs(merged.cells, dont_use_cells);
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} else {
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for (auto pin : tie_lo_pins) {
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if (pos_icg_desc)
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pos_icg_desc->tie_lo_pins.push_back(pin);
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@ -229,7 +229,7 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin
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return false;
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}
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static void find_cell(const LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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@ -237,14 +237,8 @@ static void find_cell(const LibertyAst *ast, IdString cell_type, bool clkpol, bo
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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for (auto cell : cells)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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@ -355,7 +349,7 @@ static void find_cell(const LibertyAst *ast, IdString cell_type, bool clkpol, bo
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}
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}
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static void find_cell_sr(const LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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@ -365,14 +359,8 @@ static void find_cell_sr(const LibertyAst *ast, IdString cell_type, bool clkpol,
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log_assert(!enapol && "set/reset cell with enable is unimplemented due to lack of cells for testing");
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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for (auto cell : cells)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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@ -561,7 +549,7 @@ struct DfflibmapPass : public Pass {
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log(" dfflibmap [-prepare] [-map-only] [-info] [-dont_use <cell_name>] -liberty <file> [selection]\n");
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log("\n");
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log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
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log("library specified in the given liberty file.\n");
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log("library specified in the given liberty files.\n");
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log("\n");
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log("This pass may add inverters as needed. Therefore it is recommended to\n");
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log("first run this pass and then map the logic paths to the target technology.\n");
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@ -590,11 +578,11 @@ struct DfflibmapPass : public Pass {
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log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
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log_push();
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std::string liberty_file;
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bool prepare_mode = false;
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bool map_only_mode = false;
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bool info_mode = false;
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std::vector<std::string> liberty_files;
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std::vector<std::string> dont_use_cells;
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size_t argidx;
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@ -602,8 +590,9 @@ struct DfflibmapPass : public Pass {
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{
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std::string arg = args[argidx];
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if (arg == "-liberty" && argidx+1 < args.size()) {
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liberty_file = args[++argidx];
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std::string liberty_file = args[++argidx];
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rewrite_filename(liberty_file);
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liberty_files.push_back(liberty_file);
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continue;
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}
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if (arg == "-prepare") {
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@ -636,41 +625,45 @@ struct DfflibmapPass : public Pass {
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if (modes > 1)
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log_cmd_error("Only one of -prepare, -map-only, or -info options should be given!\n");
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if (liberty_file.empty())
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if (liberty_files.empty())
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log_cmd_error("Missing `-liberty liberty_file' option!\n");
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std::ifstream f;
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f.open(liberty_file.c_str());
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if (f.fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
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LibertyParser libparser(f);
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f.close();
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LibertyMergedCells merged;
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for (auto path : liberty_files) {
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std::ifstream f;
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f.open(path.c_str());
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if (f.fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", path.c_str(), strerror(errno));
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LibertyParser p(f);
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merged.merge(p);
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f.close();
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}
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find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
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find_cell(libparser.ast, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
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find_cell(libparser.ast, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
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find_cell(merged.cells, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
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find_cell(merged.cells, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
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find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
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find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
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find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
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find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
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find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
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find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
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find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
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find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
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find_cell_sr(merged.cells, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
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find_cell_sr(merged.cells, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
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find_cell_sr(merged.cells, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
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find_cell_sr(merged.cells, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
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find_cell_sr(merged.cells, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
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find_cell_sr(merged.cells, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
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find_cell_sr(merged.cells, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
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find_cell_sr(merged.cells, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
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log(" final dff cell mappings:\n");
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logmap_all();
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|
|
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@ -517,12 +517,12 @@ LibertyAst *LibertyParser::parse()
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#ifndef FILTERLIB
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void LibertyParser::error()
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void LibertyParser::error() const
|
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{
|
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log_error("Syntax error in liberty file on line %d.\n", line);
|
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}
|
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|
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void LibertyParser::error(const std::string &str)
|
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void LibertyParser::error(const std::string &str) const
|
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{
|
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std::stringstream ss;
|
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ss << "Syntax error in liberty file on line " << line << ".\n";
|
||||
|
|
@ -532,13 +532,13 @@ void LibertyParser::error(const std::string &str)
|
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|
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#else
|
||||
|
||||
void LibertyParser::error()
|
||||
void LibertyParser::error() const
|
||||
{
|
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fprintf(stderr, "Syntax error in liberty file on line %d.\n", line);
|
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exit(1);
|
||||
}
|
||||
|
||||
void LibertyParser::error(const std::string &str)
|
||||
void LibertyParser::error(const std::string &str) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
ss << "Syntax error in liberty file on line " << line << ".\n";
|
||||
|
|
|
|||
|
|
@ -86,8 +86,10 @@ namespace Yosys
|
|||
bool eval(dict<std::string, bool>& values);
|
||||
};
|
||||
|
||||
class LibertyMergedCells;
|
||||
class LibertyParser
|
||||
{
|
||||
friend class LibertyMergedCells;
|
||||
private:
|
||||
std::istream &f;
|
||||
int line;
|
||||
|
|
@ -98,10 +100,10 @@ namespace Yosys
|
|||
anything else is a single character.
|
||||
*/
|
||||
int lexer(std::string &str);
|
||||
|
||||
|
||||
LibertyAst *parse();
|
||||
void error();
|
||||
void error(const std::string &str);
|
||||
void error() const;
|
||||
void error(const std::string &str) const;
|
||||
|
||||
public:
|
||||
const LibertyAst *ast;
|
||||
|
|
@ -109,6 +111,35 @@ namespace Yosys
|
|||
LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {}
|
||||
~LibertyParser() { if (ast) delete ast; }
|
||||
};
|
||||
|
||||
class LibertyMergedCells
|
||||
{
|
||||
std::vector<const LibertyAst *> asts;
|
||||
|
||||
public:
|
||||
std::vector<const LibertyAst *> cells;
|
||||
void merge(LibertyParser &parser)
|
||||
{
|
||||
if (parser.ast) {
|
||||
const LibertyAst *ast = parser.ast;
|
||||
asts.push_back(ast);
|
||||
// The parser no longer owns its top level ast, but we do.
|
||||
// sketchy zone
|
||||
parser.ast = nullptr;
|
||||
if (ast->id != "library")
|
||||
parser.error("Top level entity isn't \"library\".\n");
|
||||
for (const LibertyAst *cell : ast->children)
|
||||
if (cell->id == "cell" && cell->args.size() == 1)
|
||||
cells.push_back(cell);
|
||||
}
|
||||
}
|
||||
~LibertyMergedCells()
|
||||
{
|
||||
for (auto ast : asts)
|
||||
delete ast;
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1038,6 +1038,9 @@ struct TechmapPass : public Pass {
|
|||
log(" map file. Note that the Verilog frontend is also called with the\n");
|
||||
log(" '-nooverwrite' option set.\n");
|
||||
log("\n");
|
||||
log(" -dont_map <celltype>\n");
|
||||
log(" leave the given cell type unmapped by ignoring any mapping rules for it\n");
|
||||
log("\n");
|
||||
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
|
||||
log("match cells with a type that match the text value of this attribute. Otherwise\n");
|
||||
log("the module name will be used to match the cell. Multiple space-separated cell\n");
|
||||
|
|
@ -1169,6 +1172,7 @@ struct TechmapPass : public Pass {
|
|||
simplemap_get_mappers(worker.simplemap_mappers);
|
||||
|
||||
std::vector<std::string> map_files;
|
||||
std::vector<RTLIL::IdString> dont_map;
|
||||
std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
|
||||
int max_iter = -1;
|
||||
|
||||
|
|
@ -1210,6 +1214,10 @@ struct TechmapPass : public Pass {
|
|||
worker.ignore_wb = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-dont_map" && argidx+1 < args.size()) {
|
||||
dont_map.push_back(RTLIL::escape_id(args[++argidx]));
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
|
@ -1266,6 +1274,11 @@ struct TechmapPass : public Pass {
|
|||
celltypeMap[module_name].insert(module->name);
|
||||
}
|
||||
}
|
||||
|
||||
// Erase any rules disabled with a -dont_map argument
|
||||
for (auto type : dont_map)
|
||||
celltypeMap.erase(type);
|
||||
|
||||
log_debug("Cell type mappings to use:\n");
|
||||
for (auto &i : celltypeMap) {
|
||||
i.second.sort(RTLIL::sort_by_id_str());
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue