mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-07 19:51:23 +00:00
Yosys sync
This commit is contained in:
Akash Levy
commit
4356eae4c9
54 changed files with 1651 additions and 1040 deletions
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@ -53,6 +53,9 @@ OBJS += passes/cmds/future.o
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OBJS += passes/cmds/box_derive.o
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OBJS += passes/cmds/example_dt.o
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OBJS += passes/cmds/portarcs.o
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OBJS += passes/cmds/activity.o
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OBJS += passes/cmds/splitnetlist.o
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OBJS += passes/cmds/reconstructbusses.o
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OBJS += passes/cmds/wrapcell.o
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170
passes/cmds/wrapcell.cc
Normal file
170
passes/cmds/wrapcell.cc
Normal file
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@ -0,0 +1,170 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Martin Povišer <povik@cutebit.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "backends/rtlil/rtlil_backend.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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std::optional<std::string> format(std::string fmt, const dict<IdString, Const> ¶meters)
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{
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std::stringstream result;
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auto it = fmt.begin();
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while (it != fmt.end()) {
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if (*it == '{') {
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it++;
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auto beg = it;
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while (it != fmt.end() && *it != '}') it++;
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if (it == fmt.end()) {
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log("Unclosed curly brackets in format string '%s'\n", fmt.c_str());
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return {};
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}
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auto id = RTLIL::escape_id(std::string(beg, it));
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if (!parameters.count(id)) {
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log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
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return {};
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}
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RTLIL_BACKEND::dump_const(result, parameters.at(id));
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} else {
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result << *it;
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}
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it++;
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}
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return {result.str()};
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}
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struct WrapcellPass : Pass {
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WrapcellPass() : Pass("wrapcell", "wrap individual cells into new modules") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" wrapcell -name <format> [selection]\n");
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log("\n");
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log("This command wraps the selected cells individually into modules. The name for\n");
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log("each wrapper module is derived from the template <format> by substituting\n");
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log("parameter values as specified in curly brackets. If the named module already\n");
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log("exists, it is reused.\n");
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log("\n");
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log(" -setattr <attribute-name>\n");
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log(" set the given boolean attribute on each created wrapper module\n");
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log("\n");
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log(" -formatattr <attribute-name> <format>\n");
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log(" set a string attribute on the created wrapper module by substituting\n");
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log(" parameter values into <format>\n");
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log("\n");
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log("Currently this command only supports wrapping internal cell types.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, Design *d) override
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{
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log_header(d, "Executing WRAPCELL pass. (wrap selected cells)\n");
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struct AttrRule {
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IdString name;
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std::string value_fmt;
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AttrRule(IdString name, std::string value_fmt)
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: name(name), value_fmt(value_fmt) {}
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};
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std::vector<AttrRule> attributes;
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std::string name_fmt;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-setattr" && argidx+1 < args.size()) {
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attributes.emplace_back(RTLIL::escape_id(args[++argidx]), "");
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} else if (args[argidx] == "-formatattr" && argidx+2 < args.size()) {
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IdString id = RTLIL::escape_id(args[++argidx]);
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attributes.emplace_back(id, args[++argidx]);
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} else if (args[argidx] == "-name" && argidx+1 < args.size()) {
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name_fmt = args[++argidx];
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} else {
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break;
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}
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}
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extra_args(args, argidx, d);
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if (name_fmt.empty())
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log_cmd_error("Argument -name required");
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CellTypes ct;
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ct.setup();
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for (auto module : d->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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std::optional<std::string> unescaped_name = format(name_fmt, cell->parameters);
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if (!unescaped_name)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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log_id(cell), log_id(module));
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IdString name = RTLIL::escape_id(unescaped_name.value());
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if (d->module(name)) {
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cell->type = name;
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cell->parameters.clear();
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continue;
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}
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if (!ct.cell_known(cell->type))
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log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
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log_id(cell->type), log_id(cell), log_id(module));
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Module *subm = d->addModule(name);
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Cell *subcell = subm->addCell("$1", cell->type);
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for (auto conn : cell->connections()) {
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Wire *w = subm->addWire(conn.first, conn.second.size());
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if (ct.cell_output(cell->type, w->name))
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w->port_output = true;
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else
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w->port_input = true;
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subcell->setPort(conn.first, w);
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}
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subcell->parameters = cell->parameters;
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subm->fixup_ports();
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for (auto rule : attributes) {
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if (rule.value_fmt.empty()) {
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subm->set_bool_attribute(rule.name);
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} else {
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std::optional<std::string> value = format(rule.value_fmt, cell->parameters);
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if (!value)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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log_id(cell), log_id(module));
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subm->set_string_attribute(rule.name, value.value());
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}
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}
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cell->type = name;
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cell->parameters.clear();
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}
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}
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}
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} WrapcellPass;
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PRIVATE_NAMESPACE_END
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@ -54,7 +54,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
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RTLIL::Const pattern = it.first;
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RTLIL::SigSpec eq_sig_a, eq_sig_b, or_sig;
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for (size_t j = 0; j < pattern.size(); j++)
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for (auto j = 0; j < pattern.size(); j++)
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if (pattern[j] == RTLIL::State::S0 || pattern[j] == RTLIL::State::S1) {
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eq_sig_a.append(ctrl_in.extract(j, 1));
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eq_sig_b.append(RTLIL::SigSpec(pattern[j]));
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@ -198,7 +198,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
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RTLIL::Const state = fsm_data.state_table[i];
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RTLIL::SigSpec sig_a, sig_b;
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for (size_t j = 0; j < state.size(); j++)
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for (auto j = 0; j < state.size(); j++)
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if (state[j] == RTLIL::State::S0 || state[j] == RTLIL::State::S1) {
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sig_a.append(RTLIL::SigSpec(state_wire, j));
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sig_b.append(RTLIL::SigSpec(state[j]));
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@ -261,7 +261,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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int bit_idx = -1;
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for (size_t j = 0; j < state.size(); j++)
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for (auto j = 0; j < state.size(); j++)
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if (state[j] == RTLIL::State::S1)
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bit_idx = j;
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if (bit_idx >= 0)
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@ -23,20 +23,80 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ThresholdHierarchyKeeping {
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Design *design;
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CellCosts costs;
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dict<Module *, int> done;
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pool<Module *> in_progress;
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uint64_t threshold;
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ThresholdHierarchyKeeping(Design *design, uint64_t threshold)
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: design(design), costs(design), threshold(threshold) {}
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uint64_t visit(RTLIL::Module *module) {
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if (module->has_attribute(ID(gate_cost_equivalent)))
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return module->attributes[ID(gate_cost_equivalent)].as_int();
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if (module->has_attribute(ID(keep_hierarchy)))
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return 0;
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if (module->get_blackbox_attribute())
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log_error("Missing cost information on instanced blackbox %s\n", log_id(module));
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if (done.count(module))
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return done.at(module);
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if (in_progress.count(module))
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log_error("Circular hierarchy\n");
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in_progress.insert(module);
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uint64_t size = 0;
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module->has_processes_warn();
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for (auto cell : module->cells()) {
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if (!cell->type.isPublic()) {
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size += costs.get(cell);
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} else {
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RTLIL::Module *submodule = design->module(cell->type);
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if (!submodule)
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log_error("Hierarchy contains unknown module '%s' (instanced as %s in %s)\n",
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log_id(cell->type), log_id(cell), log_id(module));
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size += visit(submodule);
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}
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}
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if (size > threshold) {
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log("Keeping %s (estimated size above threshold: %llu > %llu).\n", log_id(module), size, threshold);
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module->set_bool_attribute(ID::keep_hierarchy);
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size = 0;
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}
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in_progress.erase(module);
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done[module] = size;
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return size;
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}
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};
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struct KeepHierarchyPass : public Pass {
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KeepHierarchyPass() : Pass("keep_hierarchy", "add the keep_hierarchy attribute") {}
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KeepHierarchyPass() : Pass("keep_hierarchy", "selectively add the keep_hierarchy attribute") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" keep_hierarchy [options]\n");
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log(" keep_hierarchy [options] [selection]\n");
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log("\n");
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log("Add the keep_hierarchy attribute.\n");
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log("\n");
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log(" -min_cost <min_cost>\n");
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log(" only add the attribute to modules estimated to have more\n");
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log(" than <min_cost> gates after simple techmapping. Intended\n");
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log(" for tuning trade-offs between quality and yosys runtime.\n");
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log(" only add the attribute to modules estimated to have more than <min_cost>\n");
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log(" gates after simple techmapping. Intended for tuning trade-offs between\n");
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log(" quality and yosys runtime.\n");
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log("\n");
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log(" When evaluating a module's cost, gates which are within a submodule\n");
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log(" which is marked with the keep_hierarchy attribute are not counted\n");
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log(" towards the upper module's cost. This applies to both when the attribute\n");
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log(" was added by this command or was pre-existing.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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@ -54,16 +114,15 @@ struct KeepHierarchyPass : public Pass {
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}
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extra_args(args, argidx, design);
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CellCosts costs(design);
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if (min_cost) {
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RTLIL::Module *top = design->top_module();
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if (!top)
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log_cmd_error("'-min_cost' mode requires a single top module in the design\n");
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for (auto module : design->selected_modules()) {
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if (min_cost) {
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unsigned int cost = costs.get(module);
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if (cost > min_cost) {
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log("Marking %s (module too big: %d > %d).\n", log_id(module), cost, min_cost);
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module->set_bool_attribute(ID::keep_hierarchy);
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}
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} else {
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ThresholdHierarchyKeeping worker(design, min_cost);
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worker.visit(top);
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} else {
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for (auto module : design->selected_modules()) {
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log("Marking %s.\n", log_id(module));
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module->set_bool_attribute(ID::keep_hierarchy);
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}
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|
|
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@ -57,6 +57,7 @@ synth -top my_design -booth
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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#include "kernel/macc.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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|
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@ -207,12 +208,33 @@ struct BoothPassWorker {
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void run()
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{
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for (auto cell : module->selected_cells()) {
|
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if (cell->type != ID($mul))
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continue;
|
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SigSpec A, B, Y;
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bool is_signed;
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|
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if (cell->type == ID($mul)) {
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A = cell->getPort(ID::A);
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B = cell->getPort(ID::B);
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Y = cell->getPort(ID::Y);
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log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
|
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is_signed = cell->getParam(ID::A_SIGNED).as_bool();
|
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} else if (cell->type == ID($macc)) {
|
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Macc macc;
|
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macc.from_cell(cell);
|
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|
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if (!macc.is_simple_product()) {
|
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log_debug("Not mapping cell %s: not a simple macc cell\n", log_id(cell));
|
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continue;
|
||||
}
|
||||
|
||||
A = macc.ports[0].in_a;
|
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B = macc.ports[0].in_b;
|
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is_signed = macc.ports[0].is_signed;
|
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Y = cell->getPort(ID::Y);
|
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} else {
|
||||
continue;
|
||||
}
|
||||
|
||||
SigSpec A = cell->getPort(ID::A);
|
||||
SigSpec B = cell->getPort(ID::B);
|
||||
SigSpec Y = cell->getPort(ID::Y);
|
||||
int x_sz = GetSize(A), y_sz = GetSize(B), z_sz = GetSize(Y);
|
||||
|
||||
if (x_sz < 4 || y_sz < 4 || z_sz < 8) {
|
||||
|
|
@ -221,9 +243,6 @@ struct BoothPassWorker {
|
|||
continue;
|
||||
}
|
||||
|
||||
log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
|
||||
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
|
||||
|
||||
log("Mapping cell %s to %s Booth multiplier\n", log_id(cell), is_signed ? "signed" : "unsigned");
|
||||
|
||||
// To simplify the generator size the arguments
|
||||
|
|
|
|||
|
|
@ -40,29 +40,15 @@ ClockGateCell icg_from_arg(std::string& name, std::string& str) {
|
|||
}
|
||||
|
||||
static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
|
||||
find_icgs(std::string filename, std::vector<std::string> const& dont_use_cells) {
|
||||
std::ifstream f;
|
||||
f.open(filename.c_str());
|
||||
if (f.fail())
|
||||
log_cmd_error("Can't open liberty file `%s': %s\n", filename.c_str(), strerror(errno));
|
||||
LibertyParser libparser(f);
|
||||
f.close();
|
||||
auto ast = libparser.ast;
|
||||
|
||||
find_icgs(std::vector<const LibertyAst *> cells, std::vector<std::string> const& dont_use_cells) {
|
||||
// We will pick the most suitable ICG absed on tie_lo count and area
|
||||
struct ICGRankable : public ClockGateCell { double area; };
|
||||
std::optional<ICGRankable> best_pos;
|
||||
std::optional<ICGRankable> best_neg;
|
||||
|
||||
if (ast->id != "library")
|
||||
log_error("Format error in liberty file.\n");
|
||||
|
||||
// This is a lot of boilerplate, isn't it?
|
||||
for (auto cell : ast->children)
|
||||
for (auto cell : cells)
|
||||
{
|
||||
if (cell->id != "cell" || cell->args.size() != 1)
|
||||
continue;
|
||||
|
||||
const LibertyAst *dn = cell->find("dont_use");
|
||||
if (dn != nullptr && dn->value == "true")
|
||||
continue;
|
||||
|
|
@ -223,7 +209,7 @@ struct ClockgatePass : public Pass {
|
|||
log(" cell with ports named <ce>, <clk>, <gclk>.\n");
|
||||
log(" The ICG's clock enable pin must be active high.\n");
|
||||
log(" -liberty <filename>\n");
|
||||
log(" If specified, ICGs will be selected from the liberty file\n");
|
||||
log(" If specified, ICGs will be selected from the liberty files\n");
|
||||
log(" if available. Priority is given to cells with fewer tie_lo\n");
|
||||
log(" inputs and smaller size. This removes the need to manually\n");
|
||||
log(" specify -pos or -neg and -tie_lo.\n");
|
||||
|
|
@ -281,7 +267,7 @@ struct ClockgatePass : public Pass {
|
|||
std::optional<ClockGateCell> pos_icg_desc;
|
||||
std::optional<ClockGateCell> neg_icg_desc;
|
||||
std::vector<std::string> tie_lo_pins;
|
||||
std::string liberty_file;
|
||||
std::vector<std::string> liberty_files;
|
||||
std::vector<std::string> dont_use_cells;
|
||||
int min_net_size = 0;
|
||||
|
||||
|
|
@ -291,18 +277,23 @@ struct ClockgatePass : public Pass {
|
|||
auto name = args[++argidx];
|
||||
auto rest = args[++argidx];
|
||||
pos_icg_desc = icg_from_arg(name, rest);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-neg" && argidx+2 < args.size()) {
|
||||
auto name = args[++argidx];
|
||||
auto rest = args[++argidx];
|
||||
neg_icg_desc = icg_from_arg(name, rest);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) {
|
||||
tie_lo_pins.push_back(RTLIL::escape_id(args[++argidx]));
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
|
||||
liberty_file = args[++argidx];
|
||||
std::string liberty_file = args[++argidx];
|
||||
rewrite_filename(liberty_file);
|
||||
liberty_files.push_back(liberty_file);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-dont_use" && argidx+1 < args.size()) {
|
||||
dont_use_cells.push_back(args[++argidx]);
|
||||
|
|
@ -310,13 +301,25 @@ struct ClockgatePass : public Pass {
|
|||
}
|
||||
if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
|
||||
min_net_size = atoi(args[++argidx].c_str());
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (!liberty_file.empty())
|
||||
if (!liberty_files.empty()) {
|
||||
LibertyMergedCells merged;
|
||||
for (auto path : liberty_files) {
|
||||
std::ifstream f;
|
||||
f.open(path.c_str());
|
||||
if (f.fail())
|
||||
log_cmd_error("Can't open liberty file `%s': %s\n", path.c_str(), strerror(errno));
|
||||
LibertyParser p(f);
|
||||
merged.merge(p);
|
||||
f.close();
|
||||
}
|
||||
std::tie(pos_icg_desc, neg_icg_desc) =
|
||||
find_icgs(liberty_file, dont_use_cells);
|
||||
else {
|
||||
find_icgs(merged.cells, dont_use_cells);
|
||||
} else {
|
||||
for (auto pin : tie_lo_pins) {
|
||||
if (pos_icg_desc)
|
||||
pos_icg_desc->tie_lo_pins.push_back(pin);
|
||||
|
|
|
|||
|
|
@ -229,7 +229,7 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin
|
|||
return false;
|
||||
}
|
||||
|
||||
static void find_cell(const LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
|
||||
static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
|
||||
{
|
||||
const LibertyAst *best_cell = nullptr;
|
||||
std::map<std::string, char> best_cell_ports;
|
||||
|
|
@ -237,14 +237,8 @@ static void find_cell(const LibertyAst *ast, IdString cell_type, bool clkpol, bo
|
|||
bool best_cell_noninv = false;
|
||||
double best_cell_area = 0;
|
||||
|
||||
if (ast->id != "library")
|
||||
log_error("Format error in liberty file.\n");
|
||||
|
||||
for (auto cell : ast->children)
|
||||
for (auto cell : cells)
|
||||
{
|
||||
if (cell->id != "cell" || cell->args.size() != 1)
|
||||
continue;
|
||||
|
||||
const LibertyAst *dn = cell->find("dont_use");
|
||||
if (dn != nullptr && dn->value == "true")
|
||||
continue;
|
||||
|
|
@ -355,7 +349,7 @@ static void find_cell(const LibertyAst *ast, IdString cell_type, bool clkpol, bo
|
|||
}
|
||||
}
|
||||
|
||||
static void find_cell_sr(const LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
|
||||
static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
|
||||
{
|
||||
const LibertyAst *best_cell = nullptr;
|
||||
std::map<std::string, char> best_cell_ports;
|
||||
|
|
@ -365,14 +359,8 @@ static void find_cell_sr(const LibertyAst *ast, IdString cell_type, bool clkpol,
|
|||
|
||||
log_assert(!enapol && "set/reset cell with enable is unimplemented due to lack of cells for testing");
|
||||
|
||||
if (ast->id != "library")
|
||||
log_error("Format error in liberty file.\n");
|
||||
|
||||
for (auto cell : ast->children)
|
||||
for (auto cell : cells)
|
||||
{
|
||||
if (cell->id != "cell" || cell->args.size() != 1)
|
||||
continue;
|
||||
|
||||
const LibertyAst *dn = cell->find("dont_use");
|
||||
if (dn != nullptr && dn->value == "true")
|
||||
continue;
|
||||
|
|
@ -561,7 +549,7 @@ struct DfflibmapPass : public Pass {
|
|||
log(" dfflibmap [-prepare] [-map-only] [-info] [-dont_use <cell_name>] -liberty <file> [selection]\n");
|
||||
log("\n");
|
||||
log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
|
||||
log("library specified in the given liberty file.\n");
|
||||
log("library specified in the given liberty files.\n");
|
||||
log("\n");
|
||||
log("This pass may add inverters as needed. Therefore it is recommended to\n");
|
||||
log("first run this pass and then map the logic paths to the target technology.\n");
|
||||
|
|
@ -590,11 +578,11 @@ struct DfflibmapPass : public Pass {
|
|||
log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
|
||||
log_push();
|
||||
|
||||
std::string liberty_file;
|
||||
bool prepare_mode = false;
|
||||
bool map_only_mode = false;
|
||||
bool info_mode = false;
|
||||
|
||||
std::vector<std::string> liberty_files;
|
||||
std::vector<std::string> dont_use_cells;
|
||||
|
||||
size_t argidx;
|
||||
|
|
@ -602,8 +590,9 @@ struct DfflibmapPass : public Pass {
|
|||
{
|
||||
std::string arg = args[argidx];
|
||||
if (arg == "-liberty" && argidx+1 < args.size()) {
|
||||
liberty_file = args[++argidx];
|
||||
std::string liberty_file = args[++argidx];
|
||||
rewrite_filename(liberty_file);
|
||||
liberty_files.push_back(liberty_file);
|
||||
continue;
|
||||
}
|
||||
if (arg == "-prepare") {
|
||||
|
|
@ -636,41 +625,45 @@ struct DfflibmapPass : public Pass {
|
|||
if (modes > 1)
|
||||
log_cmd_error("Only one of -prepare, -map-only, or -info options should be given!\n");
|
||||
|
||||
if (liberty_file.empty())
|
||||
if (liberty_files.empty())
|
||||
log_cmd_error("Missing `-liberty liberty_file' option!\n");
|
||||
|
||||
std::ifstream f;
|
||||
f.open(liberty_file.c_str());
|
||||
if (f.fail())
|
||||
log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
|
||||
LibertyParser libparser(f);
|
||||
f.close();
|
||||
LibertyMergedCells merged;
|
||||
for (auto path : liberty_files) {
|
||||
std::ifstream f;
|
||||
f.open(path.c_str());
|
||||
if (f.fail())
|
||||
log_cmd_error("Can't open liberty file `%s': %s\n", path.c_str(), strerror(errno));
|
||||
LibertyParser p(f);
|
||||
merged.merge(p);
|
||||
f.close();
|
||||
}
|
||||
|
||||
find_cell(libparser.ast, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
|
||||
|
||||
find_cell(libparser.ast, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
|
||||
|
||||
find_cell(libparser.ast, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
|
||||
find_cell(libparser.ast, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
|
||||
|
||||
find_cell_sr(libparser.ast, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
|
||||
find_cell_sr(libparser.ast, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
|
||||
find_cell_sr(libparser.ast, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
|
||||
find_cell_sr(libparser.ast, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
|
||||
find_cell_sr(libparser.ast, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
|
||||
find_cell_sr(libparser.ast, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
|
||||
find_cell_sr(libparser.ast, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
|
||||
find_cell_sr(libparser.ast, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
|
||||
|
||||
log(" final dff cell mappings:\n");
|
||||
logmap_all();
|
||||
|
|
|
|||
|
|
@ -517,12 +517,12 @@ LibertyAst *LibertyParser::parse()
|
|||
|
||||
#ifndef FILTERLIB
|
||||
|
||||
void LibertyParser::error()
|
||||
void LibertyParser::error() const
|
||||
{
|
||||
log_error("Syntax error in liberty file on line %d.\n", line);
|
||||
}
|
||||
|
||||
void LibertyParser::error(const std::string &str)
|
||||
void LibertyParser::error(const std::string &str) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
ss << "Syntax error in liberty file on line " << line << ".\n";
|
||||
|
|
@ -532,13 +532,13 @@ void LibertyParser::error(const std::string &str)
|
|||
|
||||
#else
|
||||
|
||||
void LibertyParser::error()
|
||||
void LibertyParser::error() const
|
||||
{
|
||||
fprintf(stderr, "Syntax error in liberty file on line %d.\n", line);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
void LibertyParser::error(const std::string &str)
|
||||
void LibertyParser::error(const std::string &str) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
ss << "Syntax error in liberty file on line " << line << ".\n";
|
||||
|
|
|
|||
|
|
@ -86,8 +86,10 @@ namespace Yosys
|
|||
bool eval(dict<std::string, bool>& values);
|
||||
};
|
||||
|
||||
class LibertyMergedCells;
|
||||
class LibertyParser
|
||||
{
|
||||
friend class LibertyMergedCells;
|
||||
private:
|
||||
std::istream &f;
|
||||
int line;
|
||||
|
|
@ -98,10 +100,10 @@ namespace Yosys
|
|||
anything else is a single character.
|
||||
*/
|
||||
int lexer(std::string &str);
|
||||
|
||||
|
||||
LibertyAst *parse();
|
||||
void error();
|
||||
void error(const std::string &str);
|
||||
void error() const;
|
||||
void error(const std::string &str) const;
|
||||
|
||||
public:
|
||||
const LibertyAst *ast;
|
||||
|
|
@ -109,6 +111,35 @@ namespace Yosys
|
|||
LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {}
|
||||
~LibertyParser() { if (ast) delete ast; }
|
||||
};
|
||||
|
||||
class LibertyMergedCells
|
||||
{
|
||||
std::vector<const LibertyAst *> asts;
|
||||
|
||||
public:
|
||||
std::vector<const LibertyAst *> cells;
|
||||
void merge(LibertyParser &parser)
|
||||
{
|
||||
if (parser.ast) {
|
||||
const LibertyAst *ast = parser.ast;
|
||||
asts.push_back(ast);
|
||||
// The parser no longer owns its top level ast, but we do.
|
||||
// sketchy zone
|
||||
parser.ast = nullptr;
|
||||
if (ast->id != "library")
|
||||
parser.error("Top level entity isn't \"library\".\n");
|
||||
for (const LibertyAst *cell : ast->children)
|
||||
if (cell->id == "cell" && cell->args.size() == 1)
|
||||
cells.push_back(cell);
|
||||
}
|
||||
}
|
||||
~LibertyMergedCells()
|
||||
{
|
||||
for (auto ast : asts)
|
||||
delete ast;
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1038,6 +1038,9 @@ struct TechmapPass : public Pass {
|
|||
log(" map file. Note that the Verilog frontend is also called with the\n");
|
||||
log(" '-nooverwrite' option set.\n");
|
||||
log("\n");
|
||||
log(" -dont_map <celltype>\n");
|
||||
log(" leave the given cell type unmapped by ignoring any mapping rules for it\n");
|
||||
log("\n");
|
||||
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
|
||||
log("match cells with a type that match the text value of this attribute. Otherwise\n");
|
||||
log("the module name will be used to match the cell. Multiple space-separated cell\n");
|
||||
|
|
@ -1169,6 +1172,7 @@ struct TechmapPass : public Pass {
|
|||
simplemap_get_mappers(worker.simplemap_mappers);
|
||||
|
||||
std::vector<std::string> map_files;
|
||||
std::vector<RTLIL::IdString> dont_map;
|
||||
std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
|
||||
int max_iter = -1;
|
||||
|
||||
|
|
@ -1210,6 +1214,10 @@ struct TechmapPass : public Pass {
|
|||
worker.ignore_wb = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-dont_map" && argidx+1 < args.size()) {
|
||||
dont_map.push_back(RTLIL::escape_id(args[++argidx]));
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
|
@ -1266,6 +1274,11 @@ struct TechmapPass : public Pass {
|
|||
celltypeMap[module_name].insert(module->name);
|
||||
}
|
||||
}
|
||||
|
||||
// Erase any rules disabled with a -dont_map argument
|
||||
for (auto type : dont_map)
|
||||
celltypeMap.erase(type);
|
||||
|
||||
log_debug("Cell type mappings to use:\n");
|
||||
for (auto &i : celltypeMap) {
|
||||
i.second.sort(RTLIL::sort_by_id_str());
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue