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Yosys sync

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This commit is contained in:
Akash Levy 2024-12-04 14:16:55 -08:00
commit 4356eae4c9
54 changed files with 1651 additions and 1040 deletions
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27
kernel/rtlil.cc
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@ -381,7 +381,7 @@ int RTLIL::Const::as_int(bool is_signed) const
return ret;
}
size_t RTLIL::Const::get_min_size(bool is_signed) const
int RTLIL::Const::get_min_size(bool is_signed) const
{
if (empty()) return 0;
@ -392,7 +392,7 @@ size_t RTLIL::Const::get_min_size(bool is_signed) const
else
leading_bit = RTLIL::State::S0;
size_t idx = size();
auto idx = size();
while (idx > 0 && (*this)[idx -1] == leading_bit) {
idx--;
}
@ -407,22 +407,22 @@ size_t RTLIL::Const::get_min_size(bool is_signed) const
void RTLIL::Const::compress(bool is_signed)
{
size_t idx = get_min_size(is_signed);
auto idx = get_min_size(is_signed);
bits().erase(bits().begin() + idx, bits().end());
}
std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const
{
size_t size = get_min_size(is_signed);
auto size = get_min_size(is_signed);
if(size == 0 || size > 32)
return std::nullopt;
int32_t ret = 0;
for (size_t i = 0; i < size && i < 32; i++)
for (auto i = 0; i < size && i < 32; i++)
if ((*this)[i] == State::S1)
ret |= 1 << i;
if (is_signed && (*this)[size-1] == State::S1)
for (size_t i = size; i < 32; i++)
for (auto i = size; i < 32; i++)
ret |= 1 << i;
return ret;
}
@ -2148,6 +2148,21 @@ namespace {
check_expected();
return;
}
/*
* Checklist for adding internal cell types
* ========================================
* Things to do right away:
* - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
* - Add to InternalCellChecker::check() in kernel/rtlil.cc
* - Add to techlibs/common/simlib.v
* - Add to techlibs/common/techmap.v
*
* Things to do after finalizing the cell interface:
* - Add support to kernel/satgen.h for the new cell type
* - Add to docs/source/CHAPTER_CellLib.rst (or just add a fixme to the bottom)
* - Maybe add support to the Verilog backend for dumping such cells as expression
*
*/
error(__LINE__);
}
};