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Yosys sync

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This commit is contained in:
Akash Levy 2024-12-04 14:16:55 -08:00
commit 4356eae4c9
54 changed files with 1651 additions and 1040 deletions
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78
kernel/calc.cc
View file

@ -33,7 +33,7 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
if (arg.size() > 0 && is_signed)
padding = arg.back();
while (int(arg.size()) < width)
while (GetSize(arg) < width)
arg.bits().push_back(padding);
arg.bits().resize(width);
@ -45,7 +45,7 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
BigInteger::Sign sign = BigInteger::positive;
State inv_sign_bit = RTLIL::State::S1;
size_t num_bits = val.size();
auto num_bits = val.size();
if (as_signed && num_bits && val[num_bits-1] == RTLIL::State::S1) {
inv_sign_bit = RTLIL::State::S0;
@ -53,7 +53,7 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
num_bits--;
}
for (size_t i = 0; i < num_bits; i++)
for (auto i = 0; i < num_bits; i++)
if (val[i] == RTLIL::State::S0 || val[i] == RTLIL::State::S1)
mag.setBit(i, val[i] == inv_sign_bit);
else if (undef_bit_pos < 0)
@ -78,12 +78,12 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
if (val.getSign() < 0)
{
mag--;
for (int i = 0; i < result_len; i++)
for (auto i = 0; i < result_len; i++)
result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
}
else
{
for (int i = 0; i < result_len; i++)
for (auto i = 0; i < result_len; i++)
result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
}
}
@ -132,14 +132,14 @@ static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b)
RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{
if (result_len < 0)
result_len = arg1.size();
result_len = GetSize(arg1);
RTLIL::Const arg1_ext = arg1;
extend_u0(arg1_ext, result_len, signed1);
RTLIL::Const result(RTLIL::State::Sx, result_len);
for (size_t i = 0; i < size_t(result_len); i++) {
if (i >= arg1_ext.size())
for (auto i = 0; i < result_len; i++) {
if (i >= GetSize(arg1_ext))
result.bits()[i] = RTLIL::State::S0;
else if (arg1_ext.bits()[i] == RTLIL::State::S0)
result.bits()[i] = RTLIL::State::S1;
@ -154,15 +154,15 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1)
{
if (result_len < 0)
result_len = max(arg1.size(), arg2.size());
result_len = max(GetSize(arg1), GetSize(arg2));
extend_u0(arg1, result_len, signed1);
extend_u0(arg2, result_len, signed2);
RTLIL::Const result(RTLIL::State::Sx, result_len);
for (size_t i = 0; i < size_t(result_len); i++) {
RTLIL::State a = i < arg1.size() ? arg1.bits()[i] : RTLIL::State::S0;
RTLIL::State b = i < arg2.size() ? arg2.bits()[i] : RTLIL::State::S0;
for (auto i = 0; i < result_len; i++) {
RTLIL::State a = i < GetSize(arg1) ? arg1.bits()[i] : RTLIL::State::S0;
RTLIL::State b = i < GetSize(arg2) ? arg2.bits()[i] : RTLIL::State::S0;
result.bits()[i] = logic_func(a, b);
}
@ -193,11 +193,11 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log
{
RTLIL::State temp = initial;
for (size_t i = 0; i < arg1.size(); i++)
for (auto i = 0; i < arg1.size(); i++)
temp = logic_func(temp, arg1[i]);
RTLIL::Const result(temp);
while (int(result.size()) < result_len)
while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0);
return result;
}
@ -240,7 +240,7 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const
BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len)
while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0);
return result;
}
@ -255,7 +255,7 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const
RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
RTLIL::Const result(logic_and(bit_a, bit_b));
while (int(result.size()) < result_len)
while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0);
return result;
}
@ -270,7 +270,7 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const
RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
RTLIL::Const result(logic_or(bit_a, bit_b));
while (int(result.size()) < result_len)
while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0);
return result;
}
@ -286,7 +286,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
BigInteger offset = const2big(arg2, signed2, undef_bit_pos) * direction;
if (result_len < 0)
result_len = arg1.size();
result_len = GetSize(arg1);
RTLIL::Const result(RTLIL::State::Sx, result_len);
if (undef_bit_pos >= 0)
@ -296,7 +296,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
BigInteger pos = BigInteger(i) + offset;
if (pos < 0)
result.bits()[i] = vacant_bits;
else if (pos >= BigInteger(int(arg1.size())))
else if (pos >= BigInteger(GetSize(arg1)))
result.bits()[i] = sign_ext ? arg1.back() : vacant_bits;
else
result.bits()[i] = arg1[pos.toInt()];
@ -347,7 +347,7 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos);
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len)
while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0);
return result;
}
@ -358,7 +358,7 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos);
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len)
while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0);
return result;
}
@ -369,12 +369,12 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
RTLIL::Const arg2_ext = arg2;
RTLIL::Const result(RTLIL::State::S0, result_len);
int width = max(arg1_ext.size(), arg2_ext.size());
int width = max(GetSize(arg1_ext), GetSize(arg2_ext));
extend_u0(arg1_ext, width, signed1 && signed2);
extend_u0(arg2_ext, width, signed1 && signed2);
RTLIL::State matched_status = RTLIL::State::S1;
for (size_t i = 0; i < arg1_ext.size(); i++) {
for (auto i = 0; i < arg1_ext.size(); i++) {
if (arg1_ext.at(i) == RTLIL::State::S0 && arg2_ext.at(i) == RTLIL::State::S1)
return result;
if (arg1_ext.at(i) == RTLIL::State::S1 && arg2_ext.at(i) == RTLIL::State::S0)
@ -403,11 +403,11 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2
RTLIL::Const arg2_ext = arg2;
RTLIL::Const result(RTLIL::State::S0, result_len);
int width = max(arg1_ext.size(), arg2_ext.size());
int width = max(GetSize(arg1_ext), GetSize(arg2_ext));
extend_u0(arg1_ext, width, signed1 && signed2);
extend_u0(arg2_ext, width, signed1 && signed2);
for (size_t i = 0; i < arg1_ext.size(); i++) {
for (auto i = 0; i < arg1_ext.size(); i++) {
if (arg1_ext.at(i) != arg2_ext.at(i))
return result;
}
@ -432,7 +432,7 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos);
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len)
while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0);
return result;
}
@ -443,7 +443,7 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos);
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len)
while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0);
return result;
}
@ -452,21 +452,21 @@ RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), undef_bit_pos);
}
RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), undef_bit_pos);
}
RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
}
// truncating division
@ -480,7 +480,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2
bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative);
a = a.getSign() == BigInteger::negative ? -a : a;
b = b.getSign() == BigInteger::negative ? -b : b;
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
}
// truncating modulo
@ -494,7 +494,7 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2
bool result_neg = a.getSign() == BigInteger::negative;
a = a.getSign() == BigInteger::negative ? -a : a;
b = b.getSign() == BigInteger::negative ? -b : b;
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -516,7 +516,7 @@ RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const
// bigint division with negative numbers is wonky, make sure we only negate at the very end
result = -((a + b - 1) / b);
}
return big2const(result, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
return big2const(result, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -539,7 +539,7 @@ RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const
} else {
modulo = b_sign == BigInteger::negative ? truncated - b : truncated + b;
}
return big2const(modulo, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
return big2const(modulo, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -590,7 +590,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
y *= -1;
}
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0));
return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
}
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
@ -626,7 +626,7 @@ RTLIL::Const RTLIL::const_mux(const RTLIL::Const &arg1, const RTLIL::Const &arg2
return arg2;
RTLIL::Const ret = arg1;
for (int i = 0; i < ret.size(); i++)
for (auto i = 0; i < ret.size(); i++)
if (ret[i] != arg2[i])
ret.bits()[i] = State::Sx;
return ret;
@ -640,7 +640,7 @@ RTLIL::Const RTLIL::const_pmux(const RTLIL::Const &arg1, const RTLIL::Const &arg
if (!arg3.is_onehot())
return RTLIL::Const(State::Sx, arg1.size());
for (int i = 0; i < arg3.size(); i++)
for (auto i = 0; i < arg3.size(); i++)
if (arg3[i] == State::S1)
return RTLIL::Const(std::vector<RTLIL::State>(arg2.begin() + i*arg1.size(), arg2.begin() + (i+1)*arg1.size()));
@ -702,7 +702,7 @@ RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &ar
{
log_assert(arg2.size() == arg1.size());
RTLIL::Const result(RTLIL::State::S0, arg1.size());
for (int i = 0; i < arg1.size(); i++)
for (auto i = 0; i < arg1.size(); i++)
result.bits()[i] = arg1[i] == arg2[i] ? State::S1 : State::S0;
return result;
@ -713,7 +713,7 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar
log_assert(arg2.size() == arg1.size());
log_assert(arg3.size() == arg1.size());
RTLIL::Const result(RTLIL::State::Sx, arg1.size());
for (int i = 0; i < arg1.size(); i++) {
for (auto i = 0; i < arg1.size(); i++) {
if (arg3[i] != State::Sx || arg1[i] == arg2[i])
result.bits()[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i];
}

6
kernel/driver.cc
View file

@ -276,6 +276,8 @@ int main(int argc, char **argv)
options.add_options("developer")
("X,trace", "enable tracing of core data structure changes. for debugging")
("M,randomize-pointers", "will slightly randomize allocated pointer addresses. for debugging")
("autoidx", "start counting autoidx up from <seed>, similar effect to --hash-seed",
cxxopts::value<uint64_t>(), "<idx>")
("A,abort", "will call abort() at the end of the script. for debugging")
("x,experimental", "do not print warnings for the experimental <feature>",
cxxopts::value<std::vector<std::string>>(), "<feature>")
@ -427,6 +429,10 @@ int main(int argc, char **argv)
if (result.count("infile")) {
frontend_files = result["infile"].as<std::vector<std::string>>();
}
if (result.count("autoidx")) {
int idx = result["autoidx"].as<uint64_t>();
autoidx = idx;
}
if (log_errfile == NULL) {
log_files.push_back(stdout);

8
kernel/macc.h
View file

@ -228,6 +228,14 @@ struct Macc
return true;
}
bool is_simple_product()
{
return bit_ports.empty() &&
ports.size() == 1 &&
!ports[0].in_b.empty() &&
!ports[0].do_subtract;
}
Macc(RTLIL::Cell *cell = nullptr)
{
if (cell != nullptr)

8
kernel/mem.cc
View file

@ -1680,8 +1680,6 @@ SigSpec MemWr::decompress_en(const std::vector<int> &swizzle, SigSpec sig) {
return res;
}
using addr_t = MemContents::addr_t;
MemContents::MemContents(Mem *mem) :
MemContents(ceil_log2(mem->size), mem->width)
{
@ -1758,7 +1756,7 @@ bool MemContents::_range_overlaps(std::map<addr_t, RTLIL::Const>::iterator it, a
return !(top1 < begin_addr || top2 < _range_begin(it));
}
std::map<addr_t, RTLIL::Const>::iterator MemContents::_range_at(addr_t addr) const {
std::map<MemContents::addr_t, RTLIL::Const>::iterator MemContents::_range_at(addr_t addr) const {
// allow addr == 1<<_addr_width (which will just return end())
log_assert(addr <= (addr_t)(1<<_addr_width));
// get the first range with base > addr
@ -1786,7 +1784,7 @@ RTLIL::Const MemContents::operator[](addr_t addr) const {
return _default_value;
}
addr_t MemContents::count_range(addr_t begin_addr, addr_t end_addr) const {
MemContents::addr_t MemContents::count_range(addr_t begin_addr, addr_t end_addr) const {
addr_t count = 0;
for(auto it = _range_at(begin_addr); _range_overlaps(it, begin_addr, end_addr); it++) {
auto first = std::max(_range_begin(it), begin_addr);
@ -1829,7 +1827,7 @@ void MemContents::clear_range(addr_t begin_addr, addr_t end_addr) {
_values.erase(begin_it, end_it);
}
std::map<addr_t, RTLIL::Const>::iterator MemContents::_reserve_range(addr_t begin_addr, addr_t end_addr) {
std::map<MemContents::addr_t, RTLIL::Const>::iterator MemContents::_reserve_range(addr_t begin_addr, addr_t end_addr) {
if(begin_addr >= end_addr)
return _values.end(); // need a dummy value to return, end() is cheap
// find the first range containing any addr >= begin_addr - 1

27
kernel/rtlil.cc
View file

@ -381,7 +381,7 @@ int RTLIL::Const::as_int(bool is_signed) const
return ret;
}
size_t RTLIL::Const::get_min_size(bool is_signed) const
int RTLIL::Const::get_min_size(bool is_signed) const
{
if (empty()) return 0;
@ -392,7 +392,7 @@ size_t RTLIL::Const::get_min_size(bool is_signed) const
else
leading_bit = RTLIL::State::S0;
size_t idx = size();
auto idx = size();
while (idx > 0 && (*this)[idx -1] == leading_bit) {
idx--;
}
@ -407,22 +407,22 @@ size_t RTLIL::Const::get_min_size(bool is_signed) const
void RTLIL::Const::compress(bool is_signed)
{
size_t idx = get_min_size(is_signed);
auto idx = get_min_size(is_signed);
bits().erase(bits().begin() + idx, bits().end());
}
std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const
{
size_t size = get_min_size(is_signed);
auto size = get_min_size(is_signed);
if(size == 0 || size > 32)
return std::nullopt;
int32_t ret = 0;
for (size_t i = 0; i < size && i < 32; i++)
for (auto i = 0; i < size && i < 32; i++)
if ((*this)[i] == State::S1)
ret |= 1 << i;
if (is_signed && (*this)[size-1] == State::S1)
for (size_t i = size; i < 32; i++)
for (auto i = size; i < 32; i++)
ret |= 1 << i;
return ret;
}
@ -2148,6 +2148,21 @@ namespace {
check_expected();
return;
}
/*
* Checklist for adding internal cell types
* ========================================
* Things to do right away:
* - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
* - Add to InternalCellChecker::check() in kernel/rtlil.cc
* - Add to techlibs/common/simlib.v
* - Add to techlibs/common/techmap.v
*
* Things to do after finalizing the cell interface:
* - Add support to kernel/satgen.h for the new cell type
* - Add to docs/source/CHAPTER_CellLib.rst (or just add a fixme to the bottom)
* - Maybe add support to the Verilog backend for dumping such cells as expression
*
*/
error(__LINE__);
}
};

2
kernel/rtlil.h
View file

@ -780,7 +780,7 @@ public:
RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;
// find the MSB without redundant leading bits
size_t get_min_size(bool is_signed) const;
int get_min_size(bool is_signed) const;
// compress representation to the minimum required bits
void compress(bool is_signed = false);

2
kernel/yosys.h
View file

@ -32,8 +32,6 @@
//
// This header is very boring. It just defines some general things that
// belong nowhere else and includes the interesting headers.
//
// Find more information in the "guidelines/GettingStarted" file.
#ifndef YOSYS_H