diff --git a/techlibs/intel_le/common/arith_le_map.v b/techlibs/intel_le/common/arith_le_map.v index 75e085520..614e343af 100644 --- a/techlibs/intel_le/common/arith_le_map.v +++ b/techlibs/intel_le/common/arith_le_map.v @@ -40,6 +40,7 @@ generate end else begin MISTRAL_ALUT_ARITH #( .LUT(16'b1010_1010_1010_1010), // Q = A + .sum_lutc_input("cin") ) le_start ( .A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1), .CI(1'b0), @@ -54,7 +55,8 @@ genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice MISTRAL_ALUT_ARITH #( - .LUT(16'b0110_0110_0110_0110) // Q = A ? ~B : B + .LUT(16'b0110_0110_0110_0110), // Q = A ? ~B : B + .sum_lutc_input("cin") ) le_not_i ( .A(BI), .B(BX[i]), .C(1'b0), .D(1'b0), .CI(1'b0), @@ -63,13 +65,10 @@ generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice ); - - - MISTRAL_ALUT_ARITH #( .LUT(16'b1001_0110_1110_1000), // SUM = A xor B xor CI // CARRYi+1 = A and B or A and CI or B and CI - //.sum_lutc_input("cin") + .sum_lutc_input("cin") ) le_i ( .A(AA[i]), .B(BTOADDER[i]), .C(1'b1), .D(1'b1), .CI(LE_CARRY[i]), diff --git a/techlibs/intel_le/common/le_sim.v b/techlibs/intel_le/common/le_sim.v index 8fbcdf2a7..465c7c14b 100644 --- a/techlibs/intel_le/common/le_sim.v +++ b/techlibs/intel_le/common/le_sim.v @@ -77,65 +77,6 @@ // SUMOUT 368 1342 1323 887 927 - 785 - // CARRYOUT 71 1082 1062 866 813 - 1198 - -(* abc9_lut=2, lib_whitebox *) -module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q); - -parameter [63:0] LUT = 64'h0000_0000_0000_0000; - -`ifdef cycloneiv -specify - (A => Q) = 605; - (B => Q) = 583; - (C => Q) = 510; - (D => Q) = 512; - (E => Q) = 400; - (F => Q) = 97; -endspecify -`endif -`ifdef cyclone10gx -specify - (A => Q) = 275; - (B => Q) = 272; - (C => Q) = 175; - (D => Q) = 165; - (E => Q) = 162; - (F => Q) = 53; -endspecify -`endif - -assign Q = LUT >> {F, E, D, C, B, A}; - -endmodule - - -(* abc9_lut=1, lib_whitebox *) -module MISTRAL_ALUT5(input A, B, C, D, E, output Q); - -parameter [31:0] LUT = 32'h0000_0000; - -`ifdef cycloneiv -specify - (A => Q) = 583; - (B => Q) = 510; - (C => Q) = 512; - (D => Q) = 400; - (E => Q) = 97; -endspecify -`endif -`ifdef cyclone10gx -specify - (A => Q) = 272; - (B => Q) = 175; - (C => Q) = 165; - (D => Q) = 162; - (E => Q) = 53; -endspecify -`endif - -assign Q = LUT >> {E, D, C, B, A}; - -endmodule - (* abc9_lut=1, lib_whitebox *) module MISTRAL_ALUT4(input A, B, C, D, output Q); @@ -150,14 +91,6 @@ specify (D => Q) = 97; endspecify `endif -`ifdef cyclone10gx -specify - (A => Q) = 175; - (B => Q) = 165; - (C => Q) = 162; - (D => Q) = 53; -endspecify -`endif assign Q = LUT >> {D, C, B, A}; @@ -176,13 +109,6 @@ specify (C => Q) = 97; endspecify `endif -`ifdef cyclone10gx -specify - (A => Q) = 165; - (B => Q) = 162; - (C => Q) = 53; -endspecify -`endif assign Q = LUT >> {C, B, A}; @@ -200,12 +126,6 @@ specify (B => Q) = 97; endspecify `endif -`ifdef cyclone10gx -specify - (A => Q) = 162; - (B => Q) = 53; -endspecify -`endif assign Q = LUT >> {B, A}; @@ -220,11 +140,6 @@ specify (A => Q) = 97; endspecify `endif -`ifdef cyclone10gx -specify - (A => Q) = 53; -endspecify -`endif assign Q = ~A; @@ -234,7 +149,7 @@ endmodule module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO); parameter LUT = 16'h0000; -//parameter sum_lutc_input = "cin"; +parameter sum_lutc_input = "cin"; `ifdef cycloneiv specify (A => SO) = 1342; @@ -253,8 +168,8 @@ endspecify wire q0, q1; -//assign q0 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A}; -//assign q1 = LUT >> sum_lutc_input == "cin" ? {'b0, CI, B, A}:{'b0, C, B, A}; +//assign q0 = LUT >> sum_lutc_input == "cin" ? {'b0, CI, B, A}:{'b0, C, B, A}; +//assign q1 = LUT >> sum_lutc_input == "cin" ? {D, CI, B, A}:{D, C, B, A}; assign q0 = LUT >> {'b0, CI, B, A}; assign q1 = LUT >> {D, CI, B, A}; @@ -266,281 +181,3 @@ assign CO = q0; endmodule -/* -// A, B, C0, C1, E0, E1, F0, F1: data inputs -// CARRYIN: carry input -// SHAREIN: shared-arithmetic input -// CLK0, CLK1, CLK2: clock inputs -// -// COMB0, COMB1: combinational outputs -// FF0, FF1, FF2, FF3: DFF outputs -// SUM0, SUM1: adder outputs -// CARRYOUT: carry output -// SHAREOUT: shared-arithmetic output -module MISTRAL_ALM( - input A, B, C0, C1, E0, E1, F0, F1, CARRYIN, SHAREIN, // LUT path - input CLK0, CLK1, CLK2, AC0, AC1, // FF path - output COMB0, COMB1, SUM0, SUM1, CARRYOUT, SHAREOUT, - output FF0, FF1, FF2, FF3 -); - -parameter LUT0 = 16'b0000; -parameter LUT1 = 16'b0000; -parameter LUT2 = 16'b0000; -parameter LUT3 = 16'b0000; - -parameter INIT0 = 1'b0; -parameter INIT1 = 1'b0; -parameter INIT2 = 1'b0; -parameter INIT3 = 1'b0; - -parameter C0_MUX = "C0"; -parameter C1_MUX = "C1"; - -parameter F0_MUX = "VCC"; -parameter F1_MUX = "GND"; - -parameter FEEDBACK0 = "FF0"; -parameter FEEDBACK1 = "FF2"; - -parameter ADD_MUX = "LUT"; - -parameter DFF01_DATA_MUX = "COMB"; -parameter DFF23_DATA_MUX = "COMB"; - -parameter DFF0_CLK = "CLK0"; -parameter DFF1_CLK = "CLK0"; -parameter DFF2_CLK = "CLK0"; -parameter DFF3_CLK = "CLK0"; - -parameter DFF0_AC = "AC0"; -parameter DFF1_AC = "AC0"; -parameter DFF2_AC = "AC0"; -parameter DFF3_AC = "AC0"; - -// Feedback muxes from the flip-flop outputs. -wire ff_feedback_mux0, ff_feedback_mux1; - -// C-input muxes which can be set to also use the F-input. -wire c0_input_mux, c1_input_mux; - -// F-input muxes which can be set to a constant to allow LUT5 use. -wire f0_input_mux, f1_input_mux; - -// Adder input muxes to select between shared-arithmetic mode and arithmetic mode. -wire add0_input_mux, add1_input_mux; - -// Combinational-output muxes for LUT #1 and LUT #3 -wire lut1_comb_mux, lut3_comb_mux; - -// Sum-output muxes for LUT #1 and LUT #3 -wire lut1_sum_mux, lut3_sum_mux; - -// DFF data-input muxes -wire dff01_data_mux, dff23_data_mux; - -// DFF clock selectors -wire dff0_clk, dff1_clk, dff2_clk, dff3_clk; - -// DFF asynchronous-clear selectors -wire dff0_ac, dff1_ac, dff2_ac, dff3_ac; - -// LUT, DFF and adder output wires for routing. -wire lut0_out, lut1a_out, lut1b_out, lut2_out, lut3a_out, lut3b_out; -wire dff0_out, dff1_out, dff2_out, dff3_out; -wire add0_sum, add1_sum, add0_carry, add1_carry; - -generate - if (FEEDBACK0 === "FF0") - assign ff_feedback_mux0 = dff0_out; - else if (FEEDBACK0 === "FF1") - assign ff_feedback_mux0 = dff1_out; - else - $error("Invalid FEEDBACK0 setting!"); - - if (FEEDBACK1 == "FF2") - assign ff_feedback_mux1 = dff2_out; - else if (FEEDBACK1 == "FF3") - assign ff_feedback_mux1 = dff3_out; - else - $error("Invalid FEEDBACK1 setting!"); - - if (C0_MUX === "C0") - assign c0_input_mux = C0; - else if (C0_MUX === "F1") - assign c0_input_mux = F1; - else if (C0_MUX === "FEEDBACK1") - assign c0_input_mux = ff_feedback_mux1; - else - $error("Invalid C0_MUX setting!"); - - if (C1_MUX === "C1") - assign c1_input_mux = C1; - else if (C1_MUX === "F0") - assign c1_input_mux = F0; - else if (C1_MUX === "FEEDBACK0") - assign c1_input_mux = ff_feedback_mux0; - else - $error("Invalid C1_MUX setting!"); - - // F0 == VCC is LUT5 - // F0 == F0 is LUT6 - // F0 == FEEDBACK is unknown - if (F0_MUX === "VCC") - assign f0_input_mux = 1'b1; - else if (F0_MUX === "F0") - assign f0_input_mux = F0; - else if (F0_MUX === "FEEDBACK0") - assign f0_input_mux = ff_feedback_mux0; - else - $error("Invalid F0_MUX setting!"); - - // F1 == GND is LUT5 - // F1 == F1 is LUT6 - // F1 == FEEDBACK is unknown - if (F1_MUX === "GND") - assign f1_input_mux = 1'b0; - else if (F1_MUX === "F1") - assign f1_input_mux = F1; - else if (F1_MUX === "FEEDBACK1") - assign f1_input_mux = ff_feedback_mux1; - else - $error("Invalid F1_MUX setting!"); - - if (ADD_MUX === "LUT") begin - assign add0_input_mux = ~lut1_sum_mux; - assign add1_input_mux = ~lut3_sum_mux; - end else if (ADD_MUX === "SHARE") begin - assign add0_input_mux = SHAREIN; - assign add1_input_mux = lut1_comb_mux; - end else - $error("Invalid ADD_MUX setting!"); - - if (DFF01_DATA_MUX === "COMB") - assign dff01_data_mux = COMB0; - else if (DFF01_DATA_MUX === "SUM") - assign dff01_data_mux = SUM0; - else - $error("Invalid DFF01_DATA_MUX setting!"); - - if (DFF23_DATA_MUX === "COMB") - assign dff23_data_mux = COMB0; - else if (DFF23_DATA_MUX === "SUM") - assign dff23_data_mux = SUM0; - else - $error("Invalid DFF23_DATA_MUX setting!"); - - if (DFF0_CLK === "CLK0") - assign dff0_clk = CLK0; - else if (DFF0_CLK === "CLK1") - assign dff0_clk = CLK1; - else if (DFF0_CLK === "CLK2") - assign dff0_clk = CLK2; - else - $error("Invalid DFF0_CLK setting!"); - - if (DFF1_CLK === "CLK0") - assign dff1_clk = CLK0; - else if (DFF1_CLK === "CLK1") - assign dff1_clk = CLK1; - else if (DFF1_CLK === "CLK2") - assign dff1_clk = CLK2; - else - $error("Invalid DFF1_CLK setting!"); - - if (DFF2_CLK === "CLK0") - assign dff2_clk = CLK0; - else if (DFF2_CLK === "CLK1") - assign dff2_clk = CLK1; - else if (DFF2_CLK === "CLK2") - assign dff2_clk = CLK2; - else - $error("Invalid DFF2_CLK setting!"); - - if (DFF3_CLK === "CLK0") - assign dff3_clk = CLK0; - else if (DFF3_CLK === "CLK1") - assign dff3_clk = CLK1; - else if (DFF3_CLK === "CLK2") - assign dff3_clk = CLK2; - else - $error("Invalid DFF3_CLK setting!"); - - if (DFF0_AC === "AC0") - assign dff0_ac = AC0; - else if (DFF0_AC === "AC1") - assign dff0_ac = AC1; - else - $error("Invalid DFF0_AC setting!"); - - if (DFF1_AC === "AC0") - assign dff1_ac = AC0; - else if (DFF1_AC === "AC1") - assign dff1_ac = AC1; - else - $error("Invalid DFF1_AC setting!"); - - if (DFF2_AC === "AC0") - assign dff2_ac = AC0; - else if (DFF2_AC === "AC1") - assign dff2_ac = AC1; - else - $error("Invalid DFF2_AC setting!"); - - if (DFF3_AC === "AC0") - assign dff3_ac = AC0; - else if (DFF3_AC === "AC1") - assign dff3_ac = AC1; - else - $error("Invalid DFF3_AC setting!"); - -endgenerate - -// F0 on the Quartus diagram -MISTRAL_ALUT4 #(.LUT(LUT0)) lut0 (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut0_out)); - -// F2 on the Quartus diagram -MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_comb (.A(A), .B(B), .C(C0), .D(c1_input_mux), .Q(lut1_comb_mux)); -MISTRAL_ALUT4 #(.LUT(LUT1)) lut1_sum (.A(A), .B(B), .C(C0), .D(E0), .Q(lut1_sum_mux)); - -// F1 on the Quartus diagram -MISTRAL_ALUT4 #(.LUT(LUT2)) lut2 (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut2_out)); - -// F3 on the Quartus diagram -MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_comb (.A(A), .B(B), .C(C1), .D(c0_input_mux), .Q(lut3_comb_mux)); -MISTRAL_ALUT4 #(.LUT(LUT3)) lut3_sum (.A(A), .B(B), .C(C1), .D(E1), .Q(lut3_sum_mux)); - -MISTRAL_FF #(.INIT(INIT0)) dff0 (.D(dff01_data_mux), .CLK(dff0_clk), .ACn(dff0_ac), .Q(dff0_out)); -MISTRAL_FF #(.INIT(INIT1)) dff1 (.D(dff01_data_mux), .CLK(dff1_clk), .ACn(dff1_ac), .Q(dff1_out)); -MISTRAL_FF #(.INIT(INIT2)) dff2 (.D(dff23_data_mux), .CLK(dff2_clk), .ACn(dff2_ac), .Q(dff2_out)); -MISTRAL_FF #(.INIT(INIT3)) dff3 (.D(dff23_data_mux), .CLK(dff3_clk), .ACn(dff3_ac), .Q(dff3_out)); - -// Adders -assign {add0_carry, add0_sum} = CARRYIN + lut0_out + lut1_sum_mux; -assign {add1_carry, add1_sum} = add0_carry + lut2_out + lut3_sum_mux; - -// COMBOUT outputs on the Quartus diagram -assign COMB0 = E0 ? (f0_input_mux ? lut3_comb_mux : lut1_comb_mux) - : (f0_input_mux ? lut2_out : lut0_out); - -assign COMB1 = E1 ? (f1_input_mux ? lut3_comb_mux : lut1_comb_mux) - : (f1_input_mux ? lut2_out : lut0_out); - -// SUMOUT output on the Quartus diagram -assign SUM0 = add0_sum; -assign SUM1 = add1_sum; - -// COUT output on the Quartus diagram -assign CARRYOUT = add1_carry; - -// SHAREOUT output on the Quartus diagram -assign SHAREOUT = lut3_comb_mux; - -// REGOUT outputs on the Quartus diagram -assign FF0 = dff0_out; -assign FF1 = dff1_out; -assign FF2 = dff2_out; -assign FF3 = dff3_out; - -endmodule -*/ diff --git a/techlibs/intel_le/common/quartus_rename.v b/techlibs/intel_le/common/quartus_rename.v index 15497b010..00449d522 100644 --- a/techlibs/intel_le/common/quartus_rename.v +++ b/techlibs/intel_le/common/quartus_rename.v @@ -1,4 +1,4 @@ -`ifdef cycloneiv +`ifdef cycloneiv `define LCELL cycloneiv_lcell_comb `define MAC cycloneiv_mac `define MLAB cycloneiv_mlab_cell @@ -29,24 +29,24 @@ endmodule module MISTRAL_ALUT4(input A, B, C, D, output Q); parameter [15:0] LUT = 16'h0000; - -`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q)); +parameter sum_lutc_input = "datac"; +`LCELL #(.lut_mask(LUT),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q)); endmodule module MISTRAL_ALUT3(input A, B, C, output Q); parameter [7:0] LUT = 8'h00; - -`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q)); +parameter sum_lutc_input = "datac"; +`LCELL #(.lut_mask({2{LUT}}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q)); endmodule module MISTRAL_ALUT2(input A, B, output Q); parameter [3:0] LUT = 4'h0; - -`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q)); +parameter sum_lutc_input = "datac"; +`LCELL #(.lut_mask({4{LUT}}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q)); endmodule @@ -60,8 +60,8 @@ endmodule module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO); parameter LUT = 16'h0000; - -`LCELL #(.lut_mask({16'h0, LUT})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .sumout(SO), .cout(CO)); +parameter sum_lutc_input = "datac"; +`LCELL #(.lut_mask({LUT}),.sum_lutc_input(sum_lutc_input)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .sumout(SO), .cout(CO)); endmodule diff --git a/techlibs/intel_le/cycloneiv/cells_sim.v b/techlibs/intel_le/cycloneiv/cells_sim.v index 0f7432fc7..48b2651b0 100644 --- a/techlibs/intel_le/cycloneiv/cells_sim.v +++ b/techlibs/intel_le/cycloneiv/cells_sim.v @@ -48,67 +48,7 @@ module cycloneiv_lcell_comb parameter lpm_type = "cycloneiv_lcell_comb"; parameter sum_lutc_input = "datac"; - reg cout_tmp; - reg combout_tmp; - reg [1:0] isum_lutc_input; - - wire dataa_in; - wire datab_in; - wire datac_in; - wire datad_in; - wire cin_in; - - // Simulation model of 4-input LUT - function lut4; - input [15:0] mask; - input dataa, datab, datac, datad; - reg [7:0] s3; - reg [3:0] s2; - reg [1:0] s1; - begin - s3 = datad ? mask[15:8] : mask[7:0]; - s2 = datac ? s3[7:4] : s3[3:0]; - s1 = datab ? s2[3:2] : s2[1:0]; - lut4 = dataa ? s1[1] : s1[0]; - end - endfunction // lut4 - - - initial - begin - if (sum_lutc_input == "datac") - isum_lutc_input = 0; - else if (sum_lutc_input == "cin") - isum_lutc_input = 1; - else - begin - $display ("Error: Invalid sum_lutc_input specified\n"); - $display ("Time: %0t Instance: %m", $time); - isum_lutc_input = 2; - end - - end - - always @(datad_in or datac_in or datab_in or dataa_in or cin_in) - begin - - if (isum_lutc_input == 0) // datac - begin - combout_tmp = lut4(lut_mask, dataa_in, datab_in, - datac_in, datad_in); - end - else if (isum_lutc_input == 1) // cin - begin - combout_tmp = lut4(lut_mask, dataa_in, datab_in, - cin_in, datad_in); - end - - cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0); - end - - and (combout, combout_tmp, 1'b1) ; - and (cout, cout_tmp, 1'b1) ; endmodule // cycloneiv_lcell_comb