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Correct and more test

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Kelvin Chung 2025-04-10 00:01:50 +01:00
parent a0dabf9203
commit 414dc85573
2 changed files with 24 additions and 1 deletions
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23
tests/techmap/constmap.ys
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@ -16,6 +16,7 @@ design -reset
read_verilog -lib << EOT
module const_cell(O);
parameter value=0;
output O;
endmodule
EOT
@ -33,8 +34,30 @@ endmodule
EOT
constmap -cell const_cell O value
select -assert-count 2 t:const_cell
select -assert-count 1 r:value=16
select -assert-count 1 r:value=32
select -assert-count 1 test/out1 %ci* r:value=16 %i
select -assert-count 1 test/out2 %ci* r:value=32 %i
select -assert-count 1 t:const_cell r:value=16 %i
select -assert-count 1 t:const_cell r:value=32 %i
design -reset
read_verilog << EOT
module test();
wire [31:0] in;
wire [31:0] out1;
wire [31:0] out2;
assign out1 = in + 16;
assign out2 = in + 32;
endmodule
EOT
constmap -cell const_cell O value
select -assert-count 1 t:const_cell r:value=16 %i
select -assert-count 1 t:const_cell r:value=32 %i