diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc
index 59bffbeb6..8f3235991 100644
--- a/passes/techmap/constmap.cc
+++ b/passes/techmap/constmap.cc
@@ -77,6 +77,6 @@ struct ConstmapPass : public Pass {
 			module->rewrite_sigspecs(constmap_worker);
 		}
 	}
-} HilomapPass;
+} ConstmapPass;
 
 PRIVATE_NAMESPACE_END
diff --git a/tests/techmap/constmap.ys b/tests/techmap/constmap.ys
index 2854f2e57..fbaca7662 100644
--- a/tests/techmap/constmap.ys
+++ b/tests/techmap/constmap.ys
@@ -16,6 +16,7 @@ design -reset
 
 read_verilog -lib << EOT
 module const_cell(O);
+parameter value=0;
 output O;
 endmodule
 EOT
@@ -33,8 +34,30 @@ endmodule
 EOT
 
 constmap -cell const_cell O value
+
 select -assert-count 2 t:const_cell
 select -assert-count 1 r:value=16
 select -assert-count 1 r:value=32
 select -assert-count 1 test/out1 %ci* r:value=16 %i
 select -assert-count 1 test/out2 %ci* r:value=32 %i
+select -assert-count 1 t:const_cell r:value=16 %i
+select -assert-count 1 t:const_cell r:value=32 %i
+
+design -reset
+
+read_verilog << EOT
+
+module test();
+  wire [31:0] in;
+  wire [31:0] out1;
+  wire [31:0] out2;
+  assign out1 = in + 16;
+  assign out2 = in + 32;
+endmodule
+
+EOT
+
+constmap -cell const_cell O value
+
+select -assert-count 1 t:const_cell r:value=16 %i
+select -assert-count 1 t:const_cell r:value=32 %i