From 4062825a9ed94a449e8162559ea89b1ce0ed9d10 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Tue, 28 May 2024 01:47:46 -0700 Subject: [PATCH] Disable Liberty support, add blackbox Verilog module, and add attribute parsing into Yosys Liberty parser --- frontends/liberty/liberty.cc | 6 ++++++ frontends/verific/verific.cc | 3 +++ 2 files changed, 9 insertions(+) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index cadbcaee6..a8d437b75 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -591,6 +591,12 @@ struct LibertyFrontend : public Frontend { for (auto node : cell->children) { + if (node->id == "area") + module->attributes["\\area"] = node->value; + + if (node->id == "cell_leakage_power") + module->attributes["\\LeakagePower"] = node->value; + if (node->id == "pin" && node->args.size() == 1) { LibertyAst *dir = node->find("direction"); if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal")) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 91526ea23..2840dfaf9 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3459,6 +3459,9 @@ struct VerificPass : public Pass { veri_file::AddFileExtMode(".svh", veri_file::SYSTEM_VERILOG); veri_file::AddFileExtMode(".svp", veri_file::SYSTEM_VERILOG); veri_file::AddFileExtMode(".h", veri_file::SYSTEM_VERILOG); + + // Add blackbox modules + veri_file::AddVFile("preqorsor/data/blackboxes.v"); // Select analyze function auto analyze_function = (args[argidx] == "-auto_discover") ? hdl_file_sort::AnalyzeDiscoveredFiles : hdl_file_sort::AnalyzeSortedFiles;