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Merge branch 'YosysHQ:main' into abc-custom-flow

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Philippe Sauter 2024-11-11 23:09:29 +01:00 • committed by GitHub
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291 changed files with 18481 additions and 11714 deletions
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1
passes/cmds/Makefile.inc
View file

@ -31,7 +31,6 @@ OBJS += passes/cmds/cover.o
OBJS += passes/cmds/trace.o
OBJS += passes/cmds/plugin.o
OBJS += passes/cmds/check.o
OBJS += passes/cmds/qwp.o
OBJS += passes/cmds/edgetypes.o
OBJS += passes/cmds/portlist.o
OBJS += passes/cmds/chformal.o

2
passes/cmds/bugpoint.cc
View file

@ -354,7 +354,7 @@ struct BugpointPass : public Pass {
for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
auto &mask = it2->priority_mask;
if (GetSize(mask) > i) {
mask.bits.erase(mask.bits.begin() + i);
mask.bits().erase(mask.bits().begin() + i);
}
}
return design_copy;

91
passes/cmds/check.cc
View file

@ -59,6 +59,12 @@ struct CheckPass : public Pass {
log(" -assert\n");
log(" produce a runtime error if any problems are found in the current design\n");
log("\n");
log(" -force-detailed-loop-check\n");
log(" for the detection of combinatorial loops, use a detailed connectivity\n");
log(" model for all internal cells for which it is available. This disables\n");
log(" falling back to a simpler overapproximating model for those cells for\n");
log(" which the detailed model is expected costly.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
@ -68,6 +74,8 @@ struct CheckPass : public Pass {
bool mapped = false;
bool allow_tbuf = false;
bool assert_mode = false;
bool force_detailed_loop_check = false;
bool suggest_detail = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
@ -91,6 +99,10 @@ struct CheckPass : public Pass {
assert_mode = true;
continue;
}
if (args[argidx] == "-force-detailed-loop-check") {
force_detailed_loop_check = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -154,9 +166,10 @@ struct CheckPass : public Pass {
struct CircuitEdgesDatabase : AbstractCellEdgesDatabase {
TopoSort<std::pair<RTLIL::IdString, int>> &topo;
SigMap sigmap;
bool force_detail;
CircuitEdgesDatabase(TopoSort<std::pair<RTLIL::IdString, int>> &topo, SigMap &sigmap)
: topo(topo), sigmap(sigmap) {}
CircuitEdgesDatabase(TopoSort<std::pair<RTLIL::IdString, int>> &topo, SigMap &sigmap, bool force_detail)
: topo(topo), sigmap(sigmap), force_detail(force_detail) {}
void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit,
RTLIL::IdString to_port, int to_bit, int) override {
@ -171,10 +184,41 @@ struct CheckPass : public Pass {
topo.edge(std::make_pair(from.wire->name, from.offset), std::make_pair(to.wire->name, to.offset));
}
bool add_edges_from_cell(Cell *cell) {
if (AbstractCellEdgesDatabase::add_edges_from_cell(cell))
bool detail_costly(Cell *cell) {
// Only those cell types for which the edge data can expode quadratically
// in port widths are those for us to check.
if (!cell->type.in(
ID($add), ID($sub),
ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
return false;
int in_widths = 0, out_widths = 0;
for (auto &conn : cell->connections()) {
if (cell->input(conn.first))
in_widths += conn.second.size();
if (cell->output(conn.first))
out_widths += conn.second.size();
}
const int threshold = 1024;
// if the multiplication may overflow we will catch it here
if (in_widths + out_widths >= threshold)
return true;
if (in_widths * out_widths >= threshold)
return true;
return false;
}
bool add_edges_from_cell(Cell *cell) {
if (force_detail || !detail_costly(cell)) {
if (AbstractCellEdgesDatabase::add_edges_from_cell(cell))
return true;
}
// We don't have accurate cell edges, do the fallback of all input-output pairs
for (auto &conn : cell->connections()) {
if (cell->input(conn.first))
@ -189,12 +233,15 @@ struct CheckPass : public Pass {
topo.edge(std::make_pair(cell->name, -1),
std::make_pair(bit.wire->name, bit.offset));
}
return true;
// Return false to signify the fallback
return false;
}
};
CircuitEdgesDatabase edges_db(topo, sigmap);
CircuitEdgesDatabase edges_db(topo, sigmap, force_detailed_loop_check);
pool<Cell *> coarsened_cells;
for (auto cell : module->cells())
{
if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
@ -225,8 +272,10 @@ struct CheckPass : public Pass {
}
if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
|| RTLIL::builtin_ff_cell_types().count(cell->type))
edges_db.add_edges_from_cell(cell);
|| RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (!edges_db.add_edges_from_cell(cell))
coarsened_cells.insert(cell);
}
}
pool<SigBit> init_bits;
@ -284,10 +333,10 @@ struct CheckPass : public Pass {
for (auto &loop : topo.loops) {
string message = stringf("found logic loop in module %s:\n", log_id(module));
// `loop` only contains wire bits, or an occassional special helper node for cells for
// which we have done the edges fallback. The cell and its ports that led to an edge is
// an information we need to recover now. For that we need to have the previous wire bit
// of the loop at hand.
// `loop` only contains wire bits, or an occasional special helper node for cells for
// which we have done the edges fallback. The cell and its ports that led to an edge are
// a piece of information we need to recover now. For that we need to have the previous
// wire bit of the loop at hand.
SigBit prev;
for (auto it = loop.rbegin(); it != loop.rend(); it++)
if (it->second != -1) { // skip the fallback helper nodes
@ -316,10 +365,10 @@ struct CheckPass : public Pass {
SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit];
if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT)
message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit,
message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit,
log_id(to_port), to_bit);
if (nhits == HITS_LIMIT)
message += " ...\n";
message += " ...\n";
}
};
@ -334,9 +383,16 @@ struct CheckPass : public Pass {
std::string src_attr = driver->get_src_attribute();
driver_src = stringf(" source: %s", src_attr.c_str());
}
message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str());
MatchingEdgePrinter printer(message, sigmap, prev, bit);
printer.add_edges_from_cell(driver);
if (!coarsened_cells.count(driver)) {
MatchingEdgePrinter printer(message, sigmap, prev, bit);
printer.add_edges_from_cell(driver);
} else {
message += " (cell's internal connectivity overapproximated; loop may be a false positive)\n";
suggest_detail = true;
}
if (wire->name.isPublic()) {
std::string wire_src;
@ -376,6 +432,9 @@ struct CheckPass : public Pass {
log("Found and reported %d problems.\n", counter);
if (suggest_detail)
log("Consider re-running with '-force-detailed-loop-check' to rule out false positives.\n");
if (assert_mode && counter > 0)
log_error("Found %d problems in 'check -assert'.\n", counter);
}

2
passes/cmds/clean_zerowidth.cc
View file

@ -160,7 +160,7 @@ struct CleanZeroWidthPass : public Pass {
memwr.address = State::S0;
Const priority_mask;
for (auto x : swizzle) {
priority_mask.bits.push_back(memwr.priority_mask.bits[x]);
priority_mask.bits().push_back(memwr.priority_mask[x]);
}
memwr.priority_mask = priority_mask;
swizzle.push_back(i);

2
passes/cmds/dft_tag.cc
View file

@ -883,7 +883,7 @@ struct DftTagWorker {
{
if (sig_a.is_fully_const()) {
auto const_val = sig_a.as_const();
for (auto &bit : const_val.bits)
for (auto bit : const_val)
bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit;
return const_val;
}

2
passes/cmds/example_dt.cc
View file

@ -27,6 +27,8 @@ struct ExampleDtPass : public Pass
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log("TODO: add help message\n");
log("\n");
}

3
passes/cmds/logger.cc
View file

@ -162,7 +162,8 @@ struct LoggerPass : public Pass {
log_cmd_error("Number of expected messages must be higher then 0 !\n");
if (type=="error" && count!=1)
log_cmd_error("Expected error message occurrences must be 1 !\n");
log("Added regex '%s' for warnings to expected %s list.\n", pattern.c_str(), type.c_str());
log("Added regex '%s' to expected %s messages list.\n",
pattern.c_str(), type.c_str());
try {
if (type == "error")
log_expect_error[pattern] = LogExpectedItem(YS_REGEX_COMPILE(pattern), count);

4
passes/cmds/printattrs.cc
View file

@ -40,12 +40,12 @@ struct PrintAttrsPass : public Pass {
}
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags == RTLIL::CONST_FLAG_STRING)
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str());
else
log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override

871
passes/cmds/qwp.cc
View file

@ -1,871 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#undef LOG_MATRICES
#undef PYPLOT_EDGES
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static uint32_t xorshift32_state;
static double xorshift32()
{
xorshift32_state ^= xorshift32_state << 13;
xorshift32_state ^= xorshift32_state >> 17;
xorshift32_state ^= xorshift32_state << 5;
return (xorshift32_state % 1000000) / 1e6;
}
struct QwpConfig
{
bool ltr;
bool alpha;
bool verbose;
double grid;
std::ofstream dump_file;
QwpConfig() {
ltr = false;
alpha = false;
verbose = false;
grid = 1.0 / 16;
}
};
struct QwpWorker
{
QwpConfig &config;
Module *module;
char direction;
struct Node {
Cell *cell;
bool tied, alt_tied;
// pos = position in current direction
// alt_pos = position in the other direction
double pos, alt_pos;
Node() {
cell = nullptr;
tied = false;
pos = xorshift32();
alt_tied = false;
alt_pos = xorshift32();
}
void tie(double v) {
tied = true;
pos = v;
}
void alt_tie(double v) {
alt_tied = true;
alt_pos = v;
}
void swap_alt() {
std::swap(tied, alt_tied);
std::swap(pos, alt_pos);
}
void proj_left(double midpos) {
cell = nullptr;
tie(pos > midpos ? midpos : pos);
}
void proj_right(double midpos) {
cell = nullptr;
tie(pos < midpos ? midpos : pos);
}
};
vector<Node> nodes;
dict<pair<int, int>, double> edges;
dict<Cell*, int> cell_to_node;
// worker state variables
double midpos;
double radius;
double alt_midpos;
double alt_radius;
QwpWorker(QwpConfig &config, Module *module, char direction = 'x') : config(config), module(module), direction(direction)
{
log_assert(direction == 'x' || direction == 'y');
}
void load_module()
{
log_assert(direction == 'x');
SigMap sigmap(module);
dict<SigBit, pool<int>> bits_to_nodes;
if (config.ltr || config.alpha)
{
dict<Wire*, double> alpha_inputs, alpha_outputs;
if (config.alpha)
{
dict<string, Wire*> alpha_order;
for (auto wire : module->wires()) {
if (wire->port_input || wire->port_output)
alpha_order[wire->name.str()] = wire;
}
alpha_order.sort();
for (auto &it : alpha_order) {
if (it.second->port_input) {
int idx = GetSize(alpha_inputs);
alpha_inputs[it.second] = idx + 0.5;
}
if (it.second->port_output) {
int idx = GetSize(alpha_outputs);
alpha_outputs[it.second] = idx + 0.5;
}
}
}
for (auto wire : module->wires())
{
if (!wire->port_input && !wire->port_output)
continue;
int idx = GetSize(nodes);
nodes.push_back(Node());
if (config.ltr) {
if (wire->port_input)
nodes[idx].tie(0.0);
else
nodes[idx].tie(1.0);
}
if (config.alpha) {
if (wire->port_input)
nodes[idx].alt_tie(alpha_inputs.at(wire) / GetSize(alpha_inputs));
else
nodes[idx].alt_tie(alpha_outputs.at(wire) / GetSize(alpha_outputs));
}
for (auto bit : sigmap(wire))
bits_to_nodes[bit].insert(idx);
}
}
for (auto cell : module->selected_cells())
{
log_assert(cell_to_node.count(cell) == 0);
int idx = GetSize(nodes);
nodes.push_back(Node());
cell_to_node[cell] = GetSize(nodes);
nodes[idx].cell = cell;
for (auto &conn : cell->connections())
for (auto bit : sigmap(conn.second))
bits_to_nodes[bit].insert(idx);
}
for (auto &it : bits_to_nodes)
{
if (GetSize(it.second) > 100)
continue;
for (int idx1 : it.second)
for (int idx2 : it.second)
if (idx1 < idx2)
edges[pair<int, int>(idx1, idx2)] += 1.0 / GetSize(it.second);
}
}
void solve(bool alt_mode = false)
{
// A := constraint_matrix
// y := constraint_rhs_vector
//
// AA = A' * A
// Ay = A' * y
//
// M := [AA Ay]
if (config.verbose)
log("> System size: %d^2\n", GetSize(nodes));
// Row major order
int N = GetSize(nodes), N1 = N+1;
vector<double> M(N * N1);
if (config.verbose)
log("> Edge constraints: %d\n", GetSize(edges));
// Edge constraints:
// A[i,:] := [ 0 0 .... 0 weight 0 ... 0 -weight 0 ... 0 0], y[i] := 0
//
// i.e. nonzero columns in A[i,:] at the two node indices.
for (auto &edge : edges)
{
int idx1 = edge.first.first;
int idx2 = edge.first.second;
double weight = edge.second * (1.0 + xorshift32() * 1e-3);
M[idx1 + idx1*N1] += weight * weight;
M[idx2 + idx2*N1] += weight * weight;
M[idx1 + idx2*N1] += -weight * weight;
M[idx2 + idx1*N1] += -weight * weight;
}
if (config.verbose)
log("> Node constraints: %d\n", GetSize(nodes));
// Node constraints:
// A[i,:] := [ 0 0 .... 0 weight 0 ... 0 0], y[i] := weight * pos
//
// i.e. nonzero column in A[i,:] at the node index
//
// "tied" nodes have a large weight, pinning them in position. Untied
// nodes have a small weight, giving then a tiny preference to stay at
// the current position, making sure that AA never is singular.
for (int idx = 0; idx < GetSize(nodes); idx++)
{
auto &node = nodes[idx];
double rhs = (alt_mode ? node.alt_pos : node.pos);
double weight = 1e-3;
if (alt_mode ? node.alt_tied : node.tied)
weight = 1e3;
weight *= (1.0 + xorshift32() * 1e-3);
M[idx + idx*N1] += weight * weight;
M[N + idx*N1] += rhs * weight * weight;
}
#ifdef LOG_MATRICES
log("\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N+1; j++)
log(" %10.2e", M[(N+1)*i + j]);
log("\n");
}
#endif
if (config.verbose)
log("> Solving\n");
// Solve "AA*x = Ay"
// (least squares fit for "A*x = y")
//
// Using gaussian elimination to get M := [Id x]
vector<int> pivot_cache;
vector<int> queue;
for (int i = 0; i < N; i++)
queue.push_back(i);
// gaussian elimination
for (int i = 0; i < N; i++)
{
if (config.verbose && N > 15 && ((i+1) % (N/15)) == 0)
log("> Solved %d%%: %d/%d\n", (100*(i+1))/N, i+1, N);
// find best row
int best_row = queue.front();
int best_row_queue_idx = 0;
double best_row_absval = 0;
for (int k = 0; k < GetSize(queue); k++) {
int row = queue[k];
double absval = fabs(M[i + row*N1]);
if (absval > best_row_absval) {
best_row = row;
best_row_queue_idx = k;
best_row_absval = absval;
}
}
int row = best_row;
pivot_cache.push_back(row);
queue[best_row_queue_idx] = queue.back();
queue.pop_back();
// normalize row
for (int k = i+1; k < N1; k++)
M[k + row*N1] /= M[i + row*N1];
M[i + row*N1] = 1.0;
// elimination
for (int other_row : queue) {
double d = M[i + other_row*N1];
for (int k = i+1; k < N1; k++)
M[k + other_row*N1] -= d*M[k + row*N1];
M[i + other_row*N1] = 0.0;
}
}
if (config.verbose)
log("> Solved\n");
log_assert(queue.empty());
log_assert(GetSize(pivot_cache) == N);
// back substitution
for (int i = N-1; i >= 0; i--)
for (int j = i+1; j < N; j++)
{
int row = pivot_cache[i];
int other_row = pivot_cache[j];
M[N + row*N1] -= M[j + row*N1] * M[N + other_row*N1];
M[j + row*N1] = 0.0;
}
#ifdef LOG_MATRICES
log("\n");
for (int i = 0; i < N; i++) {
for (int j = 0; j < N+1; j++)
log(" %10.2e", M[(N+1)*i + j]);
log("\n");
}
#endif
if (config.verbose)
log("> Update nodes\n");
// update node positions
for (int i = 0; i < N; i++)
{
double v = M[(N+1)*i + N];
double c = alt_mode ? alt_midpos : midpos;
double r = alt_mode ? alt_radius : radius;
if (std::isfinite(v)) {
v = min(v, c+r);
v = max(v, c-r);
} else {
v = c;
}
if (alt_mode) {
if (!nodes[i].alt_tied)
nodes[i].alt_pos = v;
} else {
if (!nodes[i].tied)
nodes[i].pos = v;
}
}
}
void log_cell_coordinates(int indent, bool log_all_nodes = false)
{
for (auto &node : nodes)
{
if (node.cell == nullptr && !log_all_nodes)
continue;
for (int i = 0; i < indent; i++)
log(" ");
if (direction == 'x')
log("X=%.2f, Y=%.2f", node.pos, node.alt_pos);
else
log("X=%.2f, Y=%.2f", node.alt_pos, node.pos);
if (node.tied)
log(" [%c-tied]", direction);
if (node.alt_tied)
log(" [%c-tied]", direction == 'x' ? 'y' : 'x');
if (node.cell != nullptr)
log(" %s (%s)", log_id(node.cell), log_id(node.cell->type));
else
log(" (none)");
log("\n");
}
}
void dump_svg(const pool<int> *green_nodes = nullptr, double median = -1)
{
double x_center = direction == 'x' ? midpos : alt_midpos;
double y_center = direction == 'y' ? midpos : alt_midpos;
double x_radius = direction == 'x' ? radius : alt_radius;
double y_radius = direction == 'y' ? radius : alt_radius;
config.dump_file << stringf("<svg height=\"240\" width=\"470\">\n");
config.dump_file << stringf("<rect x=\"0\" y=\"0\" width=\"470\" height=\"240\" style=\"fill:rgb(250,250,200);\" />\n");
config.dump_file << stringf("<rect x=\"20\" y=\"20\" width=\"200\" height=\"200\" style=\"fill:rgb(200,200,200);\" />\n");
config.dump_file << stringf("<rect x=\"250\" y=\"20\" width=\"200\" height=\"200\" style=\"fill:rgb(200,200,200);\" />\n");
double win_x = 250 + 200 * (direction == 'x' ? midpos - radius : alt_midpos - alt_radius);
double win_y = 20 + 200 * (direction == 'y' ? midpos - radius : alt_midpos - alt_radius);
double win_w = 200 * (direction == 'x' ? 2*radius : 2*alt_radius);
double win_h = 200 * (direction == 'y' ? 2*radius : 2*alt_radius);
config.dump_file << stringf("<rect x=\"%.2f\" y=\"%.2f\" width=\"%.2f\" height=\"%.2f\" "
"style=\"stroke:rgb(0,0,0);stroke-width:1;fill:none\" />\n", win_x, win_y, win_w, win_h);
if (median >= 0)
{
double x1 = 20.0, x2 = 220.0, y1 = 20.0, y2 = 220.0;
if (direction == 'x')
x1 = x2 = 120 + 100 * (median - x_center) / x_radius;
else
y1 = y2 = 120 + 100 * (median - y_center) / y_radius;
config.dump_file << stringf("<line x1=\"%.2f\" y1=\"%.2f\" x2=\"%.2f\" y2=\"%.2f\" "
"style=\"stroke:rgb(150,0,150);stroke-width:1\" />\n", x1, y1, x2, y2);
}
for (auto &edge : edges)
{
auto &node1 = nodes[edge.first.first];
auto &node2 = nodes[edge.first.second];
double x1 = direction == 'x' ? node1.pos : node1.alt_pos;
double y1 = direction == 'y' ? node1.pos : node1.alt_pos;
double x2 = direction == 'x' ? node2.pos : node2.alt_pos;
double y2 = direction == 'y' ? node2.pos : node2.alt_pos;
x1 = 120 + 100 * (x1 - x_center) / x_radius;
y1 = 120 + 100 * (y1 - y_center) / y_radius;
x2 = 120 + 100 * (x2 - x_center) / x_radius;
y2 = 120 + 100 * (y2 - y_center) / y_radius;
config.dump_file << stringf("<line x1=\"%.2f\" y1=\"%.2f\" x2=\"%.2f\" y2=\"%.2f\" "
"style=\"stroke:rgb(0,0,0);stroke-width:1\" />\n", x1, y1, x2, y2);
}
for (int i = 0; i < GetSize(nodes); i++)
{
auto &node = nodes[i];
double x = direction == 'x' ? node.pos : node.alt_pos;
double y = direction == 'y' ? node.pos : node.alt_pos;
x = 120 + 100 * (x - x_center) / x_radius;
y = 120 + 100 * (y - y_center) / y_radius;
const char *color = node.cell == nullptr ? "blue" : "red";
if (green_nodes != nullptr && green_nodes->count(i))
color = "green";
config.dump_file << stringf("<circle cx=\"%.2f\" cy=\"%.2f\" r=\"3\" fill=\"%s\"/>\n", x, y, color);
}
config.dump_file << stringf("</svg>\n");
}
void run_worker(int indent)
{
int count_cells = 0;
for (auto &node : nodes)
if (node.cell != nullptr)
count_cells++;
for (int i = 0; i < indent; i++)
log(" ");
string range_str;
if (direction == 'x')
range_str = stringf("X=%.2f:%.2f, Y=%.2f:%.2f",
midpos - radius, midpos + radius,
alt_midpos - alt_radius, alt_midpos + alt_radius);
else
range_str = stringf("X=%.2f:%.2f, Y=%.2f:%.2f",
alt_midpos - alt_radius, alt_midpos + alt_radius,
midpos - radius, midpos + radius);
log("%c-qwp on %s with %d cells, %d nodes, and %d edges.\n", direction,
range_str.c_str(), count_cells, GetSize(nodes), GetSize(edges));
solve();
solve(true);
// detect median position and check for break condition
vector<pair<double, int>> sorted_pos;
for (int i = 0; i < GetSize(nodes); i++)
if (nodes[i].cell != nullptr)
sorted_pos.push_back(pair<double, int>(nodes[i].pos, i));
std::sort(sorted_pos.begin(), sorted_pos.end());
int median_sidx = GetSize(sorted_pos)/2;
double median = sorted_pos[median_sidx].first;
double left_scale = radius / (median - (midpos - radius));
double right_scale = radius / ((midpos + radius) - median);
if (config.dump_file.is_open())
{
config.dump_file << stringf("<h4>LSQ %c-Solution for %s:</h4>\n", direction, range_str.c_str());
pool<int> green_nodes;
for (int i = 0; i < median_sidx; i++)
green_nodes.insert(sorted_pos[i].second);
dump_svg(&green_nodes, median);
}
for (auto &node : nodes)
{
double rel_pos = node.pos - median;
if (rel_pos < 0) {
node.pos = midpos + left_scale*rel_pos;
if (std::isfinite(node.pos)) {
node.pos = min(node.pos, midpos);
node.pos = max(node.pos, midpos - radius);
} else
node.pos = midpos - radius/2;
} else {
node.pos = midpos + right_scale*rel_pos;
if (std::isfinite(node.pos)) {
node.pos = max(node.pos, midpos);
node.pos = min(node.pos, midpos + radius);
} else
node.pos = midpos + radius/2;
}
}
if (GetSize(sorted_pos) < 2 || (2*radius <= config.grid && 2*alt_radius <= config.grid)) {
log_cell_coordinates(indent + 1);
return;
}
// create child workers
char child_direction = direction == 'x' ? 'y' : 'x';
QwpWorker left_worker(config, module, child_direction);
QwpWorker right_worker(config, module, child_direction);
// duplicate nodes into child workers
dict<int, int> left_nodes, right_nodes;
for (int k = 0; k < GetSize(sorted_pos); k++)
{
int i = sorted_pos[k].second;
if (k < median_sidx) {
left_nodes[i] = GetSize(left_worker.nodes);
left_worker.nodes.push_back(nodes[i]);
if (left_worker.nodes.back().pos > midpos)
left_worker.nodes.back().pos = midpos;
left_worker.nodes.back().swap_alt();
} else {
right_nodes[i] = GetSize(right_worker.nodes);
right_worker.nodes.push_back(nodes[i]);
if (right_worker.nodes.back().pos < midpos)
right_worker.nodes.back().pos = midpos;
right_worker.nodes.back().swap_alt();
}
}
// duplicate edges into child workers, project nodes as needed
for (auto &edge : edges)
{
int idx1 = edge.first.first;
int idx2 = edge.first.second;
double weight = edge.second;
if (nodes[idx1].cell == nullptr && nodes[idx2].cell == nullptr)
continue;
int left_idx1 = left_nodes.count(idx1) ? left_nodes.at(idx1) : -1;
int left_idx2 = left_nodes.count(idx2) ? left_nodes.at(idx2) : -1;
int right_idx1 = right_nodes.count(idx1) ? right_nodes.at(idx1) : -1;
int right_idx2 = right_nodes.count(idx2) ? right_nodes.at(idx2) : -1;
if (left_idx1 >= 0 && left_worker.nodes[left_idx1].cell && left_idx2 < 0) {
left_idx2 = left_nodes[idx2] = GetSize(left_worker.nodes);
left_worker.nodes.push_back(nodes[idx2]);
left_worker.nodes.back().proj_left(midpos);
left_worker.nodes.back().swap_alt();
} else
if (left_idx2 >= 0 && left_worker.nodes[left_idx2].cell && left_idx1 < 0) {
left_idx1 = left_nodes[idx1] = GetSize(left_worker.nodes);
left_worker.nodes.push_back(nodes[idx1]);
left_worker.nodes.back().proj_left(midpos);
left_worker.nodes.back().swap_alt();
}
if (right_idx1 >= 0 && right_worker.nodes[right_idx1].cell && right_idx2 < 0) {
right_idx2 = right_nodes[idx2] = GetSize(right_worker.nodes);
right_worker.nodes.push_back(nodes[idx2]);
right_worker.nodes.back().proj_right(midpos);
right_worker.nodes.back().swap_alt();
} else
if (right_idx2 >= 0 && right_worker.nodes[right_idx2].cell && right_idx1 < 0) {
right_idx1 = right_nodes[idx1] = GetSize(right_worker.nodes);
right_worker.nodes.push_back(nodes[idx1]);
right_worker.nodes.back().proj_right(midpos);
right_worker.nodes.back().swap_alt();
}
if (left_idx1 >= 0 && left_idx2 >= 0)
left_worker.edges[pair<int, int>(left_idx1, left_idx2)] += weight;
if (right_idx1 >= 0 && right_idx2 >= 0)
right_worker.edges[pair<int, int>(right_idx1, right_idx2)] += weight;
}
// run child workers
left_worker.midpos = right_worker.midpos = alt_midpos;
left_worker.radius = right_worker.radius = alt_radius;
left_worker.alt_midpos = midpos - radius/2;
right_worker.alt_midpos = midpos + radius/2;
left_worker.alt_radius = right_worker.alt_radius = radius/2;
left_worker.run_worker(indent+1);
right_worker.run_worker(indent+1);
// re-integrate results
for (auto &it : left_nodes)
if (left_worker.nodes[it.second].cell != nullptr) {
nodes[it.first].pos = left_worker.nodes[it.second].alt_pos;
nodes[it.first].alt_pos = left_worker.nodes[it.second].pos;
}
for (auto &it : right_nodes)
if (right_worker.nodes[it.second].cell != nullptr) {
nodes[it.first].pos = right_worker.nodes[it.second].alt_pos;
nodes[it.first].alt_pos = right_worker.nodes[it.second].pos;
}
if (config.dump_file.is_open()) {
config.dump_file << stringf("<h4>Final %c-Solution for %s:</h4>\n", direction, range_str.c_str());
dump_svg();
}
}
void histogram(const vector<double> &values)
{
if (values.empty()) {
log("no data\n");
return;
}
double min_value = values.front();
double max_value = values.front();
for (auto &v : values) {
min_value = min(min_value, v);
max_value = max(max_value, v);
}
if (fabs(max_value - min_value) < 0.001) {
log("all values in range %f .. %f\n", min_value, max_value);
return;
}
vector<int> buckets(60);
int max_bucket_val = 0;
for (auto &v : values) {
int idx = min(int(GetSize(buckets) * (v - min_value) / (max_value - min_value)), GetSize(buckets)-1);
max_bucket_val = max(max_bucket_val, ++buckets.at(idx));
}
for (int i = 4; i >= 0; i--) {
for (int k = 0; k < GetSize(buckets); k++) {
int v = 10 * buckets[k] / max_bucket_val;
if (v >= 2*i+1)
log(v == 2*i+1 ? "." : ":");
else
log(i == 0 ? (buckets[k] > 0 ? "," : "_") : " ");
}
log("\n");
}
log("%-30f%30f\n", min_value, max_value);
}
void run()
{
log("\n");
log("Running qwp on module %s..\n", log_id(module));
if (config.dump_file.is_open())
config.dump_file << stringf("<h3>QWP protocol for module %s:</h3>\n", log_id(module));
load_module();
midpos = 0.5;
radius = 0.5;
alt_midpos = 0.5;
alt_radius = 0.5;
run_worker(1);
for (auto &node : nodes)
if (node.cell != nullptr)
node.cell->attributes[ID::qwp_position] = stringf("%f %f", node.pos, node.alt_pos);
vector<double> edge_lengths;
vector<double> weighted_edge_lengths;
double total_edge_length = 0;
double total_weighted_edge_length = 0;
for (auto &edge : edges)
{
auto &node1 = nodes[edge.first.first];
auto &node2 = nodes[edge.first.second];
double distance = sqrt(pow(node1.pos - node2.pos, 2) + pow(node1.alt_pos - node2.alt_pos, 2));
double weighted_distance = distance * edge.second;
edge_lengths.push_back(distance);
weighted_edge_lengths.push_back(weighted_distance);
total_edge_length += distance;
total_weighted_edge_length += weighted_distance;
}
log("\n");
log("Summary for module %s:\n", log_id(module));
log("Number of edges: %d\n", GetSize(edges));
log("Total edge length: %f\n", total_edge_length);
log("Total weighted edge length: %f\n", total_weighted_edge_length);
log("\n");
log("Histogram over edge lengths:\n");
histogram(edge_lengths);
log("\n");
log("Histogram over weighted edge lengths:\n");
histogram(weighted_edge_lengths);
}
};
struct QwpPass : public Pass {
QwpPass() : Pass("qwp", "quadratic wirelength placer") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" qwp [options] [selection]\n");
log("\n");
log("This command runs quadratic wirelength placement on the selected modules and\n");
log("annotates the cells in the design with 'qwp_position' attributes.\n");
log("\n");
log(" -ltr\n");
log(" Add left-to-right constraints: constrain all inputs on the left border\n");
log(" outputs to the right border.\n");
log("\n");
log(" -alpha\n");
log(" Add constraints for inputs/outputs to be placed in alphanumerical\n");
log(" order along the y-axis (top-to-bottom).\n");
log("\n");
log(" -grid N\n");
log(" Number of grid divisions in x- and y-direction. (default=16)\n");
log("\n");
log(" -dump <html_file_name>\n");
log(" Dump a protocol of the placement algorithm to the html file.\n");
log("\n");
log(" -v\n");
log(" Verbose solver output for profiling or debugging\n");
log("\n");
log("Note: This implementation of a quadratic wirelength placer uses exact\n");
log("dense matrix operations. It is only a toy-placer for small circuits.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
QwpConfig config;
xorshift32_state = 123456789;
log_header(design, "Executing QWP pass (quadratic wirelength placer).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-ltr") {
config.ltr = true;
continue;
}
if (args[argidx] == "-alpha") {
config.alpha = true;
continue;
}
if (args[argidx] == "-v") {
config.verbose = true;
continue;
}
if (args[argidx] == "-grid" && argidx+1 < args.size()) {
config.grid = 1.0 / atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-dump" && argidx+1 < args.size()) {
config.dump_file.open(args[++argidx], std::ofstream::trunc);
yosys_output_files.insert(args[argidx]);
continue;
}
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
{
QwpWorker worker(config, module);
worker.run();
#ifdef PYPLOT_EDGES
log("\n");
log("plt.figure(figsize=(10, 10));\n");
for (auto &edge : worker.edges) {
log("plt.plot([%.2f, %.2f], [%.2f, %.2f], \"r-\");\n",
worker.nodes[edge.first.first].pos,
worker.nodes[edge.first.second].pos,
worker.nodes[edge.first.first].alt_pos,
worker.nodes[edge.first.second].alt_pos);
}
for (auto &node : worker.nodes) {
const char *style = node.cell != nullptr ? "ko" : "ks";
log("plt.plot([%.2f], [%.2f], \"%s\");\n", node.pos, node.alt_pos, style);
}
#endif
}
}
} QwpPass;
PRIVATE_NAMESPACE_END

32
passes/cmds/select.cc
View file

@ -876,9 +876,20 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
sel.selected_members[mod->name].insert(cell->name);
} else
if (arg_memb.compare(0, 2, "t:") == 0) {
for (auto cell : mod->cells())
if (match_ids(cell->type, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(cell->name);
if (arg_memb.compare(2, 1, "@") == 0) {
std::string set_name = RTLIL::escape_id(arg_memb.substr(3));
if (!design->selection_vars.count(set_name))
log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str());
auto &muster = design->selection_vars[set_name];
for (auto cell : mod->cells())
if (muster.selected_modules.count(cell->type))
sel.selected_members[mod->name].insert(cell->name);
} else {
for (auto cell : mod->cells())
if (match_ids(cell->type, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(cell->name);
}
} else
if (arg_memb.compare(0, 2, "p:") == 0) {
for (auto &it : mod->processes)
@ -1030,7 +1041,7 @@ struct SelectPass : public Pass {
log(" select [ -add | -del | -set <name> ] {-read <filename> | <selection>}\n");
log(" select [ -unset <name> ]\n");
log(" select [ <assert_option> ] {-read <filename> | <selection>}\n");
log(" select [ -list | -write <filename> | -count | -clear ]\n");
log(" select [ -list | -list-mod | -write <filename> | -count | -clear ]\n");
log(" select -module <modname>\n");
log("\n");
log("Most commands use the list of currently selected objects to determine which part\n");
@ -1164,6 +1175,9 @@ struct SelectPass : public Pass {
log(" t:<pattern>\n");
log(" all cells with a type matching the given pattern\n");
log("\n");
log(" t:@<name>\n");
log(" all cells with a type matching a module in the saved selection <name>\n");
log("\n");
log(" p:<pattern>\n");
log(" all processes with a name matching the given pattern\n");
log("\n");
@ -1263,6 +1277,7 @@ struct SelectPass : public Pass {
bool clear_mode = false;
bool none_mode = false;
bool list_mode = false;
bool list_mod_mode = false;
bool count_mode = false;
bool got_module = false;
bool assert_none = false;
@ -1324,6 +1339,11 @@ struct SelectPass : public Pass {
list_mode = true;
continue;
}
if (arg == "-list-mod") {
list_mode = true;
list_mod_mode = true;
continue;
}
if (arg == "-write" && argidx+1 < args.size()) {
write_file = args[++argidx];
continue;
@ -1402,7 +1422,7 @@ struct SelectPass : public Pass {
log_cmd_error("Options %s can not be combined.\n", common_flagset);
if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally)
log_cmd_error("Options -list, -write and -count can not be combined with %s.\n", common_flagset);
log_cmd_error("Options -list, -list-mod, -write and -count can not be combined with %s.\n", common_flagset);
if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || !unset_name.empty() || common_flagset_tally))
log_cmd_error("Option -set can not be combined with -list, -write, -count, -unset, %s.\n", common_flagset);
@ -1453,7 +1473,7 @@ struct SelectPass : public Pass {
{
if (sel->selected_whole_module(mod->name) && list_mode)
log("%s\n", id2cstr(mod->name));
if (sel->selected_module(mod->name)) {
if (sel->selected_module(mod->name) && !list_mod_mode) {
for (auto wire : mod->wires())
if (sel->selected_member(mod->name, wire->name))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(wire->name))

8
passes/cmds/setundef.cc
View file

@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
{
for (auto *cell : module->selected_cells()) {
for (auto &parameter : cell->parameters) {
for (auto &bit : parameter.second.bits) {
for (auto bit : parameter.second) {
if (bit > RTLIL::State::S1)
bit = worker.next_bit();
}
@ -390,12 +390,12 @@ struct SetundefPass : public Pass {
for (auto wire : initwires)
{
Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
for (int i = 0; i < GetSize(wire); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (initval[i] == State::Sx && ffbits.count(bit)) {
initval[i] = worker.next_bit();
initval.bits()[i] = worker.next_bit();
ffbits.erase(bit);
}
}
@ -421,7 +421,7 @@ struct SetundefPass : public Pass {
continue;
Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) {
wire->attributes.erase(ID::init);

2
passes/cmds/splitnets.cc
View file

@ -77,7 +77,7 @@ struct SplitnetsWorker
if (it != wire->attributes.end()) {
Const old_init = it->second, new_init;
for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
new_init.bits().push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init);
}

1
passes/cmds/stat.cc
View file

@ -48,7 +48,6 @@ struct statdata_t
double sequential_area = 0;
string tech;
std::map<RTLIL::IdString, int> techinfo;
std::map<RTLIL::IdString, unsigned int, RTLIL::sort_by_id_str> num_cells_by_type;
std::set<RTLIL::IdString> unknown_cell_area;

12
passes/cmds/xprop.cc
View file

@ -827,9 +827,9 @@ struct XpropWorker
auto init_q_is_1 = init_q;
auto init_q_is_x = init_q;
for (auto &bit : init_q_is_1)
for (auto &bit : init_q_is_1.bits())
bit = bit == State::S1 ? State::S1 : State::S0;
for (auto &bit : init_q_is_x)
for (auto &bit : init_q_is_x.bits())
bit = bit == State::Sx ? State::S1 : State::S0;
initvals.remove_init(sig_q);
@ -864,14 +864,14 @@ struct XpropWorker
auto init_q_is_x = init_q;
if (ff.is_anyinit) {
for (auto &bit : init_q_is_1)
for (auto &bit : init_q_is_1.bits())
bit = State::Sx;
for (auto &bit : init_q_is_x)
for (auto &bit : init_q_is_x.bits())
bit = State::S0;
} else {
for (auto &bit : init_q_is_1)
for (auto &bit : init_q_is_1.bits())
bit = bit == State::S1 ? State::S1 : State::S0;
for (auto &bit : init_q_is_x)
for (auto &bit : init_q_is_x.bits())
bit = bit == State::Sx ? State::S1 : State::S0;
}

4
passes/fsm/fsm_extract.cc
View file

@ -168,10 +168,10 @@ undef_bit_in_next_state:
ctrl_in_bit_indices[ctrl_in[i]] = i;
for (auto &it : ctrl_in_bit_indices)
if (tr.ctrl_in.bits.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
if (tr.ctrl_in.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
for (auto &dc_bit : exclusive_ctrls.at(it.first))
if (ctrl_in_bit_indices.count(dc_bit))
tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
tr.ctrl_in.bits().at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits);
if (state_in >= 0)

30
passes/fsm/fsm_map.cc
View file

@ -30,11 +30,11 @@ PRIVATE_NAMESPACE_BEGIN
static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern)
{
log_assert(GetSize(super_pattern.bits) == GetSize(sub_pattern.bits));
for (int i = 0; i < GetSize(super_pattern.bits); i++)
if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) {
if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) {
if (super_pattern.bits[i] != sub_pattern.bits[i])
log_assert(GetSize(super_pattern) == GetSize(sub_pattern));
for (int i = 0; i < GetSize(super_pattern); i++)
if (sub_pattern[i] == RTLIL::State::S0 || sub_pattern[i] == RTLIL::State::S1) {
if (super_pattern[i] == RTLIL::State::S0 || super_pattern[i] == RTLIL::State::S1) {
if (super_pattern[i] != sub_pattern[i])
return false;
} else
return false;
@ -54,10 +54,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Const pattern = it.first;
RTLIL::SigSpec eq_sig_a, eq_sig_b, or_sig;
for (size_t j = 0; j < pattern.bits.size(); j++)
if (pattern.bits[j] == RTLIL::State::S0 || pattern.bits[j] == RTLIL::State::S1) {
for (size_t j = 0; j < pattern.size(); j++)
if (pattern[j] == RTLIL::State::S0 || pattern[j] == RTLIL::State::S1) {
eq_sig_a.append(ctrl_in.extract(j, 1));
eq_sig_b.append(RTLIL::SigSpec(pattern.bits[j]));
eq_sig_b.append(RTLIL::SigSpec(pattern[j]));
}
for (int in_state : it.second)
@ -176,7 +176,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
state_dff->type = ID($adff);
state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits)
for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits())
if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0;
state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
@ -198,10 +198,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
RTLIL::Const state = fsm_data.state_table[i];
RTLIL::SigSpec sig_a, sig_b;
for (size_t j = 0; j < state.bits.size(); j++)
if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
for (size_t j = 0; j < state.size(); j++)
if (state[j] == RTLIL::State::S0 || state[j] == RTLIL::State::S1) {
sig_a.append(RTLIL::SigSpec(state_wire, j));
sig_b.append(RTLIL::SigSpec(state.bits[j]));
sig_b.append(RTLIL::SigSpec(state[j]));
}
if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
@ -261,8 +261,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
RTLIL::Const state = fsm_data.state_table[i];
int bit_idx = -1;
for (size_t j = 0; j < state.bits.size(); j++)
if (state.bits[j] == RTLIL::State::S1)
for (size_t j = 0; j < state.size(); j++)
if (state[j] == RTLIL::State::S1)
bit_idx = j;
if (bit_idx >= 0)
next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
@ -306,7 +306,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
fullstate_cache.insert(j);
for (auto &tr : fsm_data.transition_table) {
if (tr.ctrl_out.bits[i] == RTLIL::State::S1)
if (tr.ctrl_out[i] == RTLIL::State::S1)
pattern_cache[tr.ctrl_in].insert(tr.state_in);
else
fullstate_cache.erase(tr.state_in);

22
passes/fsm/fsm_opt.cc
View file

@ -106,11 +106,11 @@ struct FsmOpt
for (int i = 0; i < ctrl_in.size(); i++) {
RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1);
if (ctrl_bit.is_fully_const()) {
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit)
if (tr.ctrl_in[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in[i]) != ctrl_bit)
goto delete_this_transition;
continue;
}
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1)
if (tr.ctrl_in[i] <= RTLIL::State::S1)
ctrl_in_used[i] = true;
}
new_transition_table.push_back(tr);
@ -169,8 +169,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits[i];
RTLIL::State &sj = tr.ctrl_in.bits[j];
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_in.bits()[j];
if (si > RTLIL::State::S1)
si = sj;
@ -207,8 +207,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits[i];
RTLIL::State &sj = tr.ctrl_out.bits[j];
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_out.bits()[j];
if (si > RTLIL::State::S1 || si == sj) {
RTLIL::SigSpec tmp(tr.ctrl_in);
@ -232,22 +232,22 @@ struct FsmOpt
for (auto &pattern : set)
{
if (pattern.bits[bit] > RTLIL::State::S1) {
if (pattern[bit] > RTLIL::State::S1) {
new_set.insert(pattern);
continue;
}
RTLIL::Const other_pattern = pattern;
if (pattern.bits[bit] == RTLIL::State::S1)
other_pattern.bits[bit] = RTLIL::State::S0;
if (pattern[bit] == RTLIL::State::S1)
other_pattern.bits()[bit] = RTLIL::State::S0;
else
other_pattern.bits[bit] = RTLIL::State::S1;
other_pattern.bits()[bit] = RTLIL::State::S1;
if (set.count(other_pattern) > 0) {
log(" Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern),
tr.state_in, tr.state_out, log_signal(tr.ctrl_out));
other_pattern.bits[bit] = RTLIL::State::Sa;
other_pattern.bits()[bit] = RTLIL::State::Sa;
new_set.insert(other_pattern);
did_something = true;
continue;

6
passes/fsm/fsm_recode.cc
View file

@ -43,8 +43,8 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
fprintf(f, "set_fsm_encoding {");
for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
fprintf(f, " s%d=2#", i);
for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--)
fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
for (int j = GetSize(fsm_data.state_table[i])-1; j >= 0; j--)
fprintf(f, "%c", fsm_data.state_table[i][j] == RTLIL::State::S1 ? '1' : '0');
}
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
prefix, RTLIL::unescape_id(name).c_str(),
@ -105,7 +105,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
if (encoding == "one-hot") {
new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits);
new_code.bits[state_idx] = RTLIL::State::S1;
new_code.bits()[state_idx] = RTLIL::State::S1;
} else
if (encoding == "binary") {
new_code = RTLIL::Const(state_idx, fsm_data.state_bits);

26
passes/fsm/fsmdata.h
View file

@ -48,8 +48,8 @@ struct FsmData
cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) {
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
std::vector<RTLIL::State> &bits_state = state_table[i].bits;
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits();
std::vector<RTLIL::State> &bits_state = state_table[i].bits();
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
}
@ -57,16 +57,16 @@ struct FsmData
cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
for (int i = 0; i < int(transition_table.size()); i++)
{
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits();
transition_t &tr = transition_table[i];
RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);
std::vector<RTLIL::State> &bits_state_in = const_state_in.bits;
std::vector<RTLIL::State> &bits_state_out = const_state_out.bits;
std::vector<RTLIL::State> &bits_state_in = const_state_in.bits();
std::vector<RTLIL::State> &bits_state_out = const_state_out.bits();
std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits;
std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits;
std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits();
std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits();
// append lsb first
bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());
@ -97,23 +97,23 @@ struct FsmData
for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code;
int off_begin = i*state_bits, off_end = off_begin + state_bits;
state_code.bits.insert(state_code.bits.begin(), state_table.bits.begin()+off_begin, state_table.bits.begin()+off_end);
state_code.bits().insert(state_code.bits().begin(), state_table.begin()+off_begin, state_table.begin()+off_end);
this->state_table.push_back(state_code);
}
for (int i = 0; i < trans_num; i++)
{
auto off_ctrl_out = trans_table.bits.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
auto off_ctrl_out = trans_table.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
auto off_state_out = off_ctrl_out + num_outputs;
auto off_ctrl_in = off_state_out + state_num_log2;
auto off_state_in = off_ctrl_in + num_inputs;
auto off_end = off_state_in + state_num_log2;
RTLIL::Const state_in, state_out, ctrl_in, ctrl_out;
ctrl_out.bits.insert(state_in.bits.begin(), off_ctrl_out, off_state_out);
state_out.bits.insert(state_out.bits.begin(), off_state_out, off_ctrl_in);
ctrl_in.bits.insert(ctrl_in.bits.begin(), off_ctrl_in, off_state_in);
state_in.bits.insert(state_in.bits.begin(), off_state_in, off_end);
ctrl_out.bits().insert(ctrl_out.bits().begin(), off_ctrl_out, off_state_out);
state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in);
ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in);
state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end);
transition_t tr;
tr.state_in = state_in.as_int();

4
passes/hierarchy/hierarchy.cc
View file

@ -219,7 +219,7 @@ struct IFExpander
const RTLIL::SigSpec &conn_signals)
{
// Check if the connected wire is a potential interface in the parent module
std::string interface_name_str = conn_signals.bits()[0].wire->name.str();
std::string interface_name_str = conn_signals[0].wire->name.str();
// Strip the prefix '$dummywireforinterface' from the dummy wire to get the name
interface_name_str.replace(0,23,"");
interface_name_str = "\\" + interface_name_str;
@ -289,7 +289,7 @@ struct IFExpander
return;
// If the connection looks like an interface, handle it.
const auto &bits = conn_signals.bits();
const auto &bits = conn_signals;
if (bits.size() == 1 && bits[0].wire->get_bool_attribute(ID::is_interface))
on_interface(submodule, conn_name, conn_signals);
}

8
passes/hierarchy/submod.cc
View file

@ -79,7 +79,7 @@ struct SubmodWorker
flag_wire(c.wire, create, set_int_used, set_ext_driven, set_ext_used);
if (set_int_driven)
for (int i = c.offset; i < c.offset+c.width; i++) {
wire_flags.at(c.wire).is_int_driven[i] = State::S1;
wire_flags.at(c.wire).is_int_driven.bits()[i] = State::S1;
flag_found_something = true;
}
}
@ -185,8 +185,8 @@ struct SubmodWorker
auto it = sig[i].wire->attributes.find(ID::init);
if (it != sig[i].wire->attributes.end()) {
auto jt = new_wire->attributes.insert(std::make_pair(ID::init, Const(State::Sx, GetSize(sig)))).first;
jt->second[i] = it->second[sig[i].offset];
it->second[sig[i].offset] = State::Sx;
jt->second.bits()[i] = it->second[sig[i].offset];
it->second.bits()[sig[i].offset] = State::Sx;
}
}
}
@ -279,7 +279,7 @@ struct SubmodWorker
for (auto cell : module->cells())
{
if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].bits.size() == 0) {
if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].size() == 0) {
cell->attributes.erase(ID::submod);
continue;
}

10
passes/memory/memory_bram.cc
View file

@ -848,9 +848,9 @@ grow_read_ports:;
for (int i = 0; i < mem.width; i++)
if (shuffle_map[i] != -1) {
module->connect(port.data[shuffle_map[i]], new_data[i]);
new_init_value[i] = port.init_value[shuffle_map[i]];
new_arst_value[i] = port.arst_value[shuffle_map[i]];
new_srst_value[i] = port.srst_value[shuffle_map[i]];
new_init_value.bits()[i] = port.init_value[shuffle_map[i]];
new_arst_value.bits()[i] = port.arst_value[shuffle_map[i]];
new_srst_value.bits()[i] = port.srst_value[shuffle_map[i]];
}
port.data = new_data;
port.init_value = new_init_value;
@ -887,9 +887,9 @@ grow_read_ports:;
for (int i = 0; i < init_size; i++)
for (int j = 0; j < bram.dbits; j++)
if (init_offset+i < GetSize(initdata) && init_offset+i >= 0)
initparam[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j];
initparam.bits()[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j];
else
initparam[i*bram.dbits+j] = State::Sx;
initparam.bits()[i*bram.dbits+j] = State::Sx;
c->setParam(ID::INIT, initparam);
}

10
passes/memory/memory_libmap.cc
View file

@ -1019,7 +1019,7 @@ void MemMapping::handle_priority() {
}
bool is_all_zero(const Const &val) {
for (auto bit: val.bits)
for (auto bit: val)
if (bit == State::S1)
return false;
return true;
@ -1913,7 +1913,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(val.bits[bit.bit]);
hw_val.push_back(val[bit.bit]);
}
}
if (pdef.rdinitval == ResetValKind::NoUndef)
@ -1926,7 +1926,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(rport.arst_value.bits[bit.bit]);
hw_val.push_back(rport.arst_value[bit.bit]);
}
}
if (pdef.rdarstval == ResetValKind::NoUndef)
@ -1939,7 +1939,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(rport.srst_value.bits[bit.bit]);
hw_val.push_back(rport.srst_value[bit.bit]);
}
}
if (pdef.rdsrstval == ResetValKind::NoUndef)
@ -2103,7 +2103,7 @@ void MemMapping::emit(const MemConfig &cfg) {
if (hwa & 1 << i)
addr += 1 << hw_addr_swizzle[i];
if (addr >= mem.start_offset && addr < mem.start_offset + mem.size)
initval.push_back(init_data.bits[(addr - mem.start_offset) * mem.width + bit.bit]);
initval.push_back(init_data[(addr - mem.start_offset) * mem.width + bit.bit]);
else
initval.push_back(State::Sx);
}

4
passes/memory/memory_share.cc
View file

@ -60,11 +60,11 @@ struct MemoryShareWorker
bool merge_rst_value(Mem &mem, Const &res, int wide_log2, const Const &src1, int sub1, const Const &src2, int sub2) {
res = Const(State::Sx, mem.width << wide_log2);
for (int i = 0; i < GetSize(src1); i++)
res[i + sub1 * mem.width] = src1[i];
res.bits()[i + sub1 * mem.width] = src1[i];
for (int i = 0; i < GetSize(src2); i++) {
if (src2[i] == State::Sx)
continue;
auto &dst = res[i + sub2 * mem.width];
auto &dst = res.bits()[i + sub2 * mem.width];
if (dst == src2[i])
continue;
if (dst != State::Sx)

8
passes/opt/muxpack.cc
View file

@ -94,7 +94,7 @@ struct ExclusiveDatabase
SigSpec nonconst_sig;
pool<Const> const_values;
for (auto bit : sig.bits()) {
for (auto bit : sig) {
auto it = sig_cmp_prev.find(bit);
if (it == sig_cmp_prev.end())
return false;
@ -152,7 +152,7 @@ struct MuxpackWorker
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (sig_chain_next.count(a_sig))
for (auto a_bit : a_sig.bits())
for (auto a_bit : a_sig)
sigbit_with_non_chain_users.insert(a_bit);
else {
sig_chain_next[a_sig] = cell;
@ -161,7 +161,7 @@ struct MuxpackWorker
if (!b_sig.empty()) {
if (sig_chain_next.count(b_sig))
for (auto b_bit : b_sig.bits())
for (auto b_bit : b_sig)
sigbit_with_non_chain_users.insert(b_bit);
else {
sig_chain_next[b_sig] = cell;
@ -201,7 +201,7 @@ struct MuxpackWorker
}
else log_abort();
for (auto bit : a_sig.bits())
for (auto bit : a_sig)
if (sigbit_with_non_chain_users.count(bit))
goto start_cell;

10
passes/opt/opt_clean.cc
View file

@ -393,8 +393,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
RTLIL::Const &val = it2->second;
SigSpec sig = assign_map(wire);
for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++)
if (val.bits[i] != State::Sx)
init_bits[sig[i]] = val.bits[i];
if (val[i] != State::Sx)
init_bits[sig[i]] = val[i];
wire->attributes.erase(it2);
}
}
@ -406,7 +406,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
for (int i = 0; i < wire->width; i++) {
auto it = init_bits.find(RTLIL::SigBit(wire, i));
if (it != init_bits.end()) {
val.bits[i] = it->second;
val.bits()[i] = it->second;
found = true;
}
}
@ -425,7 +425,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (wire->attributes.count(ID::init))
initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire))
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
wire->attributes.erase(ID::init);
@ -457,7 +457,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (s1[i] != s2[i]) {
if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
s2[i] = initval[i];
initval[i] = State::Sx;
initval.bits()[i] = State::Sx;
}
new_conn.first.append(s1[i]);
new_conn.second.append(s2[i]);

8
passes/opt/opt_dff.cc
View file

@ -361,9 +361,9 @@ struct OptDffWorker
bool failed = false;
for (int i = 0; i < ff.width; i++) {
if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral)
val_arst.bits.push_back(State::S0);
val_arst.bits().push_back(State::S0);
else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral)
val_arst.bits.push_back(State::S1);
val_arst.bits().push_back(State::S1);
else
failed = true;
}
@ -626,7 +626,7 @@ struct OptDffWorker
groups[resets].push_back(i);
} else
remaining_indices.push_back(i);
val_srst.bits.push_back(reset_val);
val_srst.bits().push_back(reset_val);
}
for (auto &it : groups) {
@ -634,7 +634,7 @@ struct OptDffWorker
new_ff.val_srst = Const();
for (int i = 0; i < new_ff.width; i++) {
int j = it.second[i];
new_ff.val_srst.bits.push_back(val_srst[j]);
new_ff.val_srst.bits().push_back(val_srst[j]);
}
ctrl_t srst = combine_resets(it.first, ff.is_fine);

16
passes/opt/opt_expr.cc
View file

@ -83,7 +83,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
auto cursor = initbits.find(bit);
if (cursor != initbits.end()) {
revisit_initwires.insert(cursor->second.first);
val[i] = cursor->second.second;
val.bits()[i] = cursor->second.second;
}
}
@ -101,7 +101,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (SigBit(initval[i]) == sig[i])
initval[i] = State::Sx;
initval.bits()[i] = State::Sx;
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
@ -351,21 +351,21 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative)
bool all_bits_one = true;
bool last_bit_one = true;
if (GetSize(value.bits) < 1)
if (GetSize(value) < 1)
return false;
if (GetSize(value.bits) == 1) {
if (value.bits[0] != State::S1)
if (GetSize(value) == 1) {
if (value[0] != State::S1)
return false;
if (is_signed)
is_negative = true;
return true;
}
for (int i = 0; i < GetSize(value.bits); i++) {
if (value.bits[i] != State::S1)
for (int i = 0; i < GetSize(value); i++) {
if (value[i] != State::S1)
all_bits_one = false;
if (value.bits[i] != (i ? State::S0 : State::S1))
if (value[i] != (i ? State::S0 : State::S1))
last_bit_one = false;
}

8
passes/opt/opt_ffinv.cc
View file

@ -98,7 +98,7 @@ struct OptFfInvWorker
Const mask = lut->getParam(ID::LUT);
Const new_mask;
for (int j = 0; j < (1 << GetSize(sig_a)); j++) {
new_mask.bits.push_back(mask.bits[j ^ flip_mask]);
new_mask.bits().push_back(mask[j ^ flip_mask]);
}
if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
module->connect(lut->getPort(ID::Y), ff.sig_q);
@ -180,10 +180,10 @@ struct OptFfInvWorker
Const mask = d_lut->getParam(ID::LUT);
Const new_mask;
for (int i = 0; i < GetSize(mask); i++) {
if (mask.bits[i] == State::S0)
new_mask.bits.push_back(State::S1);
if (mask[i] == State::S0)
new_mask.bits().push_back(State::S1);
else
new_mask.bits.push_back(State::S0);
new_mask.bits().push_back(State::S0);
}
d_lut->setParam(ID::LUT, new_mask);
if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {

2
passes/opt/opt_lut.cc
View file

@ -493,7 +493,7 @@ struct OptLutWorker
eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
}
eval_inputs[lutA_output] = evaluate_lut(lutA, eval_inputs);
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
lutM_new_table.bits()[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
}
log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());

4
passes/opt/opt_lut_ins.cc
View file

@ -78,7 +78,7 @@ struct OptLutInsPass : public Pass {
if (techname == "") {
if (cell->type != ID($lut))
continue;
inputs = cell->getPort(ID::A).bits();
inputs = cell->getPort(ID::A);
output = cell->getPort(ID::Y);
lut = cell->getParam(ID::LUT);
} else if (techname == "xilinx" || techname == "gowin") {
@ -213,7 +213,7 @@ struct OptLutInsPass : public Pass {
}
lidx |= val << j;
}
new_lut[i] = lut[lidx];
new_lut.bits()[i] = lut[lidx];
}
// For lattice, and gowin do not replace with a const driver — the nextpnr
// packer requires a complete set of LUTs for wide LUT muxes.

12
passes/opt/opt_mem.cc
View file

@ -90,7 +90,7 @@ struct OptMemPass : public Pass {
}
for (auto &init : mem.inits) {
for (int i = 0; i < GetSize(init.data); i++) {
State bit = init.data.bits[i];
State bit = init.data[i];
int lane = i % mem.width;
if (bit != State::Sx && bit != State::S0) {
always_0[lane] = false;
@ -182,9 +182,9 @@ struct OptMemPass : public Pass {
for (auto i: swizzle) {
int bidx = sub * mem.width + i;
new_data.append(port.data[bidx]);
new_init.bits.push_back(port.init_value.bits[bidx]);
new_arst.bits.push_back(port.arst_value.bits[bidx]);
new_srst.bits.push_back(port.srst_value.bits[bidx]);
new_init.bits().push_back(port.init_value[bidx]);
new_arst.bits().push_back(port.arst_value[bidx]);
new_srst.bits().push_back(port.srst_value[bidx]);
}
}
port.data = new_data;
@ -197,11 +197,11 @@ struct OptMemPass : public Pass {
Const new_en;
for (int s = 0; s < GetSize(init.data); s += mem.width) {
for (auto i: swizzle) {
new_data.bits.push_back(init.data.bits[s + i]);
new_data.bits().push_back(init.data[s + i]);
}
}
for (auto i: swizzle) {
new_en.bits.push_back(init.en.bits[i]);
new_en.bits().push_back(init.en[i]);
}
init.data = new_data;
init.en = new_en;

12
passes/opt/pmux2shiftx.cc
View file

@ -323,7 +323,7 @@ struct Pmux2ShiftxPass : public Pass {
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits.push_back(it.second);
entry.second.bits().push_back(it.second);
}
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
@ -344,7 +344,7 @@ struct Pmux2ShiftxPass : public Pass {
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits.push_back(it.second);
entry.second.bits().push_back(it.second);
}
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
@ -411,7 +411,7 @@ struct Pmux2ShiftxPass : public Pass {
for (int i : seldb.at(sig)) {
Const val = eqdb.at(S[i]).second;
int onebits = 0;
for (auto b : val.bits)
for (auto b : val)
if (b == State::S1)
onebits++;
if (onebits > 1)
@ -590,7 +590,7 @@ struct Pmux2ShiftxPass : public Pass {
used_src_columns[best_src_col] = true;
perm_new_from_old[dst_col] = best_src_col;
perm_xormask[dst_col] = best_inv ? State::S1 : State::S0;
perm_xormask.bits()[dst_col] = best_inv ? State::S1 : State::S0;
}
}
@ -613,7 +613,7 @@ struct Pmux2ShiftxPass : public Pass {
Const new_c(State::S0, GetSize(old_c));
for (int i = 0; i < GetSize(old_c); i++)
new_c[i] = old_c[perm_new_from_old[i]];
new_c.bits()[i] = old_c[perm_new_from_old[i]];
Const new_c_before_xor = new_c;
new_c = const_xor(new_c, perm_xormask, false, false, GetSize(new_c));
@ -686,7 +686,7 @@ struct Pmux2ShiftxPass : public Pass {
if (!full_case) {
Const enable_mask(State::S0, max_choice+1);
for (auto &it : perm_choices)
enable_mask[it.first.as_int()] = State::S1;
enable_mask.bits()[it.first.as_int()] = State::S1;
en = module->addWire(NEW_ID);
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
}

22
passes/opt/share.cc
View file

@ -781,18 +781,18 @@ struct ShareWorker
std::vector<RTLIL::SigBit> p_first_bits = p.first;
for (int i = 0; i < GetSize(p_first_bits); i++) {
RTLIL::SigBit b = p_first_bits[i];
RTLIL::State v = p.second.bits[i];
RTLIL::State v = p.second[i];
if (p_bits.count(b) && p_bits.at(b) != v)
return false;
p_bits[b] = v;
}
p.first = RTLIL::SigSpec();
p.second.bits.clear();
p.second.bits().clear();
for (auto &it : p_bits) {
p.first.append(it.first);
p.second.bits.push_back(it.second);
p.second.bits().push_back(it.second);
}
return true;
@ -815,10 +815,10 @@ struct ShareWorker
{
auto otherval = val;
if (otherval.bits[i] == State::S0)
otherval.bits[i] = State::S1;
else if (otherval.bits[i] == State::S1)
otherval.bits[i] = State::S0;
if (otherval[i] == State::S0)
otherval.bits()[i] = State::S1;
else if (otherval[i] == State::S1)
otherval.bits()[i] = State::S0;
else
continue;
@ -828,7 +828,7 @@ struct ShareWorker
newsig.remove(i);
auto newval = val;
newval.bits.erase(newval.bits.begin() + i);
newval.bits().erase(newval.bits().begin() + i);
db[newsig].insert(newval);
db[sig].erase(otherval);
@ -907,14 +907,14 @@ struct ShareWorker
if (used_in_a)
for (auto p : c_patterns) {
for (int i = 0; i < GetSize(sig_s); i++)
p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
p.first.append(sig_s[i]), p.second.bits().push_back(RTLIL::State::S0);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
for (int idx : used_in_b_parts)
for (auto p : c_patterns) {
p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
p.first.append(sig_s[idx]), p.second.bits().push_back(RTLIL::State::S1);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
@ -965,7 +965,7 @@ struct ShareWorker
for (int i = 0; i < GetSize(p_first); i++)
if (filter_bits.count(p_first[i]) == 0) {
new_p.first.append(p_first[i]);
new_p.second.bits.push_back(p.second.bits.at(i));
new_p.second.bits().push_back(p.second.at(i));
}
out.insert(new_p);

4
passes/opt/wreduce.cc
View file

@ -219,10 +219,10 @@ struct WreduceWorker
// Narrow ARST_VALUE parameter to new size.
if (cell->parameters.count(ID::ARST_VALUE)) {
rst_value.bits.resize(GetSize(sig_q));
rst_value.bits().resize(GetSize(sig_q));
cell->setParam(ID::ARST_VALUE, rst_value);
} else if (cell->parameters.count(ID::SRST_VALUE)) {
rst_value.bits.resize(GetSize(sig_q));
rst_value.bits().resize(GetSize(sig_q));
cell->setParam(ID::SRST_VALUE, rst_value);
}

1
passes/pmgen/Makefile.inc
View file

@ -57,6 +57,7 @@ PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul_right.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftmul_left.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftadd.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_formal_clockgateff.pmg
passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
$(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)

4
passes/pmgen/microchip_dsp.cc
View file

@ -128,7 +128,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
continue;
for (int i = c.offset; i < c.offset + c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};
@ -244,7 +244,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
continue;
for (int i = c.offset; i < c.offset + c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};

26
passes/pmgen/peepopt.cc
View file

@ -40,7 +40,7 @@ struct PeepoptPass : public Pass {
log("\n");
log("This pass applies a collection of peephole optimizers to the current design.\n");
log("\n");
log("This pass employs the following rules:\n");
log("This pass employs the following rules by default:\n");
log("\n");
log(" * muldiv - Replace (A*B)/B with A\n");
log("\n");
@ -57,14 +57,26 @@ struct PeepoptPass : public Pass {
log(" limits the amount of padding to a multiple of the data, \n");
log(" to avoid high resource usage from large temporary MUX trees.\n");
log("\n");
log("If -formalclk is specified it instead employs the following rules:\n");
log("\n");
log(" * clockgateff - Replace latch based clock gating patterns with a flip-flop\n");
log(" based pattern to prevent combinational paths from the\n");
log(" output to the enable input after running clk2fflogic.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n");
bool formalclk = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-formalclk") {
formalclk = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -86,10 +98,14 @@ struct PeepoptPass : public Pass {
pm.setup(module->selected_cells());
pm.run_shiftadd();
pm.run_shiftmul_right();
pm.run_shiftmul_left();
pm.run_muldiv();
if (formalclk) {
pm.run_formal_clockgateff();
} else {
pm.run_shiftadd();
pm.run_shiftmul_right();
pm.run_shiftmul_left();
pm.run_muldiv();
}
}
}
}

59
passes/pmgen/peepopt_formal_clockgateff.pmg Normal file
View file

@ -0,0 +1,59 @@
pattern formal_clockgateff
// Detects the most common clock gating pattern using a latch and replaces it
// with a functionally equivalent pattern based on a flip-flop. The latch
// based pattern has a combinational path from the enable input to output after
// clk2fflogic, but this is a stable loop and the flip-flop based pattern does
// not exhibit this.
//
// This optimization is suitable for formal to prevent false comb loops, but
// should not be used for synthesis where the latch is an intentional choice
//
// Latch style:
// always @* if (!clk_i) latched_en = en;
// assign gated_clk_o = latched_en & clk_i;
//
// Flip-flop style:
// always @(posedge clk) flopped_en <= en;
// assign gated_clk_o = flopped_en & clk_i;
state <SigSpec> clk en latched_en gated_clk
state <IdString> latched_en_port_name
match latch
select latch->type == $dlatch
select param(latch, \WIDTH) == 1
select param(latch, \EN_POLARITY).as_bool() == false
set clk port(latch, \EN)
set en port(latch, \D)
set latched_en port(latch, \Q)
endmatch
match and_gate
select and_gate->type.in($and, $logic_and)
select param(and_gate, \A_WIDTH) == 1
select param(and_gate, \B_WIDTH) == 1
select param(and_gate, \Y_WIDTH) == 1
choice <IdString> clk_port {\A, \B}
define <IdString> latch_port {clk_port == \A ? \B : \A}
index <SigSpec> port(and_gate, clk_port) === clk
index <SigSpec> port(and_gate, latch_port) === latched_en
set gated_clk port(and_gate, \Y)
set latched_en_port_name latch_port
endmatch
code
log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n",
log_id(module), log_id(latch), log_id(and_gate));
// Add a flip-flop and rewire the AND gate to use the output of this flop
// instead of the latch. We don't delete the latch in case its output is
// used to drive other nodes. If it isn't, it will be trivially removed by
// clean
SigSpec flopped_en = module->addWire(NEW_ID);
module->addDff(NEW_ID, clk, en, flopped_en, true, latch->get_src_attribute());
and_gate->setPort(latched_en_port_name, flopped_en);
did_something = true;
accept;
endcode

10
passes/pmgen/xilinx_dsp.cc
View file

@ -339,11 +339,11 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.overflow->type == ID($ge)) {
Const B = st.overflow->getPort(ID::B).as_const();
log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1);
log_assert(std::count(B.begin(), B.end(), State::S1) == 1);
// Since B is an exact power of 2, subtract 1
// by inverting all bits up until hitting
// that one hi bit
for (auto &b : B.bits)
for (auto &b : B.bits())
if (b == State::S0) b = State::S1;
else if (b == State::S1) {
b = State::S0;
@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};
@ -579,7 +579,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};
@ -702,7 +702,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
it->second[i] = State::Sx;
it->second.bits()[i] = State::Sx;
}
}
};

2
passes/pmgen/xilinx_dsp.pmg
View file

@ -363,7 +363,7 @@ match overflow
select GetSize(port(overflow, \Y)) <= 48
select port(overflow, \B).is_fully_const()
define <Const> B port(overflow, \B).as_const()
select std::count(B.bits.begin(), B.bits.end(), State::S1) == 1
select std::count(B.begin(), B.end(), State::S1) == 1
index <SigSpec> port(overflow, \A) === sigP
optional
endmatch

4
passes/pmgen/xilinx_srl.cc
View file

@ -40,7 +40,7 @@ void run_fixed(xilinx_srl_pm &pm)
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset];
auto &i = it->second.bits()[Q.offset];
initval.append(i);
i = State::Sx;
}
@ -121,7 +121,7 @@ void run_variable(xilinx_srl_pm &pm)
log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset];
auto &i = it->second.bits()[Q.offset];
initval.append(i);
i = State::Sx;
}

6
passes/proc/proc_init.cc
View file

@ -53,11 +53,11 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
Const value = valuesig.as_const();
Const &wireinit = lhs_c.wire->attributes[ID::init];
while (GetSize(wireinit.bits) < lhs_c.wire->width)
wireinit.bits.push_back(State::Sx);
while (GetSize(wireinit) < lhs_c.wire->width)
wireinit.bits().push_back(State::Sx);
for (int i = 0; i < lhs_c.width; i++) {
auto &initbit = wireinit.bits[i + lhs_c.offset];
auto &initbit = wireinit.bits()[i + lhs_c.offset];
if (initbit != State::Sx && initbit != value[i])
log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
initbit = value[i];

2
passes/proc/proc_memwr.cc
View file

@ -39,7 +39,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
Const priority_mask(State::S0, port_id);
for (int i = 0; i < GetSize(prev_port_ids); i++)
if (memwr.priority_mask[i] == State::S1)
priority_mask[prev_port_ids[i]] = State::S1;
priority_mask.bits()[prev_port_ids[i]] = State::S1;
prev_port_ids.push_back(port_id);
RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));

16
passes/proc/proc_rom.cc
View file

@ -97,10 +97,10 @@ struct RomWorker
log_debug("rejecting switch: lhs not uniform\n");
return;
}
val[it2->second] = it.second[i].data;
val.bits()[it2->second] = it.second[i].data;
}
}
for (auto bit: val.bits) {
for (auto bit: val) {
if (bit == State::Sm) {
log_debug("rejecting switch: lhs not uniform\n");
return;
@ -113,8 +113,8 @@ struct RomWorker
return;
}
Const c = addr.as_const();
while (GetSize(c) && c.bits.back() == State::S0)
c.bits.pop_back();
while (GetSize(c) && c.back() == State::S0)
c.bits().pop_back();
if (GetSize(c) > swsigbits)
continue;
if (GetSize(c) > 30) {
@ -160,11 +160,11 @@ struct RomWorker
auto it = vals.find(i);
if (it == vals.end()) {
log_assert(got_default);
for (auto bit: default_val.bits)
init_data.bits.push_back(bit);
for (auto bit: default_val)
init_data.bits().push_back(bit);
} else {
for (auto bit: it->second.bits)
init_data.bits.push_back(bit);
for (auto bit: it->second)
init_data.bits().push_back(bit);
}
}

15
passes/sat/clk2fflogic.cc
View file

@ -51,6 +51,10 @@ struct Clk2fflogicPass : public Pass {
log(" -nolower\n");
log(" Do not automatically run 'chformal -lower' to lower $check cells.\n");
log("\n");
log(" -nopeepopt\n");
log(" Do not automatically run 'peepopt -formalclk' to rewrite clock patterns\n");
log(" to more formal friendly forms.\n");
log("\n");
}
// Active-high sampled and current value of a level-triggered control signal. Initial sampled values is low/non-asserted.
SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) {
@ -121,6 +125,7 @@ struct Clk2fflogicPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_nolower = false;
bool flag_nopeepopt = false;
log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n");
@ -131,10 +136,20 @@ struct Clk2fflogicPass : public Pass {
flag_nolower = true;
continue;
}
if (args[argidx] == "-nopeepopt") {
flag_nopeepopt = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!flag_nopeepopt) {
log_push();
Pass::call(design, "peepopt -formalclk");
log_pop();
}
bool have_check_cells = false;
for (auto module : design->selected_modules())

8
passes/sat/eval.cc
View file

@ -250,13 +250,13 @@ struct VlogHammerReporter
std::string module_name = module_names[mod].c_str();
ConstEval ce(module);
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
std::vector<RTLIL::State> bits(patterns[idx].begin(), patterns[idx].begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wire(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
recorded_set_vals.bits.push_back(bits.back());
recorded_set_vals.bits().push_back(bits.back());
bits.pop_back();
}
if (module == modules.front()) {
@ -346,7 +346,7 @@ struct VlogHammerReporter
log_error("Pattern %s is to short!\n", pattern.c_str());
patterns.push_back(sig.as_const());
if (invert_pattern) {
for (auto &bit : patterns.back().bits)
for (auto &bit : patterns.back().bits())
if (bit == RTLIL::State::S0)
bit = RTLIL::State::S1;
else if (bit == RTLIL::State::S1)
@ -557,7 +557,7 @@ struct EvalPass : public Pass {
tab_line.clear();
ce.pop();
tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.bits.size());
tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.size());
}
while (tabvals.as_bool());

2
passes/sat/expose.cc
View file

@ -131,7 +131,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits;
std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).to_bits();
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
info.arst_value = arst_value.at(i);

6
passes/sat/formalff.cc
View file

@ -363,7 +363,7 @@ struct PropagateWorker
for (auto wire : module->wires())
if (wire->has_attribute(ID::replaced_by_gclk))
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1, false);
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].at(0) == State::S1, false);
for (auto cell : module->cells()) {
if (cell->type.in(ID($not), ID($_NOT_))) {
@ -622,7 +622,7 @@ struct FormalFfPass : public Pass {
auto before = ff.val_init;
for (int i = 0; i < ff.width; i++)
if (ff.val_init[i] == State::Sx && !worker.is_initval_used(ff.sig_q[i]))
ff.val_init[i] = State::S0;
ff.val_init.bits()[i] = State::S0;
if (ff.val_init != before) {
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
@ -745,7 +745,7 @@ struct FormalFfPass : public Pass {
for (auto wire : module->wires()) {
if (!wire->has_attribute(ID::replaced_by_gclk))
continue;
bool clk_pol = wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1;
bool clk_pol = wire->attributes[ID::replaced_by_gclk].at(0) == State::S1;
found.emplace_back(SigSpec(wire), clk_pol);
}

16
passes/sat/sat.cc
View file

@ -629,9 +629,9 @@ struct SatHelper
bool found_undef = false;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx, found_undef = true;
value.bits().back() = RTLIL::State::Sx, found_undef = true;
}
if (info.timestep != last_timestep) {
@ -740,9 +740,9 @@ struct SatHelper
RTLIL::Const value;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx;
value.bits().back() = RTLIL::State::Sx;
}
if (info.timestep != last_timestep) {
@ -754,11 +754,11 @@ struct SatHelper
}
if(info.width == 1) {
fprintf(f, "%c%s\n", bitvals[value.bits[0]], vcdnames[info.description].c_str());
fprintf(f, "%c%s\n", bitvals[value[0]], vcdnames[info.description].c_str());
} else {
fprintf(f, "b");
for(int k=info.width-1; k >= 0; k --) //need to flip bit ordering for VCD
fprintf(f, "%c", bitvals[value.bits[k]]);
fprintf(f, "%c", bitvals[value[k]]);
fprintf(f, " %s\n", vcdnames[info.description].c_str());
}
}
@ -786,9 +786,9 @@ struct SatHelper
{
Const value;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx;
value.bits().back() = RTLIL::State::Sx;
}
wavedata[info.description].first = info.width;

34
passes/sat/sim.cc
View file

@ -135,7 +135,7 @@ void zinit(State &v)
void zinit(Const &v)
{
for (auto &bit : v.bits)
for (auto &bit : v.bits())
zinit(bit);
}
@ -423,11 +423,11 @@ struct SimInstance
for (auto bit : sigmap(sig))
if (bit.wire == nullptr)
value.bits.push_back(bit.data);
value.bits().push_back(bit.data);
else if (state_nets.count(bit))
value.bits.push_back(state_nets.at(bit));
value.bits().push_back(state_nets.at(bit));
else
value.bits.push_back(State::Sz);
value.bits().push_back(State::Sz);
if (shared->debug)
log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
@ -486,9 +486,9 @@ struct SimInstance
int offset = (addr - state.mem->start_offset) * state.mem->width;
for (int i = 0; i < GetSize(data); i++)
if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data.bits[i] != State::Sa)
if (state.data.bits[i+offset] != data.bits[i])
dirty = true, state.data.bits[i+offset] = data.bits[i];
if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data[i] != State::Sa)
if (state.data[i+offset] != data[i])
dirty = true, state.data.bits()[i+offset] = data[i];
if (dirty)
dirty_memories.insert(memid);
@ -499,8 +499,8 @@ struct SimInstance
auto &state = mem_database[memid];
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
if (state.data.bits[offset] != data) {
state.data.bits[offset] = data;
if (state.data[offset] != data) {
state.data.bits()[offset] = data;
dirty_memories.insert(memid);
}
}
@ -717,10 +717,10 @@ struct SimInstance
for(int i=0;i<ff.past_d.size();i++) {
if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
current_q[i] = State::S0;
current_q.bits()[i] = State::S0;
}
else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
current_q[i] = State::S1;
current_q.bits()[i] = State::S1;
}
}
}
@ -769,8 +769,8 @@ struct SimInstance
int index = addr_int - mem.start_offset;
if (index >= 0 && index < mem.size)
for (int i = 0; i < (mem.width << port.wide_log2); i++)
if (enable[i] == State::S1 && mdb.data.bits.at(index*mem.width+i) != data[i]) {
mdb.data.bits.at(index*mem.width+i) = data[i];
if (enable[i] == State::S1 && mdb.data.at(index*mem.width+i) != data[i]) {
mdb.data.bits().at(index*mem.width+i) = data[i];
dirty_memories.insert(mem.memid);
did_something = true;
}
@ -971,7 +971,7 @@ struct SimInstance
if (w->attributes.count(ID::init) == 0)
w->attributes[ID::init] = Const(State::Sx, GetSize(w));
w->attributes[ID::init][sig_q[i].offset] = initval[i];
w->attributes[ID::init].bits()[sig_q[i].offset] = initval[i];
}
}
@ -2542,7 +2542,7 @@ struct AIWWriter : public OutputWriter
{
auto val = it.second ? State::S1 : State::S0;
SigBit bit = aiw_inputs.at(it.first);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].at(bit.offset);
if (v == val)
skip = true;
}
@ -2552,7 +2552,7 @@ struct AIWWriter : public OutputWriter
{
if (aiw_inputs.count(i)) {
SigBit bit = aiw_inputs.at(i);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].at(bit.offset);
if (v == State::S1)
aiwfile << '1';
else
@ -2561,7 +2561,7 @@ struct AIWWriter : public OutputWriter
}
if (aiw_inits.count(i)) {
SigBit bit = aiw_inits.at(i);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].at(bit.offset);
if (v == State::S1)
aiwfile << '1';
else

2
passes/techmap/Makefile.inc
View file

@ -12,10 +12,12 @@ OBJS += passes/techmap/abc.o
OBJS += passes/techmap/abc9.o
OBJS += passes/techmap/abc9_exe.o
OBJS += passes/techmap/abc9_ops.o
OBJS += passes/techmap/abc_new.o
ifneq ($(ABCEXTERNAL),)
passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
passes/techmap/abc9_exe.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
passes/techmap/abc_new.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
endif
endif

3
passes/techmap/abc9.cc
View file

@ -220,7 +220,8 @@ struct Abc9Pass : public ScriptPass
std::string arg = args[argidx];
if ((arg == "-exe" || arg == "-script" || arg == "-D" ||
/*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" ||
/*arg == "-box" ||*/ arg == "-W") &&
/*arg == "-box" ||*/ arg == "-W" || arg == "-genlib" ||
arg == "-constr" || arg == "-dont_use" || arg == "-liberty") &&
argidx+1 < args.size()) {
if (arg == "-lut" || arg == "-luts")
lut_mode = true;

55
passes/techmap/abc9_exe.cc
View file

@ -167,8 +167,8 @@ struct abc9_output_filter
void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe_file,
vector<int> lut_costs, bool dff_mode, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
bool show_tempdir, std::string box_file, std::string lut_file,
std::string wire_delay, std::string tempdir_name
)
std::vector<std::string> liberty_files, std::string wire_delay, std::string tempdir_name,
std::string constr_file, std::vector<std::string> dont_use_cells)
{
std::string abc9_script;
@ -176,8 +176,17 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
else if (!lut_file.empty())
abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str());
else
log_abort();
else if (!liberty_files.empty()) {
std::string dont_use_args;
for (std::string dont_use_cell : dont_use_cells) {
dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str());
}
for (std::string liberty_file : liberty_files) {
abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str());
}
if (!constr_file.empty())
abc9_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str());
}
log_assert(!box_file.empty());
abc9_script += stringf("read_box \"%s\"; ", box_file.c_str());
@ -359,6 +368,26 @@ struct Abc9ExePass : public Pass {
log(" of output quality):\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
log("\n");
log(" -constr <file>\n");
log(" pass this file with timing constraints to ABC.\n");
log(" use with -liberty.\n");
log("\n");
log(" a constr file contains two lines:\n");
log(" set_driving_cell <cell_name>\n");
log(" set_load <floating_point_number>\n");
log("\n");
log(" the set_driving_cell statement defines which cell type is assumed to\n");
log(" drive the primary inputs and the set_load statement sets the load in\n");
log(" femtofarads for each primary output.\n");
log("\n");
log(" -liberty <file>\n");
log(" read the given Liberty file as a description of the target cell library.\n");
log(" this option can be used multiple times.\n");
log("\n");
log(" -dont_use <cell_name>\n");
log(" avoid usage of the technology cell <cell_name> when mapping the design.\n");
log(" this option can be used multiple times.\n");
log("\n");
log(" -D <picoseconds>\n");
log(" set delay target. the string {D} in the default scripts above is\n");
log(" replaced by this option when used, and an empty string otherwise\n");
@ -411,7 +440,8 @@ struct Abc9ExePass : public Pass {
log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n");
std::string exe_file = yosys_abc_executable;
std::string script_file, clk_str, box_file, lut_file;
std::string script_file, clk_str, box_file, lut_file, constr_file;
std::vector<std::string> liberty_files, dont_use_cells;
std::string delay_target, lutin_shared = "-S 1", wire_delay;
std::string tempdir_name;
bool fast_mode = false, dff_mode = false;
@ -499,6 +529,18 @@ struct Abc9ExePass : public Pass {
tempdir_name = args[++argidx];
continue;
}
if (arg == "-liberty" && argidx+1 < args.size()) {
liberty_files.push_back(args[++argidx]);
continue;
}
if (arg == "-dont_use" && argidx+1 < args.size()) {
dont_use_cells.push_back(args[++argidx]);
continue;
}
if (arg == "-constr" && argidx+1 < args.size()) {
constr_file = args[++argidx];
continue;
}
break;
}
extra_args(args, argidx, design);
@ -562,7 +604,8 @@ struct Abc9ExePass : public Pass {
abc9_module(design, script_file, exe_file, lut_costs, dff_mode,
delay_target, lutin_shared, fast_mode, show_tempdir,
box_file, lut_file, wire_delay, tempdir_name);
box_file, lut_file, liberty_files, wire_delay, tempdir_name,
constr_file, dont_use_cells);
}
} Abc9ExePass;

6
passes/techmap/abc9_ops.cc
View file

@ -1217,7 +1217,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
auto Qi = initmap(Q);
auto it = Qi.wire->attributes.find(ID::init);
if (it != Qi.wire->attributes.end())
it->second[Qi.offset] = State::Sx;
it->second.bits()[Qi.offset] = State::Sx;
}
else if (cell->type.in(ID($_AND_), ID($_NOT_)))
module->remove(cell);
@ -1528,7 +1528,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
int i = 0;
while (i < GetSize(mask)) {
for (int j = 0; j < (1 << index); j++)
std::swap(mask[i+j], mask[i+j+(1 << index)]);
std::swap(mask.bits()[i+j], mask.bits()[i+j+(1 << index)]);
i += 1 << (index+1);
}
A[index] = y_bit;
@ -1543,7 +1543,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// and get cleaned away
clone_lut:
driver_mask = driver_lut->getParam(ID::LUT);
for (auto &b : driver_mask.bits) {
for (auto &b : driver_mask.bits()) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}

153
passes/techmap/abc_new.cc Normal file
View file

@ -0,0 +1,153 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2024 Martin Povišer <povik@cutebit.org>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/rtlil.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct AbcNewPass : public ScriptPass {
AbcNewPass() : ScriptPass("abc_new", "(experimental) use ABC for SC technology mapping (new)")
{
experimental();
}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" abc_new [options] [selection]\n");
log("\n");
log("This command uses the ABC tool [1] to optimize the current design and map it to\n");
log("the target standard cell library.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -exe <command>\n");
log(" -script <file>\n");
log(" -D <picoseconds>\n");
log(" -constr <file>\n");
log(" -dont_use <cell_name>\n");
log(" -liberty <file>\n");
log(" these options are passed on to the 'abc9_exe' command which invokes\n");
log(" the ABC tool on individual modules of the design. please see\n");
log(" 'help abc9_exe' for more details\n");
log("\n");
log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
log("\n");
help_script();
log("\n");
}
bool cleanup;
std::string abc_exe_options;
void execute(std::vector<std::string> args, RTLIL::Design *d) override
{
std::string run_from, run_to;
cleanup = true;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-exe" || args[argidx] == "-script" ||
args[argidx] == "-D" ||
args[argidx] == "-constr" || args[argidx] == "-dont_use" ||
args[argidx] == "-liberty") {
abc_exe_options += " " + args[argidx] + " " + args[argidx + 1];
argidx++;
} else if (args[argidx] == "-run" && argidx + 1 < args.size()) {
size_t pos = args[++argidx].find(':');
if (pos == std::string::npos)
break;
run_from = args[argidx].substr(0, pos);
run_to = args[argidx].substr(pos + 1);
} else if (args[argidx] == "-nocleanup") {
cleanup = false;
} else {
break;
}
}
extra_args(args, argidx, d);
log_header(d, "Executing ABC_NEW pass.\n");
log_push();
run_script(d, run_from, run_to);
log_pop();
}
void script() override
{
if (check_label("check")) {
run("abc9_ops -check");
}
if (check_label("prep_boxes")) {
run("box_derive");
run("abc9_ops -prep_box");
}
if (check_label("map")) {
std::vector<Module *> selected_modules;
if (!help_mode) {
selected_modules = active_design->selected_whole_modules_warn();
active_design->selection_stack.emplace_back(false);
} else {
selected_modules = {nullptr};
run("foreach module in selection");
}
for (auto mod : selected_modules) {
std::string tmpdir = "<abc-temp-dir>";
std::string modname = "<module>";
std::string exe_options = "[options]";
if (!help_mode) {
tmpdir = cleanup ? (get_base_tmpdir() + "/") : "_tmp_";
tmpdir += proc_program_prefix() + "yosys-abc-XXXXXX";
tmpdir = make_temp_dir(tmpdir);
modname = mod->name.str();
exe_options = abc_exe_options;
log_header(active_design, "Mapping module '%s'.\n", log_id(mod));
log_push();
active_design->selection().select(mod);
}
run(stringf(" abc9_ops -write_box %s/input.box", tmpdir.c_str()));
run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir.c_str(), tmpdir.c_str()));
run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options.c_str(), tmpdir.c_str(), tmpdir.c_str()));
run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
modname.c_str(), tmpdir.c_str(), tmpdir.c_str()));
if (!help_mode) {
active_design->selection().selected_modules.clear();
log_pop();
}
}
if (!help_mode) {
active_design->selection_stack.pop_back();
}
}
}
} AbcNewPass;
PRIVATE_NAMESPACE_END

27
passes/techmap/bufnorm.cc
View file

@ -70,9 +70,9 @@ struct BufnormPass : public Pass {
log(" to chain 'keep' wires first, then ports in declaration order,\n");
log(" and then the other wires in alphanumeric sort order.)\n");
log("\n");
log(" -noinit\n");
log(" Do not move 'init' attributes to the wires on FF output ports.\n");
log("\n");
// log(" -noinit\n");
// log(" Do not move 'init' attributes to the wires on FF output ports.\n");
// log("\n");
log("Run 'bufnorm' with -pos, -bits, or -conn on the whole design to remove all\n");
log("$buf buffer cells and exit 'buffered-normalized mode' again.\n");
log("\n");
@ -108,7 +108,7 @@ struct BufnormPass : public Pass {
bool nokeep_mode = false;
bool nosticky_mode = false;
bool alphasort_mode = false;
bool noinit_mode = false; // FIXME: Actually move init attributes
// bool noinit_mode = false; // FIXME: Actually move init attributes
bool nomode_mode = false;
bool pos_mode = false;
@ -169,11 +169,11 @@ struct BufnormPass : public Pass {
got_non_update_reset_opt = true;
continue;
}
if (arg == "-noinit") {
noinit_mode = true;
got_non_update_reset_opt = true;
continue;
}
// if (arg == "-noinit") {
// noinit_mode = true;
// got_non_update_reset_opt = true;
// continue;
// }
if (arg == "-pos") {
pos_mode = true;
got_non_update_reset_opt = true;
@ -438,8 +438,13 @@ struct BufnormPass : public Pass {
bool chain_this_wire = chain_this_wire_f(wire);
SigSpec keysig = sigmap(wire), insig = wire, outsig = wire;
for (int i = 0; i < GetSize(insig); i++)
insig[i] = mapped_bits.at(keysig[i], State::Sx);
for (int i = 0; i < GetSize(insig); i++) {
if (keysig[i].is_wire())
insig[i] = mapped_bits.at(keysig[i], State::Sx);
else
insig[i] = keysig[i];
}
if (chain_this_wire) {
for (int i = 0; i < GetSize(outsig); i++)
mapped_bits[keysig[i]] = outsig[i];

22
passes/techmap/cellmatch.cc
View file

@ -155,18 +155,22 @@ struct CellmatchPass : Pass {
log("equivalent as long as their truth tables are identical upto a permutation of\n");
log("inputs and outputs. The supported number of inputs is limited to 6.\n");
log("\n");
log(" cellmatch -derive_luts [module selection]\n");
log("\n");
log("For every port in each selected module, characterize its combinational\n");
log("function with a 'lut' attribute if possible.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *d) override
{
log_header(d, "Executing CELLMATCH pass. (match cells)\n");
size_t argidx;
bool lut_attrs = false;
bool derive_luts = false;
Design *lib = NULL;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-lut_attrs") {
// an undocumented debugging option
lut_attrs = true;
if (args[argidx] == "-derive_luts") {
derive_luts = true;
} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
if (!saved_designs.count(args[++argidx]))
log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
@ -177,8 +181,8 @@ struct CellmatchPass : Pass {
}
extra_args(args, argidx, d);
if (!lib && !lut_attrs)
log_cmd_error("Missing required -lib option.\n");
if (!lib && !derive_luts)
log_cmd_error("Missing required -lib or -derive_luts option.\n");
struct Target {
Module *module;
@ -210,7 +214,7 @@ struct CellmatchPass : Pass {
r.first->second = new Design;
Design *map_design = r.first->second;
for (auto m : d->selected_whole_modules_warn()) {
for (auto m : d->selected_whole_modules_warn(/* visit whiteboxes */derive_luts)) {
std::vector<uint64_t> luts;
if (!derive_module_luts(m, luts))
continue;
@ -218,12 +222,12 @@ struct CellmatchPass : Pass {
SigSpec inputs = module_inputs(m);
SigSpec outputs = module_outputs(m);
if (lut_attrs) {
if (derive_luts) {
int no = 0;
for (auto bit : outputs) {
log_assert(bit.is_wire());
bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
bit.wire->attributes[ID(lut)] = luts[no++];
bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
}
}

8
passes/techmap/dffinit.cc
View file

@ -118,13 +118,13 @@ struct DffinitPass : public Pass {
for (int i = 0; i < GetSize(sig); i++) {
if (initval[i] == State::Sx)
continue;
while (GetSize(value.bits) <= i)
value.bits.push_back(State::S0);
if (noreinit && value.bits[i] != State::Sx && value.bits[i] != initval[i])
while (GetSize(value) <= i)
value.bits().push_back(State::S0);
if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second));
value.bits[i] = initval[i];
value.bits()[i] = initval[i];
}
if (highlow_mode && GetSize(value) != 0) {

8
passes/techmap/dfflegalize.cc
View file

@ -869,17 +869,17 @@ struct DffLegalizePass : public Pass {
if (ff.has_arst) {
if (ff.val_arst[i] == State::Sx) {
if (!(supported & (mask << 8)))
ff.val_arst[i] = State::S0;
ff.val_arst.bits()[i] = State::S0;
if (!(supported & (mask << 4)))
ff.val_arst[i] = State::S1;
ff.val_arst.bits()[i] = State::S1;
}
}
if (ff.has_srst) {
if (ff.val_srst[i] == State::Sx) {
if (!(supported & (mask << 8)))
ff.val_srst[i] = State::S0;
ff.val_srst.bits()[i] = State::S0;
if (!(supported & (mask << 4)))
ff.val_srst[i] = State::S1;
ff.val_srst.bits()[i] = State::S1;
}
}
}

2
passes/techmap/flowmap.cc
View file

@ -1399,7 +1399,7 @@ struct FlowmapWorker
log_signal(node), log_signal(undef), env.c_str());
}
lut_table[i] = value.as_bool() ? State::S1 : State::S0;
lut_table.bits()[i] = value.as_bool() ? State::S1 : State::S0;
ce.pop();
}

4
passes/techmap/techmap.cc
View file

@ -684,7 +684,7 @@ struct TechmapWorker
for (auto &bit : sigmap(conn.second)) {
int val = unique_bit_id.at(bit);
for (int i = 0; i < bits; i++) {
value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0);
val = val >> 1;
}
}
@ -1226,7 +1226,7 @@ struct TechmapPass : public Pass {
dict<IdString, pool<IdString>> celltypeMap;
for (auto module : map->modules()) {
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).empty()) {
char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) {
std::vector<std::string> queue;

6
passes/techmap/zinit.cc
View file

@ -73,10 +73,10 @@ struct ZinitPass : public Pass {
pool<int> bits;
for (int i = 0; i < ff.width; i++) {
if (ff.val_init.bits[i] == State::S1)
if (ff.val_init[i] == State::S1)
bits.insert(i);
else if (ff.val_init.bits[i] != State::S0 && all_mode)
ff.val_init.bits[i] = State::S0;
else if (ff.val_init[i] != State::S0 && all_mode)
ff.val_init.bits()[i] = State::S0;
}
ff.flip_bits(bits);
ff.emit();

4
passes/tests/test_cell.cc
View file

@ -544,13 +544,13 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
RTLIL::Const in_value;
for (int i = 0; i < GetSize(gold_wire); i++)
in_value.bits.push_back(xorshift32(2) ? State::S1 : State::S0);
in_value.bits().push_back(xorshift32(2) ? State::S1 : State::S0);
if (xorshift32(4) == 0) {
int inv_chance = 1 + xorshift32(8);
for (int i = 0; i < GetSize(gold_wire); i++)
if (xorshift32(inv_chance) == 0)
in_value.bits[i] = RTLIL::Sx;
in_value.bits()[i] = RTLIL::Sx;
}
if (verbose)