From f6f85f475ba2abd186ddda10d0099750e28231ca Mon Sep 17 00:00:00 2001 From: George Rennie Date: Sun, 24 Sep 2023 12:40:41 +0100 Subject: [PATCH 001/240] smt2: Check for constant bool after fully resolving signal * This fixes #3769 --- backends/smt2/smt2.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 5e63e6237..703628b73 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -329,13 +329,14 @@ struct Smt2Worker { sigmap.apply(bit); + if (bit_driver.count(bit)) { + export_cell(bit_driver.at(bit)); + sigmap.apply(bit); + } + if (bit.wire == nullptr) return bit == RTLIL::State::S1 ? "true" : "false"; - if (bit_driver.count(bit)) - export_cell(bit_driver.at(bit)); - sigmap.apply(bit); - if (fcache.count(bit) == 0) { if (verbose) log("%*s-> external bool: %s\n", 2+2*GetSize(recursive_cells), "", log_signal(bit)); From 3f71bc469de63ae6380e10e5f198a8ba1b7d7b3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 18 Jul 2024 13:01:22 +0200 Subject: [PATCH 002/240] check: Rephrase comment --- passes/cmds/check.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 255c32fba..1848d34b6 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -284,10 +284,10 @@ struct CheckPass : public Pass { for (auto &loop : topo.loops) { string message = stringf("found logic loop in module %s:\n", log_id(module)); - // `loop` only contains wire bits, or an occassional special helper node for cells for - // which we have done the edges fallback. The cell and its ports that led to an edge is - // an information we need to recover now. For that we need to have the previous wire bit - // of the loop at hand. + // `loop` only contains wire bits, or an occasional special helper node for cells for + // which we have done the edges fallback. The cell and its ports that led to an edge are + // a piece of information we need to recover now. For that we need to have the previous + // wire bit of the loop at hand. SigBit prev; for (auto it = loop.rbegin(); it != loop.rend(); it++) if (it->second != -1) { // skip the fallback helper nodes From e70b1251adc4e932fd069ee66372b25ce5f7a2b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 18 Jul 2024 13:01:37 +0200 Subject: [PATCH 003/240] check: Adjust prints --- passes/cmds/check.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 1848d34b6..c849b986c 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -316,10 +316,10 @@ struct CheckPass : public Pass { SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit]; if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT) - message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit, + message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit, log_id(to_port), to_bit); if (nhits == HITS_LIMIT) - message += " ...\n"; + message += " ...\n"; } }; From 0cefe8a1e87d3b33c856ad9103bcc6ea07debd33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 18 Jul 2024 13:04:27 +0200 Subject: [PATCH 004/240] check: Skip detailed edge modeling if costly --- passes/cmds/check.cc | 79 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 69 insertions(+), 10 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index c849b986c..83fe781a0 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -59,6 +59,12 @@ struct CheckPass : public Pass { log(" -assert\n"); log(" produce a runtime error if any problems are found in the current design\n"); log("\n"); + log(" -force-detailed-loop-check\n"); + log(" for the detection of combinatorial loops, use a detailed connectivity\n"); + log(" model for all internal cells for which it is available. This disables\n"); + log(" falling back to a simpler overapproximating model for those cells for\n"); + log(" which the detailed model is expected costly.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { @@ -68,6 +74,8 @@ struct CheckPass : public Pass { bool mapped = false; bool allow_tbuf = false; bool assert_mode = false; + bool force_detailed_loop_check = false; + bool suggest_detail = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -91,6 +99,10 @@ struct CheckPass : public Pass { assert_mode = true; continue; } + if (args[argidx] == "-force-detailed-loop-check") { + force_detailed_loop_check = true; + continue; + } break; } extra_args(args, argidx, design); @@ -154,9 +166,10 @@ struct CheckPass : public Pass { struct CircuitEdgesDatabase : AbstractCellEdgesDatabase { TopoSort> &topo; SigMap sigmap; + bool force_detail; - CircuitEdgesDatabase(TopoSort> &topo, SigMap &sigmap) - : topo(topo), sigmap(sigmap) {} + CircuitEdgesDatabase(TopoSort> &topo, SigMap &sigmap, bool force_detail) + : topo(topo), sigmap(sigmap), force_detail(force_detail) {} void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { @@ -171,10 +184,41 @@ struct CheckPass : public Pass { topo.edge(std::make_pair(from.wire->name, from.offset), std::make_pair(to.wire->name, to.offset)); } - bool add_edges_from_cell(Cell *cell) { - if (AbstractCellEdgesDatabase::add_edges_from_cell(cell)) + bool detail_costly(Cell *cell) { + // Only those cell types for which the edge data can expode quadratically + // in port widths are those for us to check. + if (!cell->type.in( + ID($add), ID($sub), + ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) + return false; + + int in_widths = 0, out_widths = 0; + + for (auto &conn : cell->connections()) { + if (cell->input(conn.first)) + in_widths += conn.second.size(); + if (cell->output(conn.first)) + out_widths += conn.second.size(); + } + + const int threshold = 1024; + + // if the multiplication may overflow we will catch it here + if (in_widths + out_widths >= threshold) return true; + if (in_widths * out_widths >= threshold) + return true; + + return false; + } + + bool add_edges_from_cell(Cell *cell) { + if (force_detail || !detail_costly(cell)) { + if (AbstractCellEdgesDatabase::add_edges_from_cell(cell)) + return true; + } + // We don't have accurate cell edges, do the fallback of all input-output pairs for (auto &conn : cell->connections()) { if (cell->input(conn.first)) @@ -189,12 +233,15 @@ struct CheckPass : public Pass { topo.edge(std::make_pair(cell->name, -1), std::make_pair(bit.wire->name, bit.offset)); } - return true; + + // Return false to signify the fallback + return false; } }; - CircuitEdgesDatabase edges_db(topo, sigmap); + CircuitEdgesDatabase edges_db(topo, sigmap, force_detailed_loop_check); + pool coarsened_cells; for (auto cell : module->cells()) { if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) { @@ -225,8 +272,10 @@ struct CheckPass : public Pass { } if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \ - || RTLIL::builtin_ff_cell_types().count(cell->type)) - edges_db.add_edges_from_cell(cell); + || RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (!edges_db.add_edges_from_cell(cell)) + coarsened_cells.insert(cell); + } } pool init_bits; @@ -334,9 +383,16 @@ struct CheckPass : public Pass { std::string src_attr = driver->get_src_attribute(); driver_src = stringf(" source: %s", src_attr.c_str()); } + message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str()); - MatchingEdgePrinter printer(message, sigmap, prev, bit); - printer.add_edges_from_cell(driver); + + if (!coarsened_cells.count(driver)) { + MatchingEdgePrinter printer(message, sigmap, prev, bit); + printer.add_edges_from_cell(driver); + } else { + message += " (cell's internal connectivity overapproximated; loop may be a false positive)\n"; + suggest_detail = true; + } if (wire->name.isPublic()) { std::string wire_src; @@ -376,6 +432,9 @@ struct CheckPass : public Pass { log("Found and reported %d problems.\n", counter); + if (suggest_detail) + log("Consider re-running with '-force-detailed-loop-check' to rule out false positives.\n"); + if (assert_mode && counter > 0) log_error("Found %d problems in 'check -assert'.\n", counter); } From 2cb3b6e9b8f59936524729af591d1cfbcec0e461 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Tue, 6 Aug 2024 16:32:26 +0100 Subject: [PATCH 005/240] peepopt: add formal only peepopt to rewrite latches to ffs in clock gates * this is gated behind the -formalclk flag, which also disables the other synthesis focused optimizations --- passes/pmgen/Makefile.inc | 1 + passes/pmgen/peepopt.cc | 26 +++++++-- passes/pmgen/peepopt_formal_clockgateff.pmg | 59 +++++++++++++++++++++ 3 files changed, 81 insertions(+), 5 deletions(-) create mode 100644 passes/pmgen/peepopt_formal_clockgateff.pmg diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index 84d9ebaf1..6fa7d1fd7 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -57,6 +57,7 @@ PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul_right.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftmul_left.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftadd.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg +PEEPOPT_PATTERN += passes/pmgen/peepopt_formal_clockgateff.pmg passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN) $(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index 5638ec3c2..5b678ee55 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -40,7 +40,7 @@ struct PeepoptPass : public Pass { log("\n"); log("This pass applies a collection of peephole optimizers to the current design.\n"); log("\n"); - log("This pass employs the following rules:\n"); + log("This pass employs the following rules by default:\n"); log("\n"); log(" * muldiv - Replace (A*B)/B with A\n"); log("\n"); @@ -57,14 +57,26 @@ struct PeepoptPass : public Pass { log(" limits the amount of padding to a multiple of the data, \n"); log(" to avoid high resource usage from large temporary MUX trees.\n"); log("\n"); + log("If -formalclk is specified it instead employs the following rules:\n"); + log("\n"); + log(" * clockgateff - Replace latch based clock gating patterns with a flip-flop\n"); + log(" based pattern to prevent combinational paths from the\n"); + log(" output to the enable input after running clk2fflogic.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n"); + bool formalclk = false; + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-formalclk") { + formalclk = true; + continue; + } break; } extra_args(args, argidx, design); @@ -86,10 +98,14 @@ struct PeepoptPass : public Pass { pm.setup(module->selected_cells()); - pm.run_shiftadd(); - pm.run_shiftmul_right(); - pm.run_shiftmul_left(); - pm.run_muldiv(); + if (formalclk) { + pm.run_formal_clockgateff(); + } else { + pm.run_shiftadd(); + pm.run_shiftmul_right(); + pm.run_shiftmul_left(); + pm.run_muldiv(); + } } } } diff --git a/passes/pmgen/peepopt_formal_clockgateff.pmg b/passes/pmgen/peepopt_formal_clockgateff.pmg new file mode 100644 index 000000000..835f68bd8 --- /dev/null +++ b/passes/pmgen/peepopt_formal_clockgateff.pmg @@ -0,0 +1,59 @@ +pattern formal_clockgateff + +// Detects the most common clock gating pattern using a latch and replaces it +// with a functionally equivalent pattern based on a flip-flop. The latch +// based pattern has a combinational path from the enable input to output after +// clk2fflogic, but this is a stable loop and the flip-flop based pattern does +// not exhibit this. +// +// This optimization is suitable for formal to prevent false comb loops, but +// should not be used for synthesis where the latch is an intentional choice +// +// Latch style: +// always @* if (!clk_i) latched_en = en; +// assign gated_clk_o = latched_en & clk_i; +// +// Flip-flop style: +// always @(posedge clk) flopped_en <= en; +// assign gated_clk_o = flopped_en & clk_i; + +state clk en latched_en gated_clk +state latched_en_port_name + +match latch + select latch->type == $dlatch + select param(latch, \WIDTH) == 1 + select param(latch, \EN_POLARITY).as_bool() == false + set clk port(latch, \EN) + set en port(latch, \D) + set latched_en port(latch, \Q) +endmatch + +match and_gate + select and_gate->type.in($and, $logic_and) + select param(and_gate, \A_WIDTH) == 1 + select param(and_gate, \B_WIDTH) == 1 + select param(and_gate, \Y_WIDTH) == 1 + choice clk_port {\A, \B} + define latch_port {clk_port == \A ? \B : \A} + index port(and_gate, clk_port) === clk + index port(and_gate, latch_port) === latched_en + set gated_clk port(and_gate, \Y) + set latched_en_port_name latch_port +endmatch + +code + log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n", + log_id(module), log_id(latch), log_id(and_gate)); + + // Add a flip-flop and rewire the AND gate to use the output of this flop + // instead of the latch. We don't delete the latch in case its output is + // used to drive other nodes. If it isn't, it will be trivially removed by + // clean + SigSpec flopped_en = module->addWire(NEW_ID); + module->addDff(NEW_ID, clk, en, flopped_en, true, latch->get_src_attribute()); + and_gate->setPort(latched_en_port_name, flopped_en); + did_something = true; + + accept; +endcode From 236c69bed440ca9456c0c9c609e5ee6839322be8 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 7 Aug 2024 09:59:44 +0100 Subject: [PATCH 006/240] clk2fflogic: run peepopt -formalclk before processing design * this attempts to rewrite clock gating patterns into a form that is less likely to introduce combinational loops with clk2fflogic * can be disabled with -nopeepopt which is useful for testing clk2fflogic --- passes/sat/clk2fflogic.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index bcefa7d8f..348bab727 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -51,6 +51,10 @@ struct Clk2fflogicPass : public Pass { log(" -nolower\n"); log(" Do not automatically run 'chformal -lower' to lower $check cells.\n"); log("\n"); + log(" -nopeepopt\n"); + log(" Do not automatically run 'peepopt -formalclk' to rewrite clock patterns\n"); + log(" to more formal friendly forms.\n"); + log("\n"); } // Active-high sampled and current value of a level-triggered control signal. Initial sampled values is low/non-asserted. SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) { @@ -121,6 +125,7 @@ struct Clk2fflogicPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { bool flag_nolower = false; + bool flag_nopeepopt = false; log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n"); @@ -131,10 +136,20 @@ struct Clk2fflogicPass : public Pass { flag_nolower = true; continue; } + if (args[argidx] == "-nopeepopt") { + flag_nopeepopt = true; + continue; + } break; } extra_args(args, argidx, design); + if (!flag_nopeepopt) { + log_push(); + Pass::call(design, "peepopt -formalclk"); + log_pop(); + } + bool have_check_cells = false; for (auto module : design->selected_modules()) From b6ceff2aab27c988b7de8e072eb4bc07d1637e75 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 7 Aug 2024 09:59:18 +0100 Subject: [PATCH 007/240] peepopt clockgateff: add testcase --- tests/various/peepopt_formal.ys | 45 +++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 tests/various/peepopt_formal.ys diff --git a/tests/various/peepopt_formal.ys b/tests/various/peepopt_formal.ys new file mode 100644 index 000000000..52bf3c67f --- /dev/null +++ b/tests/various/peepopt_formal.ys @@ -0,0 +1,45 @@ +read_verilog -sv < Date: Tue, 27 Aug 2024 08:50:10 +0300 Subject: [PATCH 008/240] -y flag for libyosys Python scripts This adds a Python equivalent to the `-c` option, where scripts importing `libyosys` can be imported and used. Most of the work for this was already done to enable Python passes a couple years back, so this is a relatively small changeset. --- kernel/driver.cc | 44 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 1e4cd0052..bd32872a2 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -241,6 +241,7 @@ int main(int argc, char **argv) std::string topmodule = ""; std::string perffile = ""; bool scriptfile_tcl = false; + bool scriptfile_python = false; bool print_banner = true; bool print_stats = true; bool call_abort = false; @@ -305,6 +306,11 @@ int main(int argc, char **argv) printf("\n"); printf(" -C\n"); printf(" enters TCL interatcive shell mode\n"); +#endif +#ifdef WITH_PYTHON + printf("\n"); + printf(" -y python_scriptfile\n"); + printf(" execute the python script"); #endif printf("\n"); printf(" -p command\n"); @@ -379,7 +385,7 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "MXAQTVCSgm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:r:D:P:E:x:B:")) != -1) + while ((opt = getopt(argc, argv, "MXAQTVCSgm:f:Hh:b:o:p:l:L:qv:tds:c:y:W:w:e:r:D:P:E:x:B:")) != -1) { switch (opt) { @@ -464,11 +470,19 @@ int main(int argc, char **argv) case 's': scriptfile = optarg; scriptfile_tcl = false; + scriptfile_python = false; run_shell = false; break; case 'c': scriptfile = optarg; scriptfile_tcl = true; + scriptfile_python = false; + run_shell = false; + break; + case 'y': + scriptfile = optarg; + scriptfile_tcl = false; + scriptfile_python = true; run_shell = false; break; case 'W': @@ -607,8 +621,9 @@ int main(int argc, char **argv) run_pass(vdef_cmd); } - if (scriptfile.empty() || !scriptfile_tcl) { - // Without a TCL script, arguments following '--' are also treated as frontend files + if (scriptfile.empty() || (!scriptfile_tcl && !scriptfile_python)) { + // Without a TCL or Python script, arguments following '--' are also + // treated as frontend files for (int i = optind; i < argc; ++i) frontend_files.push_back(argv[i]); } @@ -636,7 +651,28 @@ int main(int argc, char **argv) if (Tcl_EvalFile(interp, scriptfile.c_str()) != TCL_OK) log_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp())); #else - log_error("Can't exectue TCL script: this version of yosys is not built with TCL support enabled.\n"); + log_error("Can't execute TCL script: this version of yosys is not built with TCL support enabled.\n"); +#endif + } else if (scriptfile_python) { +#ifdef WITH_PYTHON + PyObject *sys = PyImport_ImportModule("sys"); + PyObject *new_argv = PyList_New(argc - optind + 1); + PyList_SetItem(new_argv, 0, PyUnicode_FromString(scriptfile.c_str())); + for (int i = optind; i < argc; ++i) + PyList_SetItem(new_argv, i - optind + 1, PyUnicode_FromString(argv[i])); + + PyObject *old_argv = PyObject_GetAttrString(sys, "argv"); + PyObject_SetAttrString(sys, "argv", new_argv); + Py_DECREF(old_argv); + + FILE *scriptfp = fopen(scriptfile.c_str(), "r"); + if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) { + log_error("Python interpreter encountered an error:\n"); + log_flush(); + PyErr_Print(); + } +#else + log_error("Can't execute Python script: this version of yosys is not built with Python support enabled.\n"); #endif } else run_frontend(scriptfile, "script"); From 738b5eef0bcbf04eff1a263fd8177c9e24ed02da Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Tue, 10 Sep 2024 13:41:04 +0300 Subject: [PATCH 009/240] Add dirname of script file to sys.path This matches the behavior of running a Python interpreter, where the first element of sys.path is the dirname of the script being run. This allows importing of files and modules in the same directory without messing with PYTHONPATH or similar. --- kernel/driver.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index bd32872a2..0e0a8fa7a 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -660,11 +660,13 @@ int main(int argc, char **argv) PyList_SetItem(new_argv, 0, PyUnicode_FromString(scriptfile.c_str())); for (int i = optind; i < argc; ++i) PyList_SetItem(new_argv, i - optind + 1, PyUnicode_FromString(argv[i])); - + PyObject *old_argv = PyObject_GetAttrString(sys, "argv"); PyObject_SetAttrString(sys, "argv", new_argv); Py_DECREF(old_argv); - + + PyRun_SimpleString(("import os;sys.path.insert(0, os.path.dirname(os.path.abspath(\""+scriptfile+"\")))").c_str()); + FILE *scriptfp = fopen(scriptfile.c_str(), "r"); if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) { log_error("Python interpreter encountered an error:\n"); From 8dac27108efdb17313fbeb0a96b1eaae0ecaf2b7 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Wed, 11 Sep 2024 21:39:37 +0300 Subject: [PATCH 010/240] Typos --- kernel/driver.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 0e0a8fa7a..d30b19c96 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -305,12 +305,12 @@ int main(int argc, char **argv) printf(" execute the commands in the tcl script file (see 'help tcl' for details)\n"); printf("\n"); printf(" -C\n"); - printf(" enters TCL interatcive shell mode\n"); + printf(" enters TCL interactive shell mode\n"); #endif #ifdef WITH_PYTHON printf("\n"); printf(" -y python_scriptfile\n"); - printf(" execute the python script"); + printf(" execute a python script with libyosys available as a built-in module\n"); #endif printf("\n"); printf(" -p command\n"); From 4cfdb7ab5031c40c5804612e5c84613c060b0977 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 10 Sep 2024 20:42:55 +0200 Subject: [PATCH 011/240] Adjust operation naming in aigmap test --- tests/techmap/aigmap.ys | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/techmap/aigmap.ys b/tests/techmap/aigmap.ys index 6f6cdd1f2..deec440e2 100644 --- a/tests/techmap/aigmap.ys +++ b/tests/techmap/aigmap.ys @@ -84,14 +84,14 @@ assign name``_y2 = op name``_a2; `BIOP(xnor, ~^, 3, 3, 3) `BIOP(logic_and, &&, 3, 3, 1) `BIOP(logic_or, ||, 3, 3, 1) -`BIOP(logic_eq, ==, 3, 3, 1) -`BIOP(logic_ne, !=, 3, 3, 1) -`BIOP(logic_lt, <, 3, 3, 1) -`BIOP(logic_le, <=, 3, 3, 1) -`BIOP(logic_gt, >, 3, 3, 1) -`BIOP(logic_ge, >=, 3, 3, 1) +`BIOP(eq, ==, 3, 3, 1) +`BIOP(ne, !=, 3, 3, 1) +`BIOP(lt, <, 3, 3, 1) +`BIOP(le, <=, 3, 3, 1) +`BIOP(gt, >, 3, 3, 1) +`BIOP(ge, >=, 3, 3, 1) `UNOP(pos, +, 3) -`UNOP(neg, ~, 3) +`UNOP(not, ~, 3) `UNOP_REDUCE(logic_not, !, 3) `UNOP_REDUCE(reduce_and, &, 3) `UNOP_REDUCE(reduce_or, |, 3) From fb26945a20a5d20585567f90a9d1eaad279f78be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 10 Sep 2024 20:53:23 +0200 Subject: [PATCH 012/240] Start an 'aiger2' backend --- backends/aiger2/Makefile.inc | 1 + backends/aiger2/aiger.cc | 593 +++++++++++++++++++++++++++++++++++ tests/various/aiger2.ys | 156 +++++++++ 3 files changed, 750 insertions(+) create mode 100644 backends/aiger2/Makefile.inc create mode 100644 backends/aiger2/aiger.cc create mode 100644 tests/various/aiger2.ys diff --git a/backends/aiger2/Makefile.inc b/backends/aiger2/Makefile.inc new file mode 100644 index 000000000..494b8d6c6 --- /dev/null +++ b/backends/aiger2/Makefile.inc @@ -0,0 +1 @@ +OBJS += backends/aiger2/aiger.o diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc new file mode 100644 index 000000000..64cde2de4 --- /dev/null +++ b/backends/aiger2/aiger.cc @@ -0,0 +1,593 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) Martin PoviĊĦer + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// TODOs: +// - gracefully handling inout ports (an error message probably) + +#include "kernel/register.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa) + +#define REDUCE_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool) + +#define LOGIC_OPS ID($logic_and), ID($logic_or), ID($logic_not) + +#define GATE_OPS ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), \ + ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), \ + ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_) + +// TODO +//#define ARITH_OPS ID($add), ID($sub), ID($lt), ID($le), ID($ge), ID($gt), ID($neg) + +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS /*, ARITH_OPS*/ + +template +struct Index { + struct HierCursor; + struct ModuleInfo { + Module *module; + int len; + dict windices; + dict suboffsets; + + bool indexing = false; + bool indexed = false; + }; + + dict modules; + + int index_wires(ModuleInfo &info, RTLIL::Module *m) + { + int sum = 0; + for (auto w : m->wires()) { + info.windices[w] = sum; + sum += w->width; + } + return sum; + } + + int index_module(RTLIL::Module *m) + { + ModuleInfo &info = modules[m]; + + if (info.indexed) + return info.len; + + if (info.indexing && !info.indexed) + log_error("Hierarchy error\n"); + + info.module = m; + int pos = index_wires(info, m); + + for (auto cell : m->cells()) { + if (cell->type.in(KNOWN_OPS)) + continue; + + Module *submodule = m->design->module(cell->type); + if (!submodule || submodule->get_blackbox_attribute()) + log_error("Unsupported cell type: %s (%s in %s)\n", + log_id(cell->type), log_id(cell), log_id(m)); + info.suboffsets[cell] = pos; + pos += index_module(submodule); + } + + info.len = pos; + return info.len; + } + + Design *design; + Module *top; + ModuleInfo *top_minfo; + std::vector lits; + + Index(RTLIL::Module *top) + : design(top->design), top(top) + { + modules.reserve(top->design->modules().size()); + int nlits = index_module(top); + log_debug("allocating for %d literals\n", nlits); + lits.resize(nlits, Writer::empty_lit()); + top_minfo = &modules.at(top); + } + + bool const_folding = false; + + Lit AND(Lit a, Lit b) + { + if (const_folding) { + if (a == Writer::CONST_FALSE || b == Writer::CONST_FALSE) + return Writer::CONST_FALSE; + if (a == Writer::CONST_TRUE) + return b; + if (b == Writer::CONST_TRUE) + return a; + } + + return (static_cast(this))->emit_gate(a, b); + } + + Lit NOT(Lit lit) + { + return Writer::negate(lit); + } + + Lit OR(Lit a, Lit b) + { + return NOT(AND(NOT(a), NOT(b))); + } + + Lit MUX(Lit a, Lit b, Lit s) + { + if (const_folding) { + if (a == b) + return a; + if (s == Writer::CONST_FALSE) + return a; + if (s == Writer::CONST_TRUE) + return b; + } + + return OR(AND(a, NOT(s)), AND(b, s)); + } + + Lit XOR(Lit a, Lit b) + { + return OR(AND(a, NOT(b)), AND(NOT(a), b)); + } + + Lit impl_op(HierCursor &cursor, Cell *cell, IdString oport, int obit) + { + if (cell->type.in(REDUCE_OPS, LOGIC_OPS) && obit != 0) { + return Writer::CONST_FALSE; + } else if (cell->type.in(REDUCE_OPS, ID($logic_not))) { + SigSpec inport = cell->getPort(ID::A); + + log_assert(inport.size() > 0); // TODO + + Lit acc = visit(cursor, inport[0]); + for (int i = 1; i < inport.size(); i++) { + Lit l = visit(cursor, inport[i]); + if (cell->type == ID($reduce_and)) { + acc = AND(acc, l); + } else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) { + acc = OR(acc, l); + } else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { + acc = XOR(acc, l); + } + } + + if (!cell->type.in(ID($reduce_xnor), ID($logic_not))) + return acc; + else + return NOT(acc); + } else if (cell->type.in(ID($logic_and), ID($logic_or))) { + SigSpec aport = cell->getPort(ID::A); + SigSpec bport = cell->getPort(ID::B); + + log_assert(aport.size() > 0 && bport.size() > 0); // TODO + + Lit a = visit(cursor, aport[0]); + for (int i = 1; i < aport.size(); i++) { + Lit l = visit(cursor, aport[i]); + a = OR(a, l); + } + + Lit b = visit(cursor, bport[0]); + for (int i = 1; i < bport.size(); i++) { + Lit l = visit(cursor, bport[i]); + b = OR(b, l); + } + + if (cell->type == ID($logic_and)) + return AND(a, b); + else if (cell->type == ID($logic_or)) + return OR(a, b); + else + log_abort(); + } else if (cell->type.in(BITWISE_OPS, GATE_OPS)) { + SigSpec aport = cell->getPort(ID::A); + Lit a; + if (obit < aport.size()) { + a = visit(cursor, aport[obit]); + } else { + if (cell->getParam(ID::A_SIGNED).as_bool()) + a = visit(cursor, aport.msb()); + else + a = Writer::CONST_FALSE; + } + + if (cell->type.in(ID($buf), ID($_BUF_))) { + return a; + } else if (cell->type.in(ID($not), ID($_NOT_))) { + return NOT(a); + } else { + SigSpec bport = cell->getPort(ID::B); + Lit b; + if (obit < bport.size()) { + b = visit(cursor, bport[obit]); + } else { + if (cell->getParam(ID::B_SIGNED).as_bool()) + b = visit(cursor, bport.msb()); + else + b = Writer::CONST_FALSE; + } + + if (cell->type.in(ID($and), ID($_AND_))) { + return AND(a, b); + } else if (cell->type.in(ID($_NAND_))) { + return NOT(AND(a, b)); + } else if (cell->type.in(ID($or), ID($_OR_))) { + return OR(a, b); + } else if (cell->type.in(ID($_NOR_))) { + return NOT(OR(a, b)); + } else if (cell->type.in(ID($xor), ID($_XOR_))) { + return XOR(a, b); + } else if (cell->type.in(ID($xnor), ID($_XNOR_))) { + return NOT(XOR(a, b)); + } else if (cell->type.in(ID($_ANDNOT_))) { + return AND(a, NOT(b)); + } else if (cell->type.in(ID($_ORNOT_))) { + return OR(a, NOT(b)); + } else if (cell->type.in(ID($mux), ID($_MUX_))) { + Lit s = visit(cursor, cell->getPort(ID::S)); + return MUX(a, b, s); + } else if (cell->type.in(ID($_NMUX_))) { + Lit s = visit(cursor, cell->getPort(ID::S)[obit]); + return NOT(MUX(a, b, s)); + } else if (cell->type.in(ID($fa))) { + Lit c = visit(cursor, cell->getPort(ID::C)[obit]); + Lit ab = XOR(a, b); + if (oport == ID::Y) { + return XOR(ab, c); + } else /* oport == ID::X */ { + return OR(AND(a, b), AND(c, ab)); + } + } else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { + Lit c, d; + + c = visit(cursor, cell->getPort(ID::C)[obit]); + if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_))) + d = visit(cursor, cell->getPort(ID::D)[obit]); + else + d = cell->type == ID($_AOI3_) ? 1 : 0; + + if (/* aoi */ cell->type.in(ID($_AOI3_), ID($_AOI4_))) + return NOT(OR(AND(a, b), AND(c, d))); + else + return NOT(AND(OR(a, b), OR(c, d))); + } else { + log_abort(); + } + } + } else { + log_abort(); + } + } + + struct HierCursor { + typedef std::pair Level; + std::vector levels; + int instance_offset = 0; + + HierCursor(ModuleInfo &top) + { + levels.push_back(Level(top, nullptr)); + } + + ModuleInfo ¤t_minfo() + { + log_assert(!levels.empty()); + return levels.back().first; + } + + int bitwire_index(SigBit bit) + { + log_assert(bit.wire != nullptr); + return instance_offset + current_minfo().windices[bit.wire] + bit.offset; + } + + Cell *exit() + { + log_assert(levels.size() > 1); + Cell *instance = levels.back().second; + + levels.pop_back(); + instance_offset -= current_minfo().suboffsets.at(instance); + + // return the instance we just exited + return instance; + } + + Module *enter(Index &index, Cell *cell) + { + Design *design = index.design; + auto &minfo = current_minfo(); + log_assert(minfo.suboffsets.count(cell)); + Module *def = design->module(cell->type); + log_assert(def); + levels.push_back(Level(index.modules.at(def), cell)); + instance_offset += minfo.suboffsets.at(cell); + + // return the module definition we just entered + return def; + } + }; + + int visit(HierCursor &cursor, SigBit bit) + { + if (!bit.wire) { + if (bit == State::S1) + return Writer::CONST_TRUE; + else if (bit == State::S0) + return Writer::CONST_FALSE; + else + log_error("Unhandled state %s\n", log_signal(bit)); + } + + int idx = cursor.bitwire_index(bit); + if (lits[idx] != Writer::empty_lit()) { + // literal already assigned + return lits[idx]; + } + + Lit ret; + if (!bit.wire->port_input) { + // an output of a cell + Cell *driver = bit.wire->driverCell(); + + if (driver->type.in(KNOWN_OPS)) { + ret = impl_op(cursor, driver, bit.wire->driverPort(), bit.offset); + } else { + Module *def = cursor.enter(*this, driver); + { + IdString portname = bit.wire->driverPort(); + Wire *w = def->wire(portname); + if (!w) + log_error("Output port %s on instance %s of %s doesn't exist\n", + log_id(portname), log_id(driver), log_id(def)); + if (bit.offset >= w->width) + log_error("Bit position %d of output port %s on instance %s of %s is out of range (port has width %d)\n", + bit.offset, log_id(portname), log_id(driver), log_id(def), w->width); + ret = visit(cursor, SigBit(w, bit.offset)); + } + cursor.exit(); + } + + } else { + // a module input: we cannot be the top module, otherwise + // the branch for pre-existing literals would have been taken + log_assert(cursor.levels.size() > 1); + + // step into the upper module + Cell *instance = cursor.exit(); + { + IdString portname = bit.wire->name; + if (!instance->hasPort(portname)) + log_error("Input port %s on instance %s of %s unconnected\n", + log_id(portname), log_id(instance), log_id(instance->type)); + auto &port = instance->getPort(portname); + if (bit.offset >= port.size()) + log_error("Bit %d of input port %s on instance %s of %s unconnected\n", + bit.offset, log_id(portname), log_id(instance), log_id(instance->type)); + ret = visit(cursor, port[bit.offset]); + } + cursor.enter(*this, instance); + } + + lits[idx] = ret; + return ret; + } + + void set_top_port(SigBit bit, Lit lit) + { + log_assert(bit.wire); + log_assert(bit.wire->module == top); + log_assert(bit.wire->port_input); + + lits[top_minfo->windices[bit.wire] + bit.offset] = lit; + } + + Lit get_top_port(SigBit bit) + { + HierCursor cursor(*top_minfo); + Lit ret = visit(cursor, bit); + log_assert(cursor.levels.size() == 1); + log_assert(cursor.instance_offset == 0); + return ret; + } +}; + +struct AigerWriter : Index { + typedef unsigned int Lit; + + const static Lit CONST_FALSE = 0; + const static Lit CONST_TRUE = 1; + + // for some reason having a 'const static int EMPTY_LIT' + // led to linkage errors + static Lit empty_lit() + { + return 0x80000000; + } + + static Lit negate(Lit lit) { + return lit ^ 1; + } + + std::ostream *f; + Lit lit_counter; + int ninputs, nlatches, noutputs, nands; + + void encode(int delta) + { + log_assert(delta >= 0); + unsigned int x = delta; + while (x & ~0x7f) { + f->put((x & 0x7f) | 0x80); + x = x >> 7; + } + f->put(x); + } + + Lit emit_gate(Lit a, Lit b) + { + Lit out = lit_counter; + nands++; + lit_counter += 2; + + if (a < b) std::swap(a, b); + encode(out - a); + encode(a - b); + return out; + } + + void reset_counters() + { + lit_counter = 2; + ninputs = nlatches = noutputs = nands = 0; + } + + void write_header() { + log_assert(lit_counter == (ninputs + nlatches + nands) * 2 + 2); + + char buf[128]; + snprintf(buf, sizeof(buf) - 1, "aig %08d %08d %08d %08d %08d\n", + ninputs + nlatches + nands, ninputs, nlatches, noutputs, nands); + f->seekp(0); + f->write(buf, strlen(buf)); + } + + void write(std::ostream *f) { + reset_counters(); + + // populate inputs + std::vector inputs; + for (auto w : top->wires()) + if (w->port_input) + for (int i = 0; i < w->width; i++) { + set_top_port(SigBit(w, i), lit_counter); + inputs.push_back(SigBit(w, i)); + lit_counter += 2; + ninputs++; + } + + this->f = f; + // start with the header + write_header(); + // insert padding where output literals will go (once known) + for (auto w : top->wires()) + if (w->port_output) { + for (auto bit : SigSpec(w)) { + (void) bit; + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", 0); + f->write(buf, strlen(buf)); + noutputs++; + } + } + auto data_start = f->tellp(); + + // now the guts + std::vector> outputs; + for (auto w : top->wires()) + if (w->port_output) { + for (auto bit : SigSpec(w)) + outputs.push_back({bit, get_top_port(bit)}); + } + auto data_end = f->tellp(); + + // revisit header and the list of outputs + write_header(); + for (auto pair : outputs) { + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", pair.second); + f->write(buf, strlen(buf)); + } + // double check we arrived at the same offset for the + // main data section + log_assert(data_start == f->tellp()); + + f->seekp(data_end); + int i = 0; + for (auto pair : outputs) { + if (pair.first.is_wire()) { + char buf[32]; + snprintf(buf, sizeof(buf) - 1, "o%d ", i); + f->write(buf, strlen(buf)); + std::string name = RTLIL::unescape_id(pair.first.wire->name); + f->write(name.data(), name.size()); + f->put('\n'); + } + i++; + } + i = 0; + for (auto bit : inputs) { + if (bit.is_wire()) { + char buf[32]; + snprintf(buf, sizeof(buf) - 1, "i%d ", i); + f->write(buf, strlen(buf)); + std::string name = RTLIL::unescape_id(bit.wire->name); + f->write(name.data(), name.size()); + f->put('\n'); + } + i++; + } + } + + AigerWriter(RTLIL::Module *top) + : Index(top) {} +}; + +struct Aiger2Backend : Backend { + Aiger2Backend() : Backend("aiger2", "write design to AIGER file (new)") + { + experimental(); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing AIGER2 backend.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + break; + } + extra_args(f, filename, args, argidx); + + Module *top = design->top_module(); + + if (!top || !design->selected_whole_module(top)) + log_cmd_error("No top module selected\n"); + + design->bufNormalize(true); + AigerWriter writer(top); + writer.write(f); + + // we are leaving the sacred land, un-bufnormalize + // (if not, this will lead to bugs: the buf-normalized + // flag must not be kept on past the code that can work + // with it) + design->bufNormalize(false); + } +} Aiger2Backend; + +PRIVATE_NAMESPACE_END diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys new file mode 100644 index 000000000..61e6d275a --- /dev/null +++ b/tests/various/aiger2.ys @@ -0,0 +1,156 @@ +read_verilog -icells < Date: Wed, 11 Sep 2024 11:01:38 +0200 Subject: [PATCH 013/240] aiger2: Support `$pos` --- backends/aiger2/aiger.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 64cde2de4..89a23ff3f 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -38,7 +38,7 @@ PRIVATE_NAMESPACE_BEGIN // TODO //#define ARITH_OPS ID($add), ID($sub), ID($lt), ID($le), ID($ge), ID($gt), ID($neg) -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS /*, ARITH_OPS*/ +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos) /*, ARITH_OPS*/ template struct Index { @@ -203,7 +203,7 @@ struct Index { return OR(a, b); else log_abort(); - } else if (cell->type.in(BITWISE_OPS, GATE_OPS)) { + } else if (cell->type.in(BITWISE_OPS, GATE_OPS, ID($pos))) { SigSpec aport = cell->getPort(ID::A); Lit a; if (obit < aport.size()) { @@ -215,7 +215,7 @@ struct Index { a = Writer::CONST_FALSE; } - if (cell->type.in(ID($buf), ID($_BUF_))) { + if (cell->type.in(ID($buf), ID($pos), ID($_BUF_))) { return a; } else if (cell->type.in(ID($not), ID($_NOT_))) { return NOT(a); From 5671c101731c58c5285d2493527911fde67ec25b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 11:02:40 +0200 Subject: [PATCH 014/240] aiger2: Add strashing option --- backends/aiger2/aiger.cc | 41 +++++++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 89a23ff3f..533abc004 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -99,9 +99,15 @@ struct Index { ModuleInfo *top_minfo; std::vector lits; - Index(RTLIL::Module *top) - : design(top->design), top(top) + Index() { + } + + void setup(RTLIL::Module *top) + { + design = top->design; + this->top = top; + modules.reserve(top->design->modules().size()); int nlits = index_module(top); log_debug("allocating for %d literals\n", nlits); @@ -109,7 +115,9 @@ struct Index { top_minfo = &modules.at(top); } - bool const_folding = false; + bool const_folding = true; + bool strashing = false; + dict, int> cache; Lit AND(Lit a, Lit b) { @@ -122,7 +130,20 @@ struct Index { return a; } - return (static_cast(this))->emit_gate(a, b); + if (!strashing) { + return (static_cast(this))->emit_gate(a, b); + } else { + if (a < b) std::swap(a, b); + auto pair = std::make_pair(a, b); + + if (!cache.count(pair)) { + Lit nl = (static_cast(this))->emit_gate(a, b); + cache[pair] = nl; + return nl; + } else { + return cache.at(pair); + } + } } Lit NOT(Lit lit) @@ -552,9 +573,6 @@ struct AigerWriter : Index { i++; } } - - AigerWriter(RTLIL::Module *top) - : Index(top) {} }; struct Aiger2Backend : Backend { @@ -568,8 +586,13 @@ struct Aiger2Backend : Backend { log_header(design, "Executing AIGER2 backend.\n"); size_t argidx; + AigerWriter writer; + writer.const_folding = true; for (argidx = 1; argidx < args.size(); argidx++) { - break; + if (args[argidx] == "-strash") + writer.strashing = true; + else + break; } extra_args(f, filename, args, argidx); @@ -579,7 +602,7 @@ struct Aiger2Backend : Backend { log_cmd_error("No top module selected\n"); design->bufNormalize(true); - AigerWriter writer(top); + writer.setup(top); writer.write(f); // we are leaving the sacred land, un-bufnormalize From de8a2fb936e25eb54074595b129f02fc14144fe2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 11:03:14 +0200 Subject: [PATCH 015/240] aiger2: Fix duplicate symbols on multibit ports --- backends/aiger2/aiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 533abc004..a49b5bf1e 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -550,7 +550,7 @@ struct AigerWriter : Index { f->seekp(data_end); int i = 0; for (auto pair : outputs) { - if (pair.first.is_wire()) { + if (SigSpec(pair.first).is_wire()) { char buf[32]; snprintf(buf, sizeof(buf) - 1, "o%d ", i); f->write(buf, strlen(buf)); @@ -562,7 +562,7 @@ struct AigerWriter : Index { } i = 0; for (auto bit : inputs) { - if (bit.is_wire()) { + if (SigSpec(bit).is_wire()) { char buf[32]; snprintf(buf, sizeof(buf) - 1, "i%d ", i); f->write(buf, strlen(buf)); From e59387e5a9538ee32fdd3f8554e350d506b7b48b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 11:10:43 +0200 Subject: [PATCH 016/240] aiger2: Add `aigsize` as a second user of index --- backends/aiger2/aiger.cc | 64 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index a49b5bf1e..075bc129d 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -613,4 +613,68 @@ struct Aiger2Backend : Backend { } } Aiger2Backend; +struct AIGCounter : Index { + typedef int Lit; + const static Lit CONST_FALSE = -1; + const static Lit CONST_TRUE = 1; + static Lit empty_lit() { return 0; } + static Lit negate(Lit lit) { return -lit; } + int nvars = 1; + int ngates = 0; + + Lit emit_gate([[maybe_unused]] Lit a, [[maybe_unused]] Lit b) + { + ngates++; + return ++nvars; + } + + void count() { + // populate inputs + for (auto w : top->wires()) + if (w->port_input) + for (int i = 0; i < w->width; i++) + set_top_port(SigBit(w, i), ++nvars); + + for (auto w : top->wires()) + if (w->port_output) { + for (auto bit : SigSpec(w)) + (void) get_top_port(bit); + } + } +}; + +struct AigsizePass : Pass { + AigsizePass() : Pass("aigsize", "estimate AIG size for design") {} + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing AIGSIZE pass. (size design AIG)\n"); + + size_t argidx; + AIGCounter counter; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-strash") + counter.strashing = true; + else + break; + } + extra_args(args, argidx, design); + + Module *top = design->top_module(); + + if (!top || !design->selected_whole_module(top)) + log_cmd_error("No top module selected\n"); + + design->bufNormalize(true); + counter.setup(top); + counter.count(); + log("Counted %d gates\n", counter.ngates); + + // we are leaving the sacred land, un-bufnormalize + // (if not, this will lead to bugs: the buf-normalized + // flag must not be kept on past the code that can work + // with it) + design->bufNormalize(false); + } +} AigsizePass; + PRIVATE_NAMESPACE_END From d7128cb78787a6a5299c1c1c126ec673e8d440e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 21:08:03 +0200 Subject: [PATCH 017/240] aiger2: Use shorthands --- backends/aiger2/aiger.cc | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 075bc129d..873a44129 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -42,6 +42,9 @@ PRIVATE_NAMESPACE_BEGIN template struct Index { + static constexpr Lit CFALSE = Writer::CONST_FALSE; + static constexpr Lit CTRUE = Writer::CONST_TRUE; + struct HierCursor; struct ModuleInfo { Module *module; @@ -122,11 +125,11 @@ struct Index { Lit AND(Lit a, Lit b) { if (const_folding) { - if (a == Writer::CONST_FALSE || b == Writer::CONST_FALSE) - return Writer::CONST_FALSE; - if (a == Writer::CONST_TRUE) + if (a == CFALSE || b == CFALSE) + return CFALSE; + if (a == CTRUE) return b; - if (b == Writer::CONST_TRUE) + if (b == CTRUE) return a; } @@ -161,9 +164,9 @@ struct Index { if (const_folding) { if (a == b) return a; - if (s == Writer::CONST_FALSE) + if (s == CFALSE) return a; - if (s == Writer::CONST_TRUE) + if (s == CTRUE) return b; } @@ -233,7 +236,7 @@ struct Index { if (cell->getParam(ID::A_SIGNED).as_bool()) a = visit(cursor, aport.msb()); else - a = Writer::CONST_FALSE; + a = CFALSE; } if (cell->type.in(ID($buf), ID($pos), ID($_BUF_))) { @@ -249,7 +252,7 @@ struct Index { if (cell->getParam(ID::B_SIGNED).as_bool()) b = visit(cursor, bport.msb()); else - b = Writer::CONST_FALSE; + b = CFALSE; } if (cell->type.in(ID($and), ID($_AND_))) { @@ -357,9 +360,9 @@ struct Index { { if (!bit.wire) { if (bit == State::S1) - return Writer::CONST_TRUE; + return CTRUE; else if (bit == State::S0) - return Writer::CONST_FALSE; + return CFALSE; else log_error("Unhandled state %s\n", log_signal(bit)); } From 8e29675a23539c958b2024fbc00021708a3dcdb3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 21:08:41 +0200 Subject: [PATCH 018/240] aiger2: Support `$bwmux`, comparison operators --- backends/aiger2/aiger.cc | 69 ++++++++++++++++++++++++++++++++++++---- tests/various/aiger2.ys | 15 +++++++-- 2 files changed, 76 insertions(+), 8 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 873a44129..bc22dac94 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -25,7 +25,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa) +#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa), \ + ID($bwmux) #define REDUCE_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool) @@ -35,10 +36,12 @@ PRIVATE_NAMESPACE_BEGIN ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), \ ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_) -// TODO -//#define ARITH_OPS ID($add), ID($sub), ID($lt), ID($le), ID($ge), ID($gt), ID($neg) +#define CMP_OPS ID($eq), ID($ne), ID($lt), ID($le), ID($ge), ID($gt) -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos) /*, ARITH_OPS*/ +// TODO +//#define ARITH_OPS ID($add), ID($sub), ID($neg) + +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS /*, ARITH_OPS*/ template struct Index { @@ -178,10 +181,61 @@ struct Index { return OR(AND(a, NOT(b)), AND(NOT(a), b)); } + Lit XNOR(Lit a, Lit b) + { + return NOT(OR(AND(a, NOT(b)), AND(NOT(a), b))); + } + + Lit CARRY(Lit a, Lit b, Lit c) + { + if (const_folding) { + if (c == CTRUE) { + return OR(a, b); + } else if (c == CFALSE) { + return AND(a, b); + } + } + return OR(AND(a, b), AND(c, OR(a, b))); + } + Lit impl_op(HierCursor &cursor, Cell *cell, IdString oport, int obit) { - if (cell->type.in(REDUCE_OPS, LOGIC_OPS) && obit != 0) { - return Writer::CONST_FALSE; + if (cell->type.in(REDUCE_OPS, LOGIC_OPS, CMP_OPS) && obit != 0) { + return CFALSE; + } else if (cell->type.in(CMP_OPS)) { + SigSpec aport = cell->getPort(ID::A); + bool asigned = cell->getParam(ID::A_SIGNED).as_bool(); + SigSpec bport = cell->getPort(ID::B); + bool bsigned = cell->getParam(ID::B_SIGNED).as_bool(); + + int width = std::max(aport.size(), bport.size()) + 1; + aport.extend_u0(width, asigned); + bport.extend_u0(width, bsigned); + + if (cell->type.in(ID($eq), ID($ne))) { + int carry = CTRUE; + for (int i = 0; i < width; i++) { + Lit a = visit(cursor, aport[i]); + Lit b = visit(cursor, bport[i]); + carry = AND(carry, XNOR(a, b)); + } + return (cell->type == ID($eq)) ? carry : /* $ne */ NOT(carry); + } else if (cell->type.in(ID($lt), ID($le), ID($gt), ID($ge))) { + if (cell->type.in(ID($gt), ID($ge))) + std::swap(aport, bport); + int carry = cell->type.in(ID($le), ID($ge)) ? CFALSE : CTRUE; + Lit a, b; + // TODO: this might not be the most economic structure; revisit at a later date + for (int i = 0; i < width; i++) { + a = visit(cursor, aport[i]); + b = visit(cursor, bport[i]); + if (i != width - 1) + carry = CARRY(a, NOT(b), carry); + } + return XOR(carry, XNOR(a, b)); + } else { + log_abort(); + } } else if (cell->type.in(REDUCE_OPS, ID($logic_not))) { SigSpec inport = cell->getPort(ID::A); @@ -274,6 +328,9 @@ struct Index { } else if (cell->type.in(ID($mux), ID($_MUX_))) { Lit s = visit(cursor, cell->getPort(ID::S)); return MUX(a, b, s); + } else if (cell->type.in(ID($bwmux))) { + Lit s = visit(cursor, cell->getPort(ID::S)[obit]); + return MUX(a, b, s); } else if (cell->type.in(ID($_NMUX_))) { Lit s = visit(cursor, cell->getPort(ID::S)[obit]); return NOT(MUX(a, b, s)); diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index 61e6d275a..5d8c6e848 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -83,6 +83,12 @@ assign name``_y2 = op name``_a2; `BIOP(xnor, ~^, 3, 3, 3) `BIOP(logic_and, &&, 4, 3, 1) `BIOP(logic_or, ||, 3, 3, 2) +`BIOP(eq, ==, 3, 3, 1) +`BIOP(ne, !=, 3, 3, 1) +`BIOP(lt, <, 3, 3, 1) +`BIOP(le, <=, 3, 3, 1) +`BIOP(gt, >, 3, 3, 1) +`BIOP(ge, >=, 3, 3, 1) `UNOP(not, ~, 3) `UNOP_REDUCE(logic_not, !, 3) `UNOP_REDUCE(reduce_and, &, 3) @@ -97,6 +103,11 @@ wire [1:0] fa_a, fa_b, fa_c, fa_x, fa_y; \$fa #( .WIDTH(2) ) fa(.A(fa_a), .B(fa_b), .C(fa_c), .X(fa_x), .Y(fa_y)); + +wire [1:0] bwmux_a, bwmux_b, bwmux_s, bwmux_y; +\$bwmux #( + .WIDTH(2) +) bwmux(.A(bwmux_a), .B(bwmux_b), .S(bwmux_s), .Y(bwmux_y)); endmodule EOF @@ -110,8 +121,8 @@ select -clear delete test read_aiger -module_name test aiger2_ops.aig select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D -miter -equiv -flatten gold test miter -sat -verify -prove trigger 0 miter +miter -equiv -make_outcmp -flatten gold test miter +sat -verify -show-ports -prove trigger 0 miter design -reset read_verilog -icells < Date: Wed, 11 Sep 2024 21:08:57 +0200 Subject: [PATCH 019/240] aiger2: Fix literal typing --- backends/aiger2/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index bc22dac94..0c787f11d 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -413,7 +413,7 @@ struct Index { } }; - int visit(HierCursor &cursor, SigBit bit) + Lit visit(HierCursor &cursor, SigBit bit) { if (!bit.wire) { if (bit == State::S1) From dbc937b2a7482d243b16c5de1f508eee71b19a59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 21:09:28 +0200 Subject: [PATCH 020/240] aiger2: Describe supported cells in help --- backends/aiger2/aiger.cc | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0c787f11d..34b9eb324 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -21,6 +21,7 @@ // - gracefully handling inout ports (an error message probably) #include "kernel/register.h" +#include "kernel/celltypes.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -641,7 +642,51 @@ struct Aiger2Backend : Backend { experimental(); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" write_aiger2 [options] [filename]\n"); + log("\n"); + log("Write the current design to an AIGER file.\n"); + log("\n"); + log("This command is able to ingest all combinational cells except for:\n"); + log("\n"); + pool supported = {KNOWN_OPS}; + CellTypes ct; + ct.setup_internals_eval(); + log(" "); + int col = 0; + for (auto pair : ct.cell_types) + if (!supported.count(pair.first)) { + if (col + pair.first.size() + 2 > 72) { + log("\n "); + col = 0; + } + col += pair.first.size() + 2; + log("%s, ", log_id(pair.first)); + } + log("\n"); + log("\n"); + log("And all combinational gates except for:\n"); + log("\n"); + CellTypes ct2; + ct2.setup_stdcells(); + log(" "); + col = 0; + for (auto pair : ct2.cell_types) + if (!supported.count(pair.first)) { + if (col + pair.first.size() + 2 > 72) { + log("\n "); + col = 0; + } + col += pair.first.size() + 2; + log("%s, ", log_id(pair.first)); + } + log("\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, Design *design) override { log_header(design, "Executing AIGER2 backend.\n"); From 9db1ca83fc80a6ffc6bab52cc70924304ed54c6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 21:15:17 +0200 Subject: [PATCH 021/240] aiger2: Drop `empty_lit()` as a function --- backends/aiger2/aiger.cc | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 34b9eb324..d300827d3 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -118,7 +118,7 @@ struct Index { modules.reserve(top->design->modules().size()); int nlits = index_module(top); log_debug("allocating for %d literals\n", nlits); - lits.resize(nlits, Writer::empty_lit()); + lits.resize(nlits, Writer::EMPTY_LIT); top_minfo = &modules.at(top); } @@ -426,7 +426,7 @@ struct Index { } int idx = cursor.bitwire_index(bit); - if (lits[idx] != Writer::empty_lit()) { + if (lits[idx] != Writer::EMPTY_LIT) { // literal already assigned return lits[idx]; } @@ -503,13 +503,7 @@ struct AigerWriter : Index { const static Lit CONST_FALSE = 0; const static Lit CONST_TRUE = 1; - - // for some reason having a 'const static int EMPTY_LIT' - // led to linkage errors - static Lit empty_lit() - { - return 0x80000000; - } + const static constexpr Lit EMPTY_LIT = std::numeric_limits::max(); static Lit negate(Lit lit) { return lit ^ 1; @@ -722,7 +716,7 @@ struct AIGCounter : Index { typedef int Lit; const static Lit CONST_FALSE = -1; const static Lit CONST_TRUE = 1; - static Lit empty_lit() { return 0; } + const static constexpr Lit EMPTY_LIT = 0; static Lit negate(Lit lit) { return -lit; } int nvars = 1; int ngates = 0; From 4976abb867c5e1dc0474975c46c966b238c5ce4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:16:15 +0200 Subject: [PATCH 022/240] read_liberty: Optionally import unit delay arcs --- frontends/liberty/liberty.cc | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 16fed54f2..e183cbf10 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -465,6 +465,9 @@ struct LibertyFrontend : public Frontend { log(" -setattr \n"); log(" set the specified attribute (to the value 1) on all loaded modules\n"); log("\n"); + log(" -unit_delay\n"); + log(" import combinational timing arcs under the unit delay model\n"); + log("\n"); } void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { @@ -475,6 +478,7 @@ struct LibertyFrontend : public Frontend { bool flag_ignore_miss_func = false; bool flag_ignore_miss_dir = false; bool flag_ignore_miss_data_latch = false; + bool flag_unit_delay = false; std::vector attributes; size_t argidx; @@ -514,6 +518,10 @@ struct LibertyFrontend : public Frontend { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; } + if (arg == "-unit_delay") { + flag_unit_delay = true; + continue; + } break; } extra_args(f, filename, args, argidx); @@ -652,6 +660,7 @@ struct LibertyFrontend : public Frontend { continue; RTLIL::Wire *wire = module->wires_.at(RTLIL::escape_id(node->args.at(0))); + log_assert(wire); if (dir && dir->value == "inout") { wire->port_input = true; @@ -690,6 +699,43 @@ struct LibertyFrontend : public Frontend { } module->connect(RTLIL::SigSig(wire, out_sig)); } + + if (flag_unit_delay) { + pool done; + + for (auto timing : node->children) + if (timing->id == "timing" && timing->args.empty()) { + auto type = timing->find("timing_type"); + auto related_pin = timing->find("related_pin"); + if (!type || type->value != "combinational" || !related_pin) + continue; + + Wire *related = module->wire(RTLIL::escape_id(related_pin->value)); + if (!related) + log_error("Failed to find related pin %s for timing of pin %s on %s\n", + related_pin->value.c_str(), log_id(wire), log_id(module)); + + if (done.count(related)) + continue; + + RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2)); + spec->setParam(ID::SRC_WIDTH, 1); + spec->setParam(ID::DST_WIDTH, 1); + spec->setParam(ID::T_FALL_MAX, 1000); + spec->setParam(ID::T_FALL_TYP, 1000); + spec->setParam(ID::T_FALL_MIN, 1000); + spec->setParam(ID::T_RISE_MAX, 1000); + spec->setParam(ID::T_RISE_TYP, 1000); + spec->setParam(ID::T_RISE_MIN, 1000); + spec->setParam(ID::SRC_DST_POL, false); + spec->setParam(ID::SRC_DST_PEN, false); + spec->setParam(ID::FULL, false); + spec->setPort(ID::EN, Const(1, 1)); + spec->setPort(ID::SRC, related); + spec->setPort(ID::DST, wire); + done.insert(related); + } + } } } From 31476e89b6524069b5ebd75e9e80700afdc58f3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:09:47 +0200 Subject: [PATCH 023/240] tests: Avoid temporary script file --- tests/liberty/.gitignore | 1 - tests/liberty/run-test.sh | 5 +---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore index bf5ba57dc..8763aaac5 100644 --- a/tests/liberty/.gitignore +++ b/tests/liberty/.gitignore @@ -1,4 +1,3 @@ *.log -test.ys *.filtered *.verilogsim diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh index 07d2cce1c..771bb69f7 100755 --- a/tests/liberty/run-test.sh +++ b/tests/liberty/run-test.sh @@ -3,10 +3,7 @@ set -e for x in *.lib; do echo "Testing on $x.." - echo "read_verilog small.v" > test.ys - echo "synth -top small" >> test.ys - echo "dfflibmap -info -liberty ${x}" >> test.ys - ../../yosys -ql ${x%.lib}.log -s test.ys + ../../yosys -p "read_verilog small.v; synth -top small; dfflibmap -info -liberty ${x}" -ql ${x%.lib}.log ../../yosys-filterlib - $x 2>/dev/null > $x.filtered ../../yosys-filterlib -verilogsim $x > $x.verilogsim diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok From d5756eb9be6de45bc108fe5c1c5557491f4e96e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:14:52 +0200 Subject: [PATCH 024/240] tests: Add trivial liberty -unit_delay test --- tests/liberty/run-test.sh | 5 +++++ tests/liberty/unit_delay.ys | 3 +++ 2 files changed, 8 insertions(+) create mode 100644 tests/liberty/unit_delay.ys diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh index 771bb69f7..ff5b20d74 100755 --- a/tests/liberty/run-test.sh +++ b/tests/liberty/run-test.sh @@ -8,3 +8,8 @@ for x in *.lib; do ../../yosys-filterlib -verilogsim $x > $x.verilogsim diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok done + +for x in *.ys; do + echo "Running $x.." + ../../yosys -q -s $x -l ${x%.ys}.log +done diff --git a/tests/liberty/unit_delay.ys b/tests/liberty/unit_delay.ys new file mode 100644 index 000000000..8dd409183 --- /dev/null +++ b/tests/liberty/unit_delay.ys @@ -0,0 +1,3 @@ +# Nothing gets imported: the file lacks timing data +read_liberty -wb -unit_delay normal.lib +select -assert-none =*/t:$specify* From 6c1fa45995f690ba1c8f8412ab09d938f83d9130 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Sep 2024 17:20:34 +0200 Subject: [PATCH 025/240] aiger2: Ingest `$pmux` --- backends/aiger2/aiger.cc | 41 +++++++++++++++++++++++++++++++++++++++- tests/various/aiger2.ys | 28 +++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index d300827d3..c0b9a0d7a 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -42,7 +42,7 @@ PRIVATE_NAMESPACE_BEGIN // TODO //#define ARITH_OPS ID($add), ID($sub), ID($neg) -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS /*, ARITH_OPS*/ +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, ID($pmux) /*, ARITH_OPS*/ template struct Index { @@ -199,6 +199,28 @@ struct Index { return OR(AND(a, b), AND(c, OR(a, b))); } + Lit REDUCE(std::vector lits, bool op_xor=false) + { + std::vector next; + while (lits.size() > 1) { + next.clear(); + for (int i = 0; i < lits.size(); i += 2) { + if (i + 1 >= lits.size()) { + next.push_back(lits[i]); + } else { + Lit a = lits[i], b = lits[i + 1]; + next.push_back(op_xor ? XOR(a, b) : AND(a, b)); + } + } + next.swap(lits); + } + + if (lits.empty()) + return op_xor ? CFALSE : CTRUE; + else + return lits.front(); + } + Lit impl_op(HierCursor &cursor, Cell *cell, IdString oport, int obit) { if (cell->type.in(REDUCE_OPS, LOGIC_OPS, CMP_OPS) && obit != 0) { @@ -360,6 +382,23 @@ struct Index { log_abort(); } } + } else if (cell->type == ID($pmux)) { + SigSpec aport = cell->getPort(ID::A); + SigSpec bport = cell->getPort(ID::B); + SigSpec sport = cell->getPort(ID::S); + int width = aport.size(); + + Lit a = visit(cursor, aport[obit]); + + std::vector bar, sels; + for (int i = 0; i < sport.size(); i++) { + Lit s = visit(cursor, sport[i]); + Lit b = visit(cursor, bport[width * i + obit]); + bar.push_back(NOT(AND(s, b))); + sels.push_back(NOT(s)); + } + + return OR(AND(REDUCE(sels), a), NOT(REDUCE(bar))); } else { log_abort(); } diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index 5d8c6e848..0efb5dd76 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -165,3 +165,31 @@ read_aiger -module_name test aiger2_ops.aig select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D miter -equiv -flatten gold test miter sat -verify -prove trigger 0 miter + +design -reset +read_verilog -icells < Date: Mon, 16 Sep 2024 17:25:17 +0200 Subject: [PATCH 026/240] aiger2: Use `REDUCE` for reduction ops --- backends/aiger2/aiger.cc | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c0b9a0d7a..0a949be48 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -262,21 +262,21 @@ struct Index { } else if (cell->type.in(REDUCE_OPS, ID($logic_not))) { SigSpec inport = cell->getPort(ID::A); - log_assert(inport.size() > 0); // TODO - - Lit acc = visit(cursor, inport[0]); - for (int i = 1; i < inport.size(); i++) { - Lit l = visit(cursor, inport[i]); - if (cell->type == ID($reduce_and)) { - acc = AND(acc, l); + std::vector lits; + for (int i = 0; i < inport.size(); i++) { + Lit lit = visit(cursor, inport[i]); + if (cell->type.in(ID($reduce_and), ID($reduce_xor), ID($reduce_xnor))) { + lits.push_back(lit); } else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) { - acc = OR(acc, l); - } else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { - acc = XOR(acc, l); + lits.push_back(NOT(lit)); + } else { + log_abort(); } } - if (!cell->type.in(ID($reduce_xnor), ID($logic_not))) + Lit acc = REDUCE(lits, cell->type.in(ID($reduce_xor), ID($reduce_xnor))); + + if (!cell->type.in(ID($reduce_xnor), ID($reduce_or), ID($reduce_bool))) return acc; else return NOT(acc); From 6cecf19ff4929ef04ce6915b4360f4d9b1782075 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Sep 2024 18:26:02 +0200 Subject: [PATCH 027/240] aiger2: Ingest `$bmux` --- backends/aiger2/aiger.cc | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0a949be48..5521a8133 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -42,7 +42,8 @@ PRIVATE_NAMESPACE_BEGIN // TODO //#define ARITH_OPS ID($add), ID($sub), ID($neg) -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, ID($pmux) /*, ARITH_OPS*/ +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, \ + ID($pmux), ID($bmux) /*, ARITH_OPS*/ template struct Index { @@ -399,6 +400,25 @@ struct Index { } return OR(AND(REDUCE(sels), a), NOT(REDUCE(bar))); + } else if (cell->type == ID($bmux)) { + SigSpec aport = cell->getPort(ID::A); + SigSpec sport = cell->getPort(ID::S); + int width = cell->getParam(ID::WIDTH).as_int(); + + std::vector data; + for (int i = obit; i < aport.size(); i += width) + data.push_back(visit(cursor, aport[i])); + + std::vector next; + for (int i = 0; i < sport.size(); i++) { + Lit s = visit(cursor, sport[i]); + next.clear(); + for (int j = 0; j < data.size(); j += 2) + next.push_back(MUX(data[j], data[j + 1], s)); + data.swap(next); + } + log_assert(data.size() == 1); + return data[0]; } else { log_abort(); } From 1ab7f2993300e5444655b3e7aa8807f2f3bfa180 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 11:55:04 +0200 Subject: [PATCH 028/240] Start read_xaiger2 -sc_mapping --- frontends/aiger2/Makefile.inc | 2 + frontends/aiger2/xaiger.cc | 275 ++++++++++++++++++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 frontends/aiger2/Makefile.inc create mode 100644 frontends/aiger2/xaiger.cc diff --git a/frontends/aiger2/Makefile.inc b/frontends/aiger2/Makefile.inc new file mode 100644 index 000000000..b4a9f6b89 --- /dev/null +++ b/frontends/aiger2/Makefile.inc @@ -0,0 +1,2 @@ + +OBJS += frontends/aiger2/xaiger.o diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc new file mode 100644 index 000000000..d2c2aa4b2 --- /dev/null +++ b/frontends/aiger2/xaiger.cc @@ -0,0 +1,275 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) Martin PoviĊĦer + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +uint32_t read_be32(std::istream &f) { + return ((uint32_t) f.get() << 24) | + ((uint32_t) f.get() << 16) | + ((uint32_t) f.get() << 8) | (uint32_t) f.get(); +} + +IdString read_idstring(std::istream &f) +{ + std::string str; + std::getline(f, str, '\0'); + if (!f.good()) + log_error("failed to read string\n"); + return RTLIL::escape_id(str); +} + +struct Xaiger2Frontend : public Frontend { + Xaiger2Frontend() : Frontend("xaiger2", "read XAIGER file (new)") {} + + void read_sc_mapping(std::istream *&f, std::string filename, std::vector args, Design *design) + { + IdString module_name; + std::string map_filename; + + size_t argidx; + for (argidx = 2; argidx < args.size(); argidx++) { + std::string arg = args[argidx]; + if (arg == "-module_name" && argidx + 1 < args.size()) { + module_name = RTLIL::escape_id(args[++argidx]); + continue; + } + if (arg == "-map2" && argidx + 1 < args.size()) { + map_filename = args[++argidx]; + continue; + } + break; + } + extra_args(f, filename, args, argidx, true); + + if (map_filename.empty()) + log_error("A '-map2' argument required\n"); + if (module_name.empty()) + log_error("A '-module_name' argument required\n"); + + Module *module = design->module(module_name); + if (!module) + log_error("Module '%s' not found\n", log_id(module_name)); + + std::ifstream map_file; + map_file.open(map_filename); + if (!map_file) + log_error("Failed to open map file '%s'\n", map_filename.c_str()); + + unsigned int M, I, L, O, A; + std::string header; + if (!(*f >> header >> M >> I >> L >> O >> A) || header != "aig") + log_error("Bad header\n"); + std::string line; + std::getline(*f, line); + log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A); + + if (L != 0) + log_error("Latches unsupported\n"); + if (I + L + A != M) + log_error("Inconsistent header\n"); + + std::vector outputs; + for (int i = 0; i < O; i++) { + int po; + *f >> po; + log_assert(f->get() == '\n'); + outputs.push_back(po); + } + + std::vector bits(2 + 2*M, RTLIL::Sm); + bits[0] = RTLIL::S0; + bits[1] = RTLIL::S1; + + std::string type; + while (map_file >> type) { + if (type == "pi") { + int pi_idx; + int woffset; + std::string name; + if (!(map_file >> pi_idx >> woffset >> name)) + log_error("Bad map file (1)\n"); + int lit = (2 * pi_idx) + 2; + if (lit < 0 || lit >= bits.size()) + log_error("Bad map file (2)\n"); + Wire *w = module->wire(name); + if (!w || woffset < 0 || woffset >= w->width) + log_error("Map file references non-existent signal bit %s[%d]\n", + name.c_str(), woffset); + bits[lit] = SigBit(w, woffset); + } else { + std::string scratch; + std::getline(map_file, scratch); + } + } + + for (int i = 0; i < A; i++) { + while (f->get() & 0x80 && !f->eof()); + while (f->get() & 0x80 && !f->eof()); + } + + if (f->get() != 'c') + log_error("Missing 'c' ahead of extensions\n"); + if (f->peek() == '\n') + f->get(); + + bool read_mapping = false; + uint32_t no_cells, no_instances; + for (int c = f->get(); c != EOF; c = f->get()) { + if (c == 'M') { + uint32_t len = read_be32(*f); + read_mapping = true; + + no_cells = read_be32(*f); + no_instances = read_be32(*f); + + log_debug("M: len=%u no_cells=%u no_instances=%u\n", len, no_cells, no_instances); + + struct MappingCell { + RTLIL::IdString type; + RTLIL::IdString out; + std::vector ins; + }; + std::vector cells; + cells.resize(no_cells); + + for (unsigned i = 0; i < no_cells; ++i) { + auto &cell = cells[i]; + cell.type = read_idstring(*f); + cell.out = read_idstring(*f); + uint32_t nins = read_be32(*f); + for (uint32_t j = 0; j < nins; j++) + cell.ins.push_back(read_idstring(*f)); + log_debug("M: Cell %s (out %s, ins", log_id(cell.type), log_id(cell.out)); + for (auto in : cell.ins) + log_debug(" %s", log_id(in)); + log_debug(")\n"); + } + + for (unsigned i = 0; i < no_instances; ++i) { + uint32_t cell_id = read_be32(*f); + uint32_t out_lit = read_be32(*f); + + log_assert(out_lit < bits.size()); + log_assert(bits[out_lit] == RTLIL::Sm); + log_assert(cell_id < cells.size()); + auto &cell = cells[cell_id]; + Cell *instance = module->addCell(NEW_ID, cell.type); + auto out_w = module->addWire(NEW_ID); + instance->setPort(cell.out, out_w); + bits[out_lit] = out_w; + for (auto in : cell.ins) { + uint32_t in_lit = read_be32(*f); + log_assert(out_lit < bits.size()); + log_assert(bits[in_lit] != RTLIL::Sm); + instance->setPort(in, bits[in_lit]); + } + } + } else if (c == '\n') { + break; + } else { + uint32_t len = read_be32(*f); + f->ignore(len); + log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + } + } + + if (!read_mapping) + log_error("Missing mapping (no 'M' section)\n"); + + while (true) { + std::string scratch; + std::getline(*f, scratch); + if (f->eof()) + break; + log_assert(!f->fail()); + log("input file: %s\n", scratch.c_str()); + } + + log("Read %d instances with cell library of size %d.\n", + no_instances, no_cells); + + // TODO + map_file.close(); + map_file.open(map_filename); + while (map_file >> type) { + if (type == "po") { + int po_idx; + int woffset; + std::string name; + if (!(map_file >> po_idx >> woffset >> name)) + log_error("Bad map file (3)\n"); + if (po_idx < 0 || po_idx >= outputs.size()) + log_error("Bad map file (4)\n"); + int lit = outputs[po_idx]; + if (lit < 0 || lit >= bits.size()) + log_error("Bad map file (5)\n"); + if (bits[lit] == RTLIL::Sm) + log_error("Bad map file (6)\n"); + Wire *w = module->wire(name); + if (!w || woffset < 0 || woffset >= w->width) + log_error("Map file references non-existent signal bit %s[%d]\n", + name.c_str(), woffset); + module->connect(SigBit(w, woffset), bits[lit]); + } else if (type == "pseudopo") { + int po_idx; + int poffset; + std::string box_name; + std::string box_port; + if (!(map_file >> po_idx >> poffset >> box_name >> box_port)) + log_error("Bad map file (7)\n"); + if (po_idx < 0 || po_idx >= outputs.size()) + log_error("Bad map file (8)\n"); + int lit = outputs[po_idx]; + if (lit < 0 || lit >= bits.size()) + log_error("Bad map file (9)\n"); + if (bits[lit] == RTLIL::Sm) + log_error("Bad map file (10)\n"); + Cell *cell = module->cell(box_name); + if (!cell || !cell->hasPort(box_port)) + log_error("Map file references non-existent box port %s/%s\n", + box_name.c_str(), box_port.c_str()); + SigSpec &port = cell->connections_[box_port]; + if (poffset < 0 || poffset >= port.size()) + log_error("Map file references non-existent box port bit %s/%s[%d]\n", + box_name.c_str(), box_port.c_str(), poffset); + port[poffset] = bits[lit]; + } else { + std::string scratch; + std::getline(map_file, scratch); + } + } + } + + void execute(std::istream *&f, std::string filename, std::vector args, Design *design) override + { + log_header(design, "Executing XAIGER2 frontend.\n"); + + if (args.size() > 1 && args[1] == "-sc_mapping") { + read_sc_mapping(f, filename, args, design); + return; + } + + log_cmd_error("Mode '-sc_mapping' must be selected\n"); + } +} Xaiger2Frontend; + +PRIVATE_NAMESPACE_END From 72d65063c32adce9eb2e33bee41736e8339fbea4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:38:05 +0200 Subject: [PATCH 029/240] aiger2: Ignore benign cells --- backends/aiger2/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 5521a8133..c6386b783 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -87,7 +87,7 @@ struct Index { int pos = index_wires(info, m); for (auto cell : m->cells()) { - if (cell->type.in(KNOWN_OPS)) + if (cell->type.in(KNOWN_OPS) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3))) continue; Module *submodule = m->design->module(cell->type); From 2a3e907da847342da56fd7a067e4f288213c36db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:39:05 +0200 Subject: [PATCH 030/240] aiger2: Adjust typing --- backends/aiger2/aiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c6386b783..d205f8508 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -125,7 +125,7 @@ struct Index { bool const_folding = true; bool strashing = false; - dict, int> cache; + dict, Lit> cache; Lit AND(Lit a, Lit b) { @@ -602,7 +602,7 @@ struct AigerWriter : Index { } void write_header() { - log_assert(lit_counter == (ninputs + nlatches + nands) * 2 + 2); + log_assert(lit_counter == (Lit) (ninputs + nlatches + nands) * 2 + 2); char buf[128]; snprintf(buf, sizeof(buf) - 1, "aig %08d %08d %08d %08d %08d\n", From ea765686b69c889f0cef7a5f4e0e670a4ab0b6db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:41:05 +0200 Subject: [PATCH 031/240] aiger2: Adjust hierarchy/port handling --- backends/aiger2/aiger.cc | 185 ++++++++++++++++++++++++++++++--------- tests/various/aiger2.ys | 2 +- 2 files changed, 145 insertions(+), 42 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index d205f8508..5e58a9ebc 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -19,6 +19,7 @@ // TODOs: // - gracefully handling inout ports (an error message probably) +// - undriven wires #include "kernel/register.h" #include "kernel/celltypes.h" @@ -56,6 +57,7 @@ struct Index { int len; dict windices; dict suboffsets; + pool found_blackboxes; bool indexing = false; bool indexed = false; @@ -73,6 +75,10 @@ struct Index { return sum; } + bool flatten = false; + bool inline_whiteboxes = false; + bool allow_blackboxes = false; + int index_module(RTLIL::Module *m) { ModuleInfo &info = modules[m]; @@ -91,11 +97,21 @@ struct Index { continue; Module *submodule = m->design->module(cell->type); - if (!submodule || submodule->get_blackbox_attribute()) - log_error("Unsupported cell type: %s (%s in %s)\n", - log_id(cell->type), log_id(cell), log_id(m)); - info.suboffsets[cell] = pos; - pos += index_module(submodule); + + if (submodule && flatten && + !submodule->get_bool_attribute(ID::keep_hierarchy) && + !submodule->get_blackbox_attribute(inline_whiteboxes)) { + info.suboffsets[cell] = pos; + pos += index_module(submodule); + } else { + if (allow_blackboxes) { + info.found_blackboxes.insert(cell); + } else { + if (!submodule || submodule->get_blackbox_attribute()) + log_error("Unsupported cell type: %s (%s in %s)\n", + log_id(cell->type), log_id(cell), log_id(m)); + } + } } info.len = pos; @@ -429,30 +445,36 @@ struct Index { std::vector levels; int instance_offset = 0; - HierCursor(ModuleInfo &top) + HierCursor() { - levels.push_back(Level(top, nullptr)); } - ModuleInfo ¤t_minfo() + ModuleInfo &leaf_minfo(Index &index) { - log_assert(!levels.empty()); - return levels.back().first; + if (levels.empty()) + return *index.top_minfo; + else + return levels.back().first; } - int bitwire_index(SigBit bit) + Module *leaf_module(Index &index) + { + return leaf_minfo(index).module; + } + + int bitwire_index(Index &index, SigBit bit) { log_assert(bit.wire != nullptr); - return instance_offset + current_minfo().windices[bit.wire] + bit.offset; + return instance_offset + leaf_minfo(index).windices[bit.wire] + bit.offset; } - Cell *exit() + Cell *exit(Index &index) { - log_assert(levels.size() > 1); + log_assert(!levels.empty()); Cell *instance = levels.back().second; levels.pop_back(); - instance_offset -= current_minfo().suboffsets.at(instance); + instance_offset -= leaf_minfo(index).suboffsets.at(instance); // return the instance we just exited return instance; @@ -461,7 +483,7 @@ struct Index { Module *enter(Index &index, Cell *cell) { Design *design = index.design; - auto &minfo = current_minfo(); + auto &minfo = leaf_minfo(index); log_assert(minfo.suboffsets.count(cell)); Module *def = design->module(cell->type); log_assert(def); @@ -471,6 +493,47 @@ struct Index { // return the module definition we just entered return def; } + + bool is_top() + { + return levels.empty(); + } + + std::string path() + { + std::string ret; + bool first = true; + for (auto pair : levels) { + if (!first) + ret += "."; + if (!pair.second) + ret += RTLIL::unescape_id(pair.first.module->name); + else + ret += RTLIL::unescape_id(pair.second->name); + first = false; + } + return ret; + } + + int hash() const + { + int hash = 0; + for (auto pair : levels) + hash += (uintptr_t) pair.second; + return hash; + } + + bool operator==(const HierCursor &other) const + { + if (levels.size() != other.levels.size()) + return false; + + for (int i = 0; i < levels.size(); i++) + if (levels[i].second != other.levels[i].second) + return false; + + return true; + } }; Lit visit(HierCursor &cursor, SigBit bit) @@ -484,7 +547,7 @@ struct Index { log_error("Unhandled state %s\n", log_signal(bit)); } - int idx = cursor.bitwire_index(bit); + int idx = cursor.bitwire_index(*this, bit); if (lits[idx] != Writer::EMPTY_LIT) { // literal already assigned return lits[idx]; @@ -510,16 +573,15 @@ struct Index { bit.offset, log_id(portname), log_id(driver), log_id(def), w->width); ret = visit(cursor, SigBit(w, bit.offset)); } - cursor.exit(); + cursor.exit(*this); } - } else { // a module input: we cannot be the top module, otherwise // the branch for pre-existing literals would have been taken - log_assert(cursor.levels.size() > 1); + log_assert(!cursor.is_top()); // step into the upper module - Cell *instance = cursor.exit(); + Cell *instance = cursor.exit(*this); { IdString portname = bit.wire->name; if (!instance->hasPort(portname)) @@ -538,23 +600,54 @@ struct Index { return ret; } - void set_top_port(SigBit bit, Lit lit) + Lit &pi_literal(SigBit bit, HierCursor *cursor=nullptr) { log_assert(bit.wire); - log_assert(bit.wire->module == top); - log_assert(bit.wire->port_input); - lits[top_minfo->windices[bit.wire] + bit.offset] = lit; + if (!cursor) { + log_assert(bit.wire->module == top); + log_assert(bit.wire->port_input); + return lits[top_minfo->windices[bit.wire] + bit.offset]; + } else { + log_assert(bit.wire->module == cursor->leaf_module(*this)); + return lits[cursor->bitwire_index(*this, bit)]; + } } - Lit get_top_port(SigBit bit) + Lit eval_po(SigBit bit, HierCursor *cursor=nullptr) { - HierCursor cursor(*top_minfo); - Lit ret = visit(cursor, bit); - log_assert(cursor.levels.size() == 1); - log_assert(cursor.instance_offset == 0); + Lit ret; + if (!cursor) { + HierCursor cursor_; + ret = visit(cursor_, bit); + log_assert(cursor_.is_top()); + log_assert(cursor_.instance_offset == 0); + } else { + ret = visit(*cursor, bit); + } return ret; } + + void visit_hierarchy(std::function f, + HierCursor &cursor) + { + f(cursor); + + ModuleInfo &minfo = cursor.leaf_minfo(*this); + for (auto cell : minfo.module->cells()) { + if (minfo.suboffsets.count(cell)) { + cursor.enter(*this, cell); + visit_hierarchy(f, cursor); + cursor.exit(*this); + } + } + } + + void visit_hierarchy(std::function f) + { + HierCursor cursor; + visit_hierarchy(f, cursor); + } }; struct AigerWriter : Index { @@ -616,20 +709,25 @@ struct AigerWriter : Index { // populate inputs std::vector inputs; - for (auto w : top->wires()) + for (auto id : top->ports) { + Wire *w = top->wire(id); + log_assert(w); if (w->port_input) for (int i = 0; i < w->width; i++) { - set_top_port(SigBit(w, i), lit_counter); + pi_literal(SigBit(w, i)) = lit_counter; inputs.push_back(SigBit(w, i)); lit_counter += 2; ninputs++; } + } this->f = f; // start with the header write_header(); // insert padding where output literals will go (once known) - for (auto w : top->wires()) + for (auto id : top->ports) { + Wire *w = top->wire(id); + log_assert(w); if (w->port_output) { for (auto bit : SigSpec(w)) { (void) bit; @@ -639,6 +737,7 @@ struct AigerWriter : Index { noutputs++; } } + } auto data_start = f->tellp(); // now the guts @@ -646,7 +745,7 @@ struct AigerWriter : Index { for (auto w : top->wires()) if (w->port_output) { for (auto bit : SigSpec(w)) - outputs.push_back({bit, get_top_port(bit)}); + outputs.push_back({bit, eval_po(bit)}); } auto data_end = f->tellp(); @@ -749,6 +848,8 @@ struct Aiger2Backend : Backend { for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-strash") writer.strashing = true; + else if (args[argidx] == "-flatten") + writer.flatten = true; else break; } @@ -791,12 +892,12 @@ struct AIGCounter : Index { for (auto w : top->wires()) if (w->port_input) for (int i = 0; i < w->width; i++) - set_top_port(SigBit(w, i), ++nvars); + pi_literal(SigBit(w, i)) = ++nvars; for (auto w : top->wires()) if (w->port_output) { for (auto bit : SigSpec(w)) - (void) get_top_port(bit); + (void) eval_po(bit); } } }; @@ -808,10 +909,12 @@ struct AigsizePass : Pass { log_header(design, "Executing AIGSIZE pass. (size design AIG)\n"); size_t argidx; - AIGCounter counter; + AIGCounter writer; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-strash") - counter.strashing = true; + writer.strashing = true; + else if (args[argidx] == "-flatten") + writer.flatten = true; else break; } @@ -823,9 +926,9 @@ struct AigsizePass : Pass { log_cmd_error("No top module selected\n"); design->bufNormalize(true); - counter.setup(top); - counter.count(); - log("Counted %d gates\n", counter.ngates); + writer.setup(top); + writer.count(); + log("Counted %d gates\n", writer.ngates); // we are leaving the sacred land, un-bufnormalize // (if not, this will lead to bugs: the buf-normalized diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index 0efb5dd76..e008cdfaf 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -158,7 +158,7 @@ copy test gold flatten gold techmap submodule1 select test -write_aiger2 aiger2_ops.aig +write_aiger2 -flatten aiger2_ops.aig select -clear delete test read_aiger -module_name test aiger2_ops.aig From 5f8d7ff1702277d380bc90462ec6006222e2eab2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:53:31 +0200 Subject: [PATCH 032/240] Start new write_xaiger2 backend for export w/ boxes --- backends/aiger2/aiger.cc | 439 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 438 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 5e58a9ebc..6af7b0948 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -700,13 +700,14 @@ struct AigerWriter : Index { char buf[128]; snprintf(buf, sizeof(buf) - 1, "aig %08d %08d %08d %08d %08d\n", ninputs + nlatches + nands, ninputs, nlatches, noutputs, nands); - f->seekp(0); f->write(buf, strlen(buf)); } void write(std::ostream *f) { reset_counters(); + auto file_start = f->tellp(); + // populate inputs std::vector inputs; for (auto id : top->ports) { @@ -750,6 +751,7 @@ struct AigerWriter : Index { auto data_end = f->tellp(); // revisit header and the list of outputs + f->seekp(file_start); write_header(); for (auto pair : outputs) { char buf[16]; @@ -788,6 +790,390 @@ struct AigerWriter : Index { } }; +struct XAigerWriter : AigerWriter { + XAigerWriter() + { + allow_blackboxes = true; + } + + bool mapping_prep = false; + pool keep_wires; + std::ofstream map_file; + + typedef std::pair HierBit; + std::vector pos; + std::vector pis; + int proper_pos_counter = 0; + + pool driven_by_opaque_box; + + void ensure_pi(SigBit bit, HierCursor cursor={}, + bool box_port=false) + { + Lit &lit = pi_literal(bit, &cursor); + if (lit == EMPTY_LIT) { + lit = lit_counter; + pis.push_back(std::make_pair(bit, cursor)); + lit_counter += 2; + if (map_file.is_open() && !box_port) { + log_assert(cursor.is_top()); // TODO + driven_by_opaque_box.insert(bit); + map_file << "pi " << pis.size() - 1 << " " << bit.offset + << " " << bit.wire->name.c_str() << "\n"; + } + } else { + log_assert(!box_port); + } + } + + bool is_pi(SigBit bit, HierCursor cursor={}) + { + return pi_literal(bit, &cursor) != EMPTY_LIT; + } + + void pad_pi() + { + pis.push_back(std::make_pair(RTLIL::Sx, HierCursor{})); + lit_counter += 2; + } + + void append_box_ports(Cell *box, HierCursor &cursor, bool inputs) + { + for (auto &conn : box->connections_) { + bool is_input = box->input(conn.first); + bool is_output = box->output(conn.first); + + if (!(is_input || is_output) || (is_input && is_output)) + log_error("Ambiguous port direction on %s/%s\n", + log_id(box->type), log_id(conn.first)); + + if (is_input && inputs) { + int bitp = 0; + for (auto bit : conn.second) { + if (!bit.wire) { + bitp++; + continue; + } + + if (map_file.is_open()) { + log_assert(cursor.is_top()); + map_file << "pseudopo " << proper_pos_counter++ << " " << bitp + << " " << box->name.c_str() + << " " << conn.first.c_str() << "\n"; + } + + pos.push_back(std::make_pair(bit, cursor)); + + if (mapping_prep) + conn.second[bitp] = RTLIL::Sx; + + bitp++; + } + } else if (is_output && !inputs) { + for (auto &bit : conn.second) { + if (!bit.wire || bit.wire->port_input) + log_error("Bad connection"); + + + ensure_pi(bit, cursor); + keep_wires.insert(bit.wire); + } + } + } + } + + RTLIL::Module *holes_module; + + std::stringstream h_buffer; + static void write_be32(std::ostream &buffer, uint32_t u32) + { + typedef unsigned char uchar; + unsigned char u32_be[4] = { + (uchar) (u32 >> 24), (uchar) (u32 >> 16), (uchar) (u32 >> 8), (uchar) u32 + }; + buffer.write((char *) u32_be, sizeof(u32_be)); + } + + void prep_boxes(int pending_pos_num) + { + // boxes which have timing data, maybe a whitebox model + std::vector> nonopaque_boxes; + // boxes which are fully opaque + std::vector> opaque_boxes; + + log_debug("found boxes:\n"); + visit_hierarchy([&](HierCursor &cursor) { + auto &minfo = cursor.leaf_minfo(*this); + + for (auto box : minfo.found_blackboxes) { + log_debug(" - %s.%s (type %s): ", cursor.path().c_str(), + RTLIL::unescape_id(box->name).c_str(), + log_id(box->type)); + + Module *box_module = design->module(box->type), *box_derived; + + if (box_module && !box->parameters.empty()) { + // TODO: This is potentially costly even if a cached derivation exists + box_derived = design->module(box_module->derive(design, box->parameters)); + log_assert(box_derived); + } else { + box_derived = box_module; + } + + if (box_derived && box_derived->has_attribute(ID::abc9_box_id)) { + // This is an ABC9 box, we have timing data, maybe even a whitebox model + // These need to go last in the AIGER port list. + nonopaque_boxes.push_back(std::make_tuple(cursor, box, box_derived)); + log_debug("non-opaque\n"); + } else { + opaque_boxes.push_back(std::make_tuple(cursor, box, box_derived)); + log_debug("opaque\n"); + } + } + }); + + for (auto [cursor, box, def] : opaque_boxes) + append_box_ports(box, cursor, true); + + holes_module = design->addModule(NEW_ID); + std::vector holes_pis; + int boxes_ci_num = 0, boxes_co_num = 0; + + int box_seq = 0; + + for (auto [cursor, box, def] : nonopaque_boxes) { + // use `def->name` not `box->type` as we want the derived type + Cell *holes_wb = holes_module->addCell(NEW_ID, def->name); + int holes_pi_idx = 0; + + if (map_file.is_open()) { + log_assert(cursor.is_top()); + map_file << "box " << box_seq << " " << box->name.c_str() << "\n"; + } + box_seq++; + + for (auto port_id : def->ports) { + Wire *port = def->wire(port_id); + log_assert(port); + + SigSpec conn = box->hasPort(port_id) ? box->getPort(port_id) : SigSpec{}; + + if (port->port_input && !port->port_output) { + // primary + for (int i = 0; i < port->width; i++) { + SigBit bit; + if (i < conn.size()) { + bit = conn[i]; + } else { + // FIXME: hierarchical path + log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n", + log_id(port_id), i, log_id(box), log_id(box->type)); + bit = RTLIL::Sx; + } + + pos.push_back(std::make_pair(bit, cursor)); + } + boxes_co_num += port->width; + + if (mapping_prep && !conn.empty()) + box->setPort(port_id, SigSpec(RTLIL::Sx, conn.size())); + + // holes + SigSpec in_conn; + for (int i = 0; i < port->width; i++) { + while (holes_pi_idx >= (int) holes_pis.size()) { + Wire *w = holes_module->addWire(NEW_ID, 1); + w->port_input = true; + holes_module->ports.push_back(w->name); + holes_pis.push_back(w); + } + in_conn.append(holes_pis[i]); + holes_pi_idx++; + } + holes_wb->setPort(port_id, in_conn); + } else if (port->port_output && !port->port_input) { + // primary + for (int i = 0; i < port->width; i++) { + SigBit bit; + if (i < conn.size() && conn[i].is_wire()) { + bit = conn[i]; + } else { + // FIXME: hierarchical path + log_warning("connection on port %s[%d] of instance %s (type %s) missing\n", + log_id(port_id), i, log_id(box), log_id(box->type)); + pad_pi(); + continue; + } + + ensure_pi(bit, cursor, true); + keep_wires.insert(bit.wire); + } + boxes_ci_num += port->width; + + // holes + Wire *w = holes_module->addWire(NEW_ID, port->width); + w->port_output = true; + holes_module->ports.push_back(w->name); + holes_wb->setPort(port_id, w); + } else { + log_error("Ambiguous port direction on %s/%s\n", + log_id(box->type), log_id(port_id)); + } + } + } + + for (auto [cursor, box, def] : opaque_boxes) + append_box_ports(box, cursor, false); + + write_be32(h_buffer, 1); + write_be32(h_buffer, pis.size()); + log_debug("ciNum = %zu\n", pis.size()); + write_be32(h_buffer, pending_pos_num + pos.size()); + log_debug("coNum = %zu\n", boxes_co_num + pos.size()); + write_be32(h_buffer, pis.size() - boxes_ci_num); + log_debug("piNum = %zu\n", pis.size() - boxes_ci_num); + write_be32(h_buffer, pending_pos_num + pos.size() - boxes_co_num); + log_debug("poNum = %zu\n", pending_pos_num + pos.size() - boxes_co_num); + write_be32(h_buffer, nonopaque_boxes.size()); + + box_seq = 0; + for (auto [cursor, box, def] : nonopaque_boxes) { + int box_ci_num = 0, box_co_num = 0; + for (auto port_id : def->ports) { + Wire *port = def->wire(port_id); + log_assert(port); + if (port->port_input && !port->port_output) { + box_co_num += port->width; + } else if (port->port_output && !port->port_input) { + box_ci_num += port->width; + } else { + log_abort(); + } + } + + write_be32(h_buffer, box_co_num); + write_be32(h_buffer, box_ci_num); + write_be32(h_buffer, def->attributes.at(ID::abc9_box_id).as_int()); + write_be32(h_buffer, box_seq++); + } + } + + void clear_boxes() + { + design->remove(holes_module); + } + + void write(std::ostream *f) { + reset_counters(); + + for (auto w : top->wires()) + if (w->port_input) + for (int i = 0; i < w->width; i++) + ensure_pi(SigBit(w, i)); + + int proper_po_num = 0; + for (auto w : top->wires()) + if (w->port_output) + proper_po_num += w->width; + + prep_boxes(proper_po_num); + for (auto w : top->wires()) + if (w->port_output) + for (int i = 0; i < w->width; i++) { + if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) { + map_file << "po " << proper_pos_counter++ << " " << i + << " " << w->name.c_str() << "\n"; + } + pos.push_back(std::make_pair(SigBit(w, i), HierCursor{})); + } + + this->f = f; + // start with the header + ninputs = pis.size(); + noutputs = pos.size(); + write_header(); + // insert padding where output literals will go (once known) + for (auto _ : pos) { + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", 0); + f->write(buf, strlen(buf)); + } + auto data_start = f->tellp(); + + // now the guts + std::vector outlits; + for (auto &pair : pos) + outlits.push_back(eval_po(pair.first, &pair.second)); + + // revisit header and the list of outputs + f->seekp(0); + ninputs = pis.size(); + noutputs = pos.size(); + write_header(); + for (auto lit : outlits) { + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", lit); + f->write(buf, strlen(buf)); + } + // double check we arrived at the same offset for the + // main data section + log_assert(data_start == f->tellp()); + + // extensions + f->seekp(0, std::ios::end); + + f->put('c'); + + // insert empty 'r' and 's' sections (abc crashes if we provide 'a' without those) + f->put('r'); + write_be32(*f, 4); + write_be32(*f, 0); + f->put('s'); + write_be32(*f, 4); + write_be32(*f, 0); + + f->put('h'); + // TODO: get rid of std::string copy + std::string h_buffer_str = h_buffer.str(); + write_be32(*f, h_buffer_str.size()); + f->write(h_buffer_str.data(), h_buffer_str.size()); + +#if 1 + f->put('a'); + write_be32(*f, 0); // size to be filled later + auto holes_aiger_start = f->tellp(); + { + AigerWriter holes_writer; + holes_writer.flatten = true; + holes_writer.inline_whiteboxes = true; + holes_writer.setup(holes_module); + holes_writer.write(f); + } + auto holes_aiger_size = f->tellp() - holes_aiger_start; + f->seekp(holes_aiger_start, std::ios::beg); + f->seekp(-4, std::ios::cur); + write_be32(*f, holes_aiger_size); +#endif + f->seekp(0, std::ios::end); + + if (mapping_prep) { + std::vector to_remove_cells; + for (auto cell : top->cells()) + if (!top_minfo->found_blackboxes.count(cell)) + to_remove_cells.push_back(cell); + for (auto cell : to_remove_cells) + top->remove(cell); + pool to_remove; + for (auto wire : top->wires()) + if (!wire->port_input && !wire->port_output && !keep_wires.count(wire)) + to_remove.insert(wire); + top->remove(to_remove); + } + + clear_boxes(); + } +}; + struct Aiger2Backend : Backend { Aiger2Backend() : Backend("aiger2", "write design to AIGER file (new)") { @@ -872,6 +1258,57 @@ struct Aiger2Backend : Backend { } } Aiger2Backend; +struct XAiger2Backend : Backend { + XAiger2Backend() : Backend("xaiger2", "write design to XAIGER file (new)") + { + experimental(); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, Design *design) override + { + log_header(design, "Executing XAIGER2 backend.\n"); + + size_t argidx; + XAigerWriter writer; + std::string map_filename; + writer.const_folding = true; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-strash") + writer.strashing = true; + else if (args[argidx] == "-flatten") + writer.flatten = true; + else if (args[argidx] == "-mapping_prep") + writer.mapping_prep = true; + else if (args[argidx] == "-map2" && argidx + 1 < args.size()) + map_filename = args[++argidx]; + else + break; + } + extra_args(f, filename, args, argidx); + + Module *top = design->top_module(); + + if (!top || !design->selected_whole_module(top)) + log_cmd_error("No top module selected\n"); + + if (!map_filename.empty()) { + writer.map_file.open(map_filename); + if (!writer.map_file) + log_cmd_error("Failed to open '%s' for writing\n", map_filename.c_str()); + } + + design->bufNormalize(true); + writer.setup(top); + writer.write(f); + + // we are leaving the sacred land, un-bufnormalize + // (if not, this will lead to bugs: the buf-normalized + // flag must not be kept on past the code that can work + // with it) + design->bufNormalize(false); + } +} XAiger2Backend; + struct AIGCounter : Index { typedef int Lit; const static Lit CONST_FALSE = -1; From 3a1b003cc34481a98bcfe61199004cebe6835c7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:53:56 +0200 Subject: [PATCH 033/240] celltypes: Fix `$buf` eval --- kernel/celltypes.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 9868827e6..b6d89a805 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -381,11 +381,10 @@ struct CellTypes HANDLE_CELL_TYPE(modfloor) HANDLE_CELL_TYPE(pow) HANDLE_CELL_TYPE(pos) - HANDLE_CELL_TYPE(buf) HANDLE_CELL_TYPE(neg) #undef HANDLE_CELL_TYPE - if (type == ID($_BUF_)) + if (type.in(ID($_BUF_), ID($buf))) return arg1; if (type == ID($_NOT_)) return eval_not(arg1); From f168b2f4b18abd4ae6a397a1a7fc4642b218c033 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:54:38 +0200 Subject: [PATCH 034/240] read_xaiger2: Update box handling --- frontends/aiger2/xaiger.cc | 183 ++++++++++++++++++++++++++++++++++++- 1 file changed, 178 insertions(+), 5 deletions(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index d2c2aa4b2..b60cd0c88 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -95,6 +95,8 @@ struct Xaiger2Frontend : public Frontend { outputs.push_back(po); } + std::vector> boxes; + std::vector retained_boxes; std::vector bits(2 + 2*M, RTLIL::Sm); bits[0] = RTLIL::S0; bits[1] = RTLIL::S1; @@ -115,6 +117,34 @@ struct Xaiger2Frontend : public Frontend { log_error("Map file references non-existent signal bit %s[%d]\n", name.c_str(), woffset); bits[lit] = SigBit(w, woffset); + } else if (type == "box") { + int box_seq; + std::string name; + if (!(map_file >> box_seq >> name)) + log_error("Bad map file (20)\n"); + if (box_seq < 0) + log_error("Bad map file (21)\n"); + + Cell *box = module->cell(RTLIL::escape_id(name)); + if (!box) + log_error("Map file references non-existent box %s\n", + name.c_str()); + + Module *def = design->module(box->type); + if (def && !box->parameters.empty()) { + // TODO: This is potentially costly even if a cached derivation exists + def = design->module(def->derive(design, box->parameters)); + log_assert(def); + } + + if (!def) + log_error("Bad map file (22)\n"); + + if (box_seq >= boxes.size()) { + boxes.resize(box_seq + 1); + retained_boxes.resize(box_seq + 1); + } + boxes[box_seq] = std::make_pair(box, def); } else { std::string scratch; std::getline(map_file, scratch); @@ -130,7 +160,73 @@ struct Xaiger2Frontend : public Frontend { log_error("Missing 'c' ahead of extensions\n"); if (f->peek() == '\n') f->get(); + auto extensions_start = f->tellg(); + log_debug("reading 'h' (first pass)\n"); + for (int c = f->get(); c != EOF; c = f->get()) { + if (c == 'h') { + uint32_t len, ci_num, co_num, pi_num, po_num, no_boxes; + len = read_be32(*f); + read_be32(*f); + ci_num = read_be32(*f); + co_num = read_be32(*f); + pi_num = read_be32(*f); + po_num = read_be32(*f); + no_boxes = read_be32(*f); + + log_debug("len=%u ci_num=%u co_num=%u pi_num=%u po_nun=%u no_boxes=%u\n", + len, ci_num, co_num, pi_num, po_num, no_boxes); + + int ci_counter = 0; + for (uint32_t i = 0; i < no_boxes; i++) { + uint32_t box_inputs, box_outputs, box_id, box_seq; + box_inputs = read_be32(*f); + box_outputs = read_be32(*f); + box_id = read_be32(*f); + box_seq = read_be32(*f); + + log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size()); + log_assert(box_seq < boxes.size()); + + auto [cell, def] = boxes[box_seq]; + log_assert(cell && def); + retained_boxes[box_seq] = true; + + int box_ci_idx = 0; + for (auto port_id : def->ports) { + Wire *port = def->wire(port_id); + if (port->port_output) { + if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width) + log_error("Malformed design (1)\n"); + + SigSpec &conn = cell->connections_[port_id]; + for (int j = 0; j < port->width; j++) { + if (conn[j].wire && conn[j].wire->port_output) + conn[j] = module->addWire(module->uniquify( + stringf("$box$%s$%s$%d", + cell->name.isPublic() ? cell->name.c_str() + 1 : cell->name.c_str(), + port_id.isPublic() ? port_id.c_str() + 1 : port_id.c_str(), + j))); + + bits[2*(pi_num + ci_counter + box_ci_idx++) + 2] = conn[j]; + } + } + } + + log_assert(box_ci_idx == box_outputs); + ci_counter += box_ci_idx; + } + log_assert(pi_num + ci_counter == ci_num); + } else if (c == '\n') { + break; + } else { + uint32_t len = read_be32(*f); + f->ignore(len); + log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + } + } + + f->seekg(extensions_start); bool read_mapping = false; uint32_t no_cells, no_instances; for (int c = f->get(); c != EOF; c = f->get()) { @@ -172,10 +268,11 @@ struct Xaiger2Frontend : public Frontend { log_assert(bits[out_lit] == RTLIL::Sm); log_assert(cell_id < cells.size()); auto &cell = cells[cell_id]; - Cell *instance = module->addCell(NEW_ID, cell.type); - auto out_w = module->addWire(NEW_ID); + Cell *instance = module->addCell(module->uniquify(stringf("$sc%d", out_lit)), cell.type); + auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit))); instance->setPort(cell.out, out_w); bits[out_lit] = out_w; + log_debug("setting %d (driven by %s)\n", out_lit, log_id(cell.type)); for (auto in : cell.ins) { uint32_t in_lit = read_be32(*f); log_assert(out_lit < bits.size()); @@ -195,6 +292,74 @@ struct Xaiger2Frontend : public Frontend { if (!read_mapping) log_error("Missing mapping (no 'M' section)\n"); + log("Read %d instances with cell library of size %d.\n", + no_instances, no_cells); + + f->seekg(extensions_start); + log_debug("reading 'h' (second pass)\n"); + int co_counter = 0; + for (int c = f->get(); c != EOF; c = f->get()) { + if (c == 'h') { + uint32_t len, ci_num, co_num, pi_num, po_num, no_boxes; + len = read_be32(*f); + read_be32(*f); + ci_num = read_be32(*f); + co_num = read_be32(*f); + pi_num = read_be32(*f); + po_num = read_be32(*f); + no_boxes = read_be32(*f); + + log_debug("len=%u ci_num=%u co_num=%u pi_num=%u po_nun=%u no_boxes=%u\n", + len, ci_num, co_num, pi_num, po_num, no_boxes); + + for (uint32_t i = 0; i < no_boxes; i++) { + uint32_t box_inputs, box_outputs, box_id, box_seq; + box_inputs = read_be32(*f); + box_outputs = read_be32(*f); + box_id = read_be32(*f); + box_seq = read_be32(*f); + + log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size()); + log_assert(box_seq < boxes.size()); + + auto [cell, def] = boxes[box_seq]; + log_assert(cell && def); + + int box_co_idx = 0; + for (auto port_id : def->ports) { + Wire *port = def->wire(port_id); + SigSpec conn; + if (port->port_input) { + if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width) + log_error("Malformed design (2)\n"); + + SigSpec conn; + for (int j = 0; j < port->width; j++) { + log_assert(co_counter + box_co_idx < outputs.size()); + int lit = outputs[co_counter + box_co_idx++]; + log_assert(lit >= 0 && lit < bits.size()); + SigBit bit = bits[lit]; + if (bit == RTLIL::Sm) + log_error("Malformed mapping (1)\n"); + conn.append(bit); + } + cell->setPort(port_id, conn); + } + } + + log_assert(box_co_idx == box_inputs); + co_counter += box_co_idx; + } + log_assert(po_num + co_counter == co_num); + } else if (c == '\n') { + break; + } else { + uint32_t len = read_be32(*f); + f->ignore(len); + log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + } + } + while (true) { std::string scratch; std::getline(*f, scratch); @@ -204,10 +369,9 @@ struct Xaiger2Frontend : public Frontend { log("input file: %s\n", scratch.c_str()); } - log("Read %d instances with cell library of size %d.\n", - no_instances, no_cells); + log_debug("co_counter=%d\n", co_counter); - // TODO + // TODO: seek without close/open map_file.close(); map_file.open(map_filename); while (map_file >> type) { @@ -217,11 +381,13 @@ struct Xaiger2Frontend : public Frontend { std::string name; if (!(map_file >> po_idx >> woffset >> name)) log_error("Bad map file (3)\n"); + po_idx += co_counter; if (po_idx < 0 || po_idx >= outputs.size()) log_error("Bad map file (4)\n"); int lit = outputs[po_idx]; if (lit < 0 || lit >= bits.size()) log_error("Bad map file (5)\n"); + log("output=%d lit=%d\n", po_idx, lit); if (bits[lit] == RTLIL::Sm) log_error("Bad map file (6)\n"); Wire *w = module->wire(name); @@ -236,6 +402,7 @@ struct Xaiger2Frontend : public Frontend { std::string box_port; if (!(map_file >> po_idx >> poffset >> box_name >> box_port)) log_error("Bad map file (7)\n"); + po_idx += co_counter; if (po_idx < 0 || po_idx >= outputs.size()) log_error("Bad map file (8)\n"); int lit = outputs[po_idx]; @@ -257,6 +424,12 @@ struct Xaiger2Frontend : public Frontend { std::getline(map_file, scratch); } } + + int box_seq = 0; + for (auto [cell, def] : boxes) { + if (!retained_boxes[box_seq++]) + module->remove(cell); + } } void execute(std::istream *&f, std::string filename, std::vector args, Design *design) override From 9018d06a33d2d66f57ad825053c31f85417339a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 19 Sep 2024 11:21:09 +0200 Subject: [PATCH 035/240] quicklogic: Avoid carry chains in division mapping The default mapping rules for division-like operations (div/divfloor/ mod/modfloor) invoke subtractions which can get mapped to carry chains in FPGA flows. Optimizations across carry chains are weak, so in practice this ends up too costly compared to implementing the division purely in soft logic. For this reason arrange for `techmap.v` ignoring division operations under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry chains for divisions. --- techlibs/common/techmap.v | 3 ++- techlibs/quicklogic/synth_quicklogic.cc | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 68b276588..119296147 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -304,6 +304,7 @@ endmodule // Divide and Modulo // -------------------------------------------------------- +`ifndef NODIV module \$__div_mod_u (A, B, Y, R); parameter WIDTH = 1; @@ -531,7 +532,7 @@ module _90_modfloor (A, B, Y); .R(Y) ); endmodule - +`endif // -------------------------------------------------------- // Power diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 0e7aaa752..76ef44570 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -266,7 +266,8 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("map_gates")) { if (inferAdder && family == "qlf_k6n10f") { - run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)"); + run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v -D NODIV", "(unless -no_adder)"); + run("techmap", "(unless -no_adder)"); } else { run("techmap"); } From b788de932972074e58df9b11db40cfb574dcf12e Mon Sep 17 00:00:00 2001 From: George Rennie Date: Tue, 24 Sep 2024 03:01:49 +0100 Subject: [PATCH 036/240] smtbmc: escape path identifiers * also changes the print format for cover statements to be more uniform with the asserts, allowing easier parsing of cover path * this allows diambiguation of properties with the same name but different paths (see https://github.com/YosysHQ/sby/issues/296) --- backends/smt2/smtbmc.py | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index c3bdcebbe..d17bad3fb 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -1454,6 +1454,10 @@ def write_trace(steps_start, steps_stop, index, allregs=False): if outywfile is not None: write_yw_trace(steps, index, allregs) +def escape_path_segment(segment): + if "." in segment: + return f"\\{segment} " + return segment def print_failed_asserts_worker(mod, state, path, extrainfo, infomap, infokey=()): assert mod in smt.modinfo @@ -1464,7 +1468,8 @@ def print_failed_asserts_worker(mod, state, path, extrainfo, infomap, infokey=() for cellname, celltype in smt.modinfo[mod].cells.items(): cell_infokey = (mod, cellname, infokey) - if print_failed_asserts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + cellname, extrainfo, infomap, cell_infokey): + cell_path = path + "." + escape_path_segment(cellname) + if print_failed_asserts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), cell_path, extrainfo, infomap, cell_infokey): found_failed_assert = True for assertfun, assertinfo in smt.modinfo[mod].asserts.items(): @@ -1497,7 +1502,7 @@ def print_anyconsts_worker(mod, state, path): assert mod in smt.modinfo for cellname, celltype in smt.modinfo[mod].cells.items(): - print_anyconsts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + cellname) + print_anyconsts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + escape_path_segment(cellname)) for fun, info in smt.modinfo[mod].anyconsts.items(): if info[1] is None: @@ -1517,18 +1522,21 @@ def print_anyconsts(state): print_anyconsts_worker(topmod, "s%d" % state, topmod) -def get_cover_list(mod, base): +def get_cover_list(mod, base, path=None): + path = path or mod assert mod in smt.modinfo cover_expr = list() + # A tuple of path and cell name cover_desc = list() for expr, desc in smt.modinfo[mod].covers.items(): cover_expr.append("(ite (|%s| %s) #b1 #b0)" % (expr, base)) - cover_desc.append(desc) + cover_desc.append((path, desc)) for cell, submod in smt.modinfo[mod].cells.items(): - e, d = get_cover_list(submod, "(|%s_h %s| %s)" % (mod, cell, base)) + cell_path = path + "." + escape_path_segment(cell) + e, d = get_cover_list(submod, "(|%s_h %s| %s)" % (mod, cell, base), cell_path) cover_expr += e cover_desc += d @@ -1544,7 +1552,8 @@ def get_assert_map(mod, base, path, key_base=()): assert_map[(expr, key_base)] = ("(|%s| %s)" % (expr, base), path, desc) for cell, submod in smt.modinfo[mod].cells.items(): - assert_map.update(get_assert_map(submod, "(|%s_h %s| %s)" % (mod, cell, base), path + "." + cell, (mod, cell, key_base))) + cell_path = path + "." + escape_path_segment(cell) + assert_map.update(get_assert_map(submod, "(|%s_h %s| %s)" % (mod, cell, base), cell_path, (mod, cell, key_base))) return assert_map @@ -1903,7 +1912,9 @@ elif covermode: new_cover_mask.append(cover_mask[i]) continue - print_msg("Reached cover statement at %s in step %d." % (cover_desc[i], step)) + path = cover_desc[i][0] + name = cover_desc[i][1] + print_msg("Reached cover statement in step %d at %s: %s" % (step, path, name)) new_cover_mask.append("0") cover_mask = "".join(new_cover_mask) @@ -1933,7 +1944,7 @@ elif covermode: if "1" in cover_mask: for i in range(len(cover_mask)): if cover_mask[i] == "1": - print_msg("Unreached cover statement at %s." % cover_desc[i]) + print_msg("Unreached cover statement at %s: %s" % (cover_desc[i][0], cover_desc[i][1])) else: # not tempind, covermode active_assert_keys = get_assert_keys() From 3e3515e7d9a0f74503245ccd1b2ff4456fa619f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 24 Sep 2024 17:46:50 +0200 Subject: [PATCH 037/240] log: Never silence `log_cmd_error` Add extra handling to arrange for `log_cmd_error` never being silenced by the command line `-v N` option. Similar path for `log_error` exists already. --- kernel/log.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/kernel/log.cc b/kernel/log.cc index 55895da06..fabbe09fd 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -459,8 +459,21 @@ void log_cmd_error(const char *format, ...) if (log_cmd_error_throw) { log_last_error = vstringf(format, ap); + + // Make sure the error message gets through any selective silencing + // of log output + bool pop_errfile = false; + if (log_errfile != NULL) { + log_files.push_back(log_errfile); + pop_errfile = true; + } + log("ERROR: %s", log_last_error.c_str()); log_flush(); + + if (pop_errfile) + log_files.pop_back(); + throw log_cmd_error_exception(); } From ce7db661a8b7318fd502f26253d810654f6c63b0 Mon Sep 17 00:00:00 2001 From: rherveille Date: Sun, 29 Sep 2024 23:03:01 +0200 Subject: [PATCH 038/240] Added cast to type support (#4284) --- frontends/ast/ast.cc | 16 +- frontends/ast/simplify.cc | 60 +++- frontends/verilog/verilog_parser.y | 6 + tests/verilog/size_cast.sv | 493 +++++++++++++++++++++++++++++ 4 files changed, 573 insertions(+), 2 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 6852ef5d3..127806fce 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -478,6 +478,10 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const fprintf(f, ";\n"); break; + case AST_WIRETYPE: + fprintf(f, "%s", id2vl(str).c_str()); + break; + case AST_MEMORY: fprintf(f, "%s" "memory", indent.c_str()); if (is_signed) @@ -694,7 +698,17 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const break; case AST_CAST_SIZE: - children[0]->dumpVlog(f, ""); + switch (children[0]->type) + { + case AST_WIRE: + if (children[0]->children.size() > 0) + children[0]->children[0]->dumpVlog(f, ""); + else + fprintf(f, "%d'", children[0]->range_left - children[0]->range_right + 1); + break; + default: + children[0]->dumpVlog(f, ""); + } fprintf(f, "'("); children[1]->dumpVlog(f, ""); fprintf(f, ")"); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3d8478ef1..fbf5b90aa 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1500,11 +1500,69 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } break; + case AST_CAST_SIZE: { + int width = 1; + AstNode *node; + AstNode *child = children[0]; + + if (child->type == AST_WIRE) { + if (child->children.size() == 0) { + // Base type (e.g., int) + width = child->range_left - child->range_right +1; + node = mkconst_int(width, child->is_signed); + } else { + // User defined type + log_assert(child->children[0]->type == AST_WIRETYPE); + + const std::string &type_name = child->children[0]->str; + if (!current_scope.count(type_name)) + input_error("Unknown identifier `%s' used as type name\n", type_name.c_str()); + AstNode *resolved_type_node = current_scope.at(type_name); + if (resolved_type_node->type != AST_TYPEDEF) + input_error("`%s' does not name a type\n", type_name.c_str()); + log_assert(resolved_type_node->children.size() == 1); + AstNode *template_node = resolved_type_node->children[0]; + + // Ensure typedef itself is fully simplified + while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {}; + + switch (template_node->type) + { + case AST_WIRE: { + if (template_node->children.size() > 0 && template_node->children[0]->type == AST_RANGE) + width = range_width(this, template_node->children[0]); + child->delete_children(); + node = mkconst_int(width, true); + break; + } + + case AST_STRUCT: + case AST_UNION: { + child->delete_children(); + width = size_packed_struct(template_node, 0); + node = mkconst_int(width, false); + break; + } + + default: + log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type).c_str()); + } + } + + delete child; + children.erase(children.begin()); + children.insert(children.begin(), node); + } + + detect_width_simple = true; + children_are_self_determined = true; + break; + } + case AST_TO_BITS: case AST_TO_SIGNED: case AST_TO_UNSIGNED: case AST_SELFSZ: - case AST_CAST_SIZE: case AST_CONCAT: case AST_REPLICATE: case AST_REDUCE_AND: diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 15a04eb28..31d69ad0c 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -3506,6 +3506,12 @@ basic_expr: $$ = new AstNode(AST_CAST_SIZE, $1, $4); SET_AST_NODE_LOC($$, @1, @4); } | + typedef_base_type OP_CAST '(' expr ')' { + if (!sv_mode) + frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode."); + $$ = new AstNode(AST_CAST_SIZE, $1, $4); + SET_AST_NODE_LOC($$, @1, @4); + } | '(' expr '=' expr ')' { ensureAsgnExprAllowed(); AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $4); diff --git a/tests/verilog/size_cast.sv b/tests/verilog/size_cast.sv index 1636f8d70..a1d6bfae5 100644 --- a/tests/verilog/size_cast.sv +++ b/tests/verilog/size_cast.sv @@ -15,6 +15,18 @@ module top; logic signed [1:0] L2sb10 = 2; logic signed [1:0] L2sb11 = 3; + typedef logic u1bit_t; + typedef logic signed s1bit_t; + typedef logic [1:0] u2bit_t; + typedef logic signed [1:0] s2bit_t; + typedef logic [2:0] u3bit_t; + + typedef struct packed { + u1bit_t sign; + u3bit_t msbs; + byte lsbs; + } s12bit_packed_struct_t; + logic y = 1; always @* begin @@ -32,6 +44,19 @@ module top; assert (1'(L2sb10) == 1'b0); assert (1'(L2sb11) == 1'b1); + assert (u1bit_t'(L1b0 ) == 1'b0); + assert (u1bit_t'(L1b1 ) == 1'b1); + assert (s1bit_t'(L1sb0 ) == 1'b0); + assert (s1bit_t'(L1sb1 ) == 1'b1); + assert (u1bit_t'(L2b00 ) == 1'b0); + assert (u1bit_t'(L2b01 ) == 1'b1); + assert (u1bit_t'(L2b10 ) == 1'b0); + assert (u1bit_t'(L2b11 ) == 1'b1); + assert (s1bit_t'(L2sb00) == 1'b0); + assert (s1bit_t'(L2sb01) == 1'b1); + assert (s1bit_t'(L2sb10) == 1'b0); + assert (s1bit_t'(L2sb11) == 1'b1); + assert (2'(L1b0 ) == 2'b00); assert (2'(L1b1 ) == 2'b01); assert (2'(L1sb0 ) == 2'b00); @@ -45,6 +70,19 @@ module top; assert (2'(L2sb10) == 2'b10); assert (2'(L2sb11) == 2'b11); + assert (u2bit_t'(L1b0 ) == 2'b00); + assert (u2bit_t'(L1b1 ) == 2'b01); + assert (s2bit_t'(L1sb0 ) == 2'b00); + assert (s2bit_t'(L1sb1 ) == 2'b11); + assert (u2bit_t'(L2b00 ) == 2'b00); + assert (u2bit_t'(L2b01 ) == 2'b01); + assert (u2bit_t'(L2b10 ) == 2'b10); + assert (u2bit_t'(L2b11 ) == 2'b11); + assert (s2bit_t'(L2sb00) == 2'b00); + assert (s2bit_t'(L2sb01) == 2'b01); + assert (s2bit_t'(L2sb10) == 2'b10); + assert (s2bit_t'(L2sb11) == 2'b11); + assert (3'(L1b0 ) == 3'b000); assert (3'(L1b1 ) == 3'b001); assert (3'(L1sb0 ) == 3'b000); @@ -58,6 +96,19 @@ module top; assert (3'(L2sb10) == 3'b110); assert (3'(L2sb11) == 3'b111); + assert (u3bit_t'(L1b0 ) == 3'b000); + assert (u3bit_t'(L1b1 ) == 3'b001); + assert (u3bit_t'(L1sb0 ) == 3'b000); + assert (u3bit_t'(L1sb1 ) == 3'b111); + assert (u3bit_t'(L2b00 ) == 3'b000); + assert (u3bit_t'(L2b01 ) == 3'b001); + assert (u3bit_t'(L2b10 ) == 3'b010); + assert (u3bit_t'(L2b11 ) == 3'b011); + assert (u3bit_t'(L2sb00) == 3'b000); + assert (u3bit_t'(L2sb01) == 3'b001); + assert (u3bit_t'(L2sb10) == 3'b110); + assert (u3bit_t'(L2sb11) == 3'b111); + assert (3'(L1b0 | '1) == 3'b111); assert (3'(L1b1 | '1) == 3'b111); assert (3'(L1sb0 | '1) == 3'b111); @@ -71,6 +122,58 @@ module top; assert (3'(L2sb10 | '1) == 3'b111); assert (3'(L2sb11 | '1) == 3'b111); + assert (u3bit_t'(L1b0 | '1) == 3'b111); + assert (u3bit_t'(L1b1 | '1) == 3'b111); + assert (u3bit_t'(L1sb0 | '1) == 3'b111); + assert (u3bit_t'(L1sb1 | '1) == 3'b111); + assert (u3bit_t'(L2b00 | '1) == 3'b111); + assert (u3bit_t'(L2b01 | '1) == 3'b111); + assert (u3bit_t'(L2b10 | '1) == 3'b111); + assert (u3bit_t'(L2b11 | '1) == 3'b111); + assert (u3bit_t'(L2sb00 | '1) == 3'b111); + assert (u3bit_t'(L2sb01 | '1) == 3'b111); + assert (u3bit_t'(L2sb10 | '1) == 3'b111); + assert (u3bit_t'(L2sb11 | '1) == 3'b111); + + assert (byte'(L1b0 | '1) == 8'hff); + assert (byte'(L1b1 | '1) == 8'hff); + assert (byte'(L1sb0 | '1) == 8'hff); + assert (byte'(L1sb1 | '1) == 8'hff); + assert (byte'(L2b00 | '1) == 8'hff); + assert (byte'(L2b01 | '1) == 8'hff); + assert (byte'(L2b10 | '1) == 8'hff); + assert (byte'(L2b11 | '1) == 8'hff); + assert (byte'(L2sb00 | '1) == 8'hff); + assert (byte'(L2sb01 | '1) == 8'hff); + assert (byte'(L2sb10 | '1) == 8'hff); + assert (byte'(L2sb11 | '1) == 8'hff); + + assert (int'(L1b0 | '1) == 32'hffff_ffff); + assert (int'(L1b1 | '1) == 32'hffff_ffff); + assert (int'(L1sb0 | '1) == 32'hffff_ffff); + assert (int'(L1sb1 | '1) == 32'hffff_ffff); + assert (int'(L2b00 | '1) == 32'hffff_ffff); + assert (int'(L2b01 | '1) == 32'hffff_ffff); + assert (int'(L2b10 | '1) == 32'hffff_ffff); + assert (int'(L2b11 | '1) == 32'hffff_ffff); + assert (int'(L2sb00 | '1) == 32'hffff_ffff); + assert (int'(L2sb01 | '1) == 32'hffff_ffff); + assert (int'(L2sb10 | '1) == 32'hffff_ffff); + assert (int'(L2sb11 | '1) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(L1b0 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L1b1 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L1sb0 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L1sb1 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2b00 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2b01 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2b10 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2b11 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2sb00 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2sb01 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2sb10 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2sb11 | '1) == 12'hfff); + assert (3'(L1b0 | '0) == 3'b000); assert (3'(L1b1 | '0) == 3'b001); assert (3'(L1sb0 | '0) == 3'b000); @@ -84,6 +187,58 @@ module top; assert (3'(L2sb10 | '0) == 3'b010); assert (3'(L2sb11 | '0) == 3'b011); + assert (u3bit_t'(L1b0 | '0) == 3'b000); + assert (u3bit_t'(L1b1 | '0) == 3'b001); + assert (u3bit_t'(L1sb0 | '0) == 3'b000); + assert (u3bit_t'(L1sb1 | '0) == 3'b001); + assert (u3bit_t'(L2b00 | '0) == 3'b000); + assert (u3bit_t'(L2b01 | '0) == 3'b001); + assert (u3bit_t'(L2b10 | '0) == 3'b010); + assert (u3bit_t'(L2b11 | '0) == 3'b011); + assert (u3bit_t'(L2sb00 | '0) == 3'b000); + assert (u3bit_t'(L2sb01 | '0) == 3'b001); + assert (u3bit_t'(L2sb10 | '0) == 3'b010); + assert (u3bit_t'(L2sb11 | '0) == 3'b011); + + assert (byte'(L1b0 | '0) == 8'h00); + assert (byte'(L1b1 | '0) == 8'h01); + assert (byte'(L1sb0 | '0) == 8'h00); + assert (byte'(L1sb1 | '0) == 8'h01); + assert (byte'(L2b00 | '0) == 8'h00); + assert (byte'(L2b01 | '0) == 8'h01); + assert (byte'(L2b10 | '0) == 8'h02); + assert (byte'(L2b11 | '0) == 8'h03); + assert (byte'(L2sb00 | '0) == 8'h00); + assert (byte'(L2sb01 | '0) == 8'h01); + assert (byte'(L2sb10 | '0) == 8'h02); + assert (byte'(L2sb11 | '0) == 8'h03); + + assert (int'(L1b0 | '0) == 32'h0000_0000); + assert (int'(L1b1 | '0) == 32'h0000_0001); + assert (int'(L1sb0 | '0) == 32'h0000_0000); + assert (int'(L1sb1 | '0) == 32'h0000_0001); + assert (int'(L2b00 | '0) == 32'h0000_0000); + assert (int'(L2b01 | '0) == 32'h0000_0001); + assert (int'(L2b10 | '0) == 32'h0000_0002); + assert (int'(L2b11 | '0) == 32'h0000_0003); + assert (int'(L2sb00 | '0) == 32'h0000_0000); + assert (int'(L2sb01 | '0) == 32'h0000_0001); + assert (int'(L2sb10 | '0) == 32'h0000_0002); + assert (int'(L2sb11 | '0) == 32'h0000_0003); + + assert (s12bit_packed_struct_t'(L1b0 | '0) == 12'h000); + assert (s12bit_packed_struct_t'(L1b1 | '0) == 12'h001); + assert (s12bit_packed_struct_t'(L1sb0 | '0) == 12'h000); + assert (s12bit_packed_struct_t'(L1sb1 | '0) == 12'h001); + assert (s12bit_packed_struct_t'(L2b00 | '0) == 12'h000); + assert (s12bit_packed_struct_t'(L2b01 | '0) == 12'h001); + assert (s12bit_packed_struct_t'(L2b10 | '0) == 12'h002); + assert (s12bit_packed_struct_t'(L2b11 | '0) == 12'h003); + assert (s12bit_packed_struct_t'(L2sb00 | '0) == 12'h000); + assert (s12bit_packed_struct_t'(L2sb01 | '0) == 12'h001); + assert (s12bit_packed_struct_t'(L2sb10 | '0) == 12'h002); + assert (s12bit_packed_struct_t'(L2sb11 | '0) == 12'h003); + assert (3'(y ? L1b0 : '1) == 3'b000); assert (3'(y ? L1b1 : '1) == 3'b001); assert (3'(y ? L1sb0 : '1) == 3'b000); @@ -97,6 +252,58 @@ module top; assert (3'(y ? L2sb10 : '1) == 3'b010); assert (3'(y ? L2sb11 : '1) == 3'b011); + assert (u3bit_t'(y ? L1b0 : '1) == 3'b000); + assert (u3bit_t'(y ? L1b1 : '1) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : '1) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : '1) == 3'b001); + assert (u3bit_t'(y ? L2b00 : '1) == 3'b000); + assert (u3bit_t'(y ? L2b01 : '1) == 3'b001); + assert (u3bit_t'(y ? L2b10 : '1) == 3'b010); + assert (u3bit_t'(y ? L2b11 : '1) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : '1) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : '1) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : '1) == 3'b010); + assert (u3bit_t'(y ? L2sb11 : '1) == 3'b011); + + assert (byte'(y ? L1b0 : '1) == 8'h00); + assert (byte'(y ? L1b1 : '1) == 8'h01); + assert (byte'(y ? L1sb0 : '1) == 8'h00); + assert (byte'(y ? L1sb1 : '1) == 8'h01); + assert (byte'(y ? L2b00 : '1) == 8'h00); + assert (byte'(y ? L2b01 : '1) == 8'h01); + assert (byte'(y ? L2b10 : '1) == 8'h02); + assert (byte'(y ? L2b11 : '1) == 8'h03); + assert (byte'(y ? L2sb00 : '1) == 8'h00); + assert (byte'(y ? L2sb01 : '1) == 8'h01); + assert (byte'(y ? L2sb10 : '1) == 8'h02); + assert (byte'(y ? L2sb11 : '1) == 8'h03); + + assert (int'(y ? L1b0 : '1) == 32'h0000_0000); + assert (int'(y ? L1b1 : '1) == 32'h0000_0001); + assert (int'(y ? L1sb0 : '1) == 32'h0000_0000); + assert (int'(y ? L1sb1 : '1) == 32'h0000_0001); + assert (int'(y ? L2b00 : '1) == 32'h0000_0000); + assert (int'(y ? L2b01 : '1) == 32'h0000_0001); + assert (int'(y ? L2b10 : '1) == 32'h0000_0002); + assert (int'(y ? L2b11 : '1) == 32'h0000_0003); + assert (int'(y ? L2sb00 : '1) == 32'h0000_0000); + assert (int'(y ? L2sb01 : '1) == 32'h0000_0001); + assert (int'(y ? L2sb10 : '1) == 32'h0000_0002); + assert (int'(y ? L2sb11 : '1) == 32'h0000_0003); + + assert (s12bit_packed_struct_t'(y ? L1b0 : '1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : '1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : '1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : '1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b00 : '1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : '1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : '1) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : '1) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : '1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : '1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : '1) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2sb11 : '1) == 12'h003); + assert (3'(y ? L1b0 : '0) == 3'b000); assert (3'(y ? L1b1 : '0) == 3'b001); assert (3'(y ? L1sb0 : '0) == 3'b000); @@ -110,6 +317,58 @@ module top; assert (3'(y ? L2sb10 : '0) == 3'b010); assert (3'(y ? L2sb11 : '0) == 3'b011); + assert (u3bit_t'(y ? L1b0 : '0) == 3'b000); + assert (u3bit_t'(y ? L1b1 : '0) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : '0) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : '0) == 3'b001); + assert (u3bit_t'(y ? L2b00 : '0) == 3'b000); + assert (u3bit_t'(y ? L2b01 : '0) == 3'b001); + assert (u3bit_t'(y ? L2b10 : '0) == 3'b010); + assert (u3bit_t'(y ? L2b11 : '0) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : '0) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : '0) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : '0) == 3'b010); + assert (u3bit_t'(y ? L2sb11 : '0) == 3'b011); + + assert (byte'(y ? L1b0 : '0) == 8'h00); + assert (byte'(y ? L1b1 : '0) == 8'h01); + assert (byte'(y ? L1sb0 : '0) == 8'h00); + assert (byte'(y ? L1sb1 : '0) == 8'h01); + assert (byte'(y ? L2b00 : '0) == 8'h00); + assert (byte'(y ? L2b01 : '0) == 8'h01); + assert (byte'(y ? L2b10 : '0) == 8'h02); + assert (byte'(y ? L2b11 : '0) == 8'h03); + assert (byte'(y ? L2sb00 : '0) == 8'h00); + assert (byte'(y ? L2sb01 : '0) == 8'h01); + assert (byte'(y ? L2sb10 : '0) == 8'h02); + assert (byte'(y ? L2sb11 : '0) == 8'h03); + + assert (int'(y ? L1b0 : '0) == 32'h0000_0000); + assert (int'(y ? L1b1 : '0) == 32'h0000_0001); + assert (int'(y ? L1sb0 : '0) == 32'h0000_0000); + assert (int'(y ? L1sb1 : '0) == 32'h0000_0001); + assert (int'(y ? L2b00 : '0) == 32'h0000_0000); + assert (int'(y ? L2b01 : '0) == 32'h0000_0001); + assert (int'(y ? L2b10 : '0) == 32'h0000_0002); + assert (int'(y ? L2b11 : '0) == 32'h0000_0003); + assert (int'(y ? L2sb00 : '0) == 32'h0000_0000); + assert (int'(y ? L2sb01 : '0) == 32'h0000_0001); + assert (int'(y ? L2sb10 : '0) == 32'h0000_0002); + assert (int'(y ? L2sb11 : '0) == 32'h0000_0003); + + assert (s12bit_packed_struct_t'(y ? L1b0 : '0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : '0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : '0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : '0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b00 : '0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : '0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : '0) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : '0) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : '0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : '0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : '0) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2sb11 : '0) == 12'h003); + assert (3'(y ? L1b0 : 1'sb0) == 3'b000); assert (3'(y ? L1b1 : 1'sb0) == 3'b001); assert (3'(y ? L1sb0 : 1'sb0) == 3'b000); @@ -123,6 +382,123 @@ module top; assert (3'(y ? L2sb10 : 1'sb0) == 3'b110); assert (3'(y ? L2sb11 : 1'sb0) == 3'b111); + assert (u3bit_t'(y ? L1b0 : 1'sb0) == 3'b000); + assert (u3bit_t'(y ? L1b1 : 1'sb0) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : 1'sb0) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : 1'sb0) == 3'b111); + assert (u3bit_t'(y ? L2b00 : 1'sb0) == 3'b000); + assert (u3bit_t'(y ? L2b01 : 1'sb0) == 3'b001); + assert (u3bit_t'(y ? L2b10 : 1'sb0) == 3'b010); + assert (u3bit_t'(y ? L2b11 : 1'sb0) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : 1'sb0) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : 1'sb0) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : 1'sb0) == 3'b110); + assert (u3bit_t'(y ? L2sb11 : 1'sb0) == 3'b111); + + assert (byte'(y ? L1b0 : 1'sb0) == 8'h00); + assert (byte'(y ? L1b1 : 1'sb0) == 8'h01); + assert (byte'(y ? L1sb0 : 1'sb0) == 8'h00); + assert (byte'(y ? L1sb1 : 1'sb0) == 8'hff); + assert (byte'(y ? L2b00 : 1'sb0) == 8'h00); + assert (byte'(y ? L2b01 : 1'sb0) == 8'h01); + assert (byte'(y ? L2b10 : 1'sb0) == 8'h02); + assert (byte'(y ? L2b11 : 1'sb0) == 8'h03); + assert (byte'(y ? L2sb00 : 1'sb0) == 8'h00); + assert (byte'(y ? L2sb01 : 1'sb0) == 8'h01); + assert (byte'(y ? L2sb10 : 1'sb0) == 8'hfe); + assert (byte'(y ? L2sb11 : 1'sb0) == 8'hff); + + assert (int'(y ? L1b0 : 1'sb0) == 32'h0000_0000); + assert (int'(y ? L1b1 : 1'sb0) == 32'h0000_0001); + assert (int'(y ? L1sb0 : 1'sb0) == 32'h0000_0000); + assert (int'(y ? L1sb1 : 1'sb0) == 32'hffff_ffff); + assert (int'(y ? L2b00 : 1'sb0) == 32'h0000_0000); + assert (int'(y ? L2b01 : 1'sb0) == 32'h0000_0001); + assert (int'(y ? L2b10 : 1'sb0) == 32'h0000_0002); + assert (int'(y ? L2b11 : 1'sb0) == 32'h0000_0003); + assert (int'(y ? L2sb00 : 1'sb0) == 32'h0000_0000); + assert (int'(y ? L2sb01 : 1'sb0) == 32'h0000_0001); + assert (int'(y ? L2sb10 : 1'sb0) == 32'hffff_fffe); + assert (int'(y ? L2sb11 : 1'sb0) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(y ? L1b0 : 1'sb0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : 1'sb0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : 1'sb0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : 1'sb0) == 12'hfff); + assert (s12bit_packed_struct_t'(y ? L2b00 : 1'sb0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : 1'sb0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : 1'sb0) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : 1'sb0) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : 1'sb0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : 1'sb0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : 1'sb0) == 12'hffe); + assert (s12bit_packed_struct_t'(y ? L2sb11 : 1'sb0) == 12'hfff); + + assert (3'(y ? L1b0 : s1bit_t'(0)) == 3'b000); + assert (3'(y ? L1b1 : s1bit_t'(0)) == 3'b001); + assert (3'(y ? L1sb0 : s1bit_t'(0)) == 3'b000); + assert (3'(y ? L1sb1 : s1bit_t'(0)) == 3'b111); + assert (3'(y ? L2b00 : s1bit_t'(0)) == 3'b000); + assert (3'(y ? L2b01 : s1bit_t'(0)) == 3'b001); + assert (3'(y ? L2b10 : s1bit_t'(0)) == 3'b010); + assert (3'(y ? L2b11 : s1bit_t'(0)) == 3'b011); + assert (3'(y ? L2sb00 : s1bit_t'(0)) == 3'b000); + assert (3'(y ? L2sb01 : s1bit_t'(0)) == 3'b001); + assert (3'(y ? L2sb10 : s1bit_t'(0)) == 3'b110); + assert (3'(y ? L2sb11 : s1bit_t'(0)) == 3'b111); + + assert (u3bit_t'(y ? L1b0 : s1bit_t'(0)) == 3'b000); + assert (u3bit_t'(y ? L1b1 : s1bit_t'(0)) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : s1bit_t'(0)) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : s1bit_t'(0)) == 3'b111); + assert (u3bit_t'(y ? L2b00 : s1bit_t'(0)) == 3'b000); + assert (u3bit_t'(y ? L2b01 : s1bit_t'(0)) == 3'b001); + assert (u3bit_t'(y ? L2b10 : s1bit_t'(0)) == 3'b010); + assert (u3bit_t'(y ? L2b11 : s1bit_t'(0)) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : s1bit_t'(0)) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : s1bit_t'(0)) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : s1bit_t'(0)) == 3'b110); + assert (u3bit_t'(y ? L2sb11 : s1bit_t'(0)) == 3'b111); + + assert (byte'(y ? L1b0 : s1bit_t'(0)) == 8'h00); + assert (byte'(y ? L1b1 : s1bit_t'(0)) == 8'h01); + assert (byte'(y ? L1sb0 : s1bit_t'(0)) == 8'h00); + assert (byte'(y ? L1sb1 : s1bit_t'(0)) == 8'hff); + assert (byte'(y ? L2b00 : s1bit_t'(0)) == 8'h00); + assert (byte'(y ? L2b01 : s1bit_t'(0)) == 8'h01); + assert (byte'(y ? L2b10 : s1bit_t'(0)) == 8'h02); + assert (byte'(y ? L2b11 : s1bit_t'(0)) == 8'h03); + assert (byte'(y ? L2sb00 : s1bit_t'(0)) == 8'h00); + assert (byte'(y ? L2sb01 : s1bit_t'(0)) == 8'h01); + assert (byte'(y ? L2sb10 : s1bit_t'(0)) == 8'hfe); + assert (byte'(y ? L2sb11 : s1bit_t'(0)) == 8'hff); + + assert (int'(y ? L1b0 : s1bit_t'(0)) == 32'h0000_0000); + assert (int'(y ? L1b1 : s1bit_t'(0)) == 32'h0000_0001); + assert (int'(y ? L1sb0 : s1bit_t'(0)) == 32'h0000_0000); + assert (int'(y ? L1sb1 : s1bit_t'(0)) == 32'hffff_ffff); + assert (int'(y ? L2b00 : s1bit_t'(0)) == 32'h0000_0000); + assert (int'(y ? L2b01 : s1bit_t'(0)) == 32'h0000_0001); + assert (int'(y ? L2b10 : s1bit_t'(0)) == 32'h0000_0002); + assert (int'(y ? L2b11 : s1bit_t'(0)) == 32'h0000_0003); + assert (int'(y ? L2sb00 : s1bit_t'(0)) == 32'h0000_0000); + assert (int'(y ? L2sb01 : s1bit_t'(0)) == 32'h0000_0001); + assert (int'(y ? L2sb10 : s1bit_t'(0)) == 32'hffff_fffe); + assert (int'(y ? L2sb11 : s1bit_t'(0)) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(y ? L1b0 : s1bit_t'(0)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : s1bit_t'(0)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : s1bit_t'(0)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : s1bit_t'(0)) == 12'hfff); + assert (s12bit_packed_struct_t'(y ? L2b00 : s1bit_t'(0)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : s1bit_t'(0)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : s1bit_t'(0)) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : s1bit_t'(0)) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : s1bit_t'(0)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : s1bit_t'(0)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : s1bit_t'(0)) == 12'hffe); + assert (s12bit_packed_struct_t'(y ? L2sb11 : s1bit_t'(0)) == 12'hfff); + assert (3'(y ? L1b0 : 1'sb1) == 3'b000); assert (3'(y ? L1b1 : 1'sb1) == 3'b001); assert (3'(y ? L1sb0 : 1'sb1) == 3'b000); @@ -136,5 +512,122 @@ module top; assert (3'(y ? L2sb10 : 1'sb1) == 3'b110); assert (3'(y ? L2sb11 : 1'sb1) == 3'b111); + assert (u3bit_t'(y ? L1b0 : 1'sb1) == 3'b000); + assert (u3bit_t'(y ? L1b1 : 1'sb1) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : 1'sb1) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : 1'sb1) == 3'b111); + assert (u3bit_t'(y ? L2b00 : 1'sb1) == 3'b000); + assert (u3bit_t'(y ? L2b01 : 1'sb1) == 3'b001); + assert (u3bit_t'(y ? L2b10 : 1'sb1) == 3'b010); + assert (u3bit_t'(y ? L2b11 : 1'sb1) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : 1'sb1) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : 1'sb1) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : 1'sb1) == 3'b110); + assert (u3bit_t'(y ? L2sb11 : 1'sb1) == 3'b111); + + assert (byte'(y ? L1b0 : 1'sb1) == 8'h00); + assert (byte'(y ? L1b1 : 1'sb1) == 8'h01); + assert (byte'(y ? L1sb0 : 1'sb1) == 8'h00); + assert (byte'(y ? L1sb1 : 1'sb1) == 8'hff); + assert (byte'(y ? L2b00 : 1'sb1) == 8'h00); + assert (byte'(y ? L2b01 : 1'sb1) == 8'h01); + assert (byte'(y ? L2b10 : 1'sb1) == 8'h02); + assert (byte'(y ? L2b11 : 1'sb1) == 8'h03); + assert (byte'(y ? L2sb00 : 1'sb1) == 8'h00); + assert (byte'(y ? L2sb01 : 1'sb1) == 8'h01); + assert (byte'(y ? L2sb10 : 1'sb1) == 8'hfe); + assert (byte'(y ? L2sb11 : 1'sb1) == 8'hff); + + assert (int'(y ? L1b0 : 1'sb1) == 32'h0000_0000); + assert (int'(y ? L1b1 : 1'sb1) == 32'h0000_0001); + assert (int'(y ? L1sb0 : 1'sb1) == 32'h0000_0000); + assert (int'(y ? L1sb1 : 1'sb1) == 32'hffff_ffff); + assert (int'(y ? L2b00 : 1'sb1) == 32'h0000_0000); + assert (int'(y ? L2b01 : 1'sb1) == 32'h0000_0001); + assert (int'(y ? L2b10 : 1'sb1) == 32'h0000_0002); + assert (int'(y ? L2b11 : 1'sb1) == 32'h0000_0003); + assert (int'(y ? L2sb00 : 1'sb1) == 32'h0000_0000); + assert (int'(y ? L2sb01 : 1'sb1) == 32'h0000_0001); + assert (int'(y ? L2sb10 : 1'sb1) == 32'hffff_fffe); + assert (int'(y ? L2sb11 : 1'sb1) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(y ? L1b0 : 1'sb1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : 1'sb1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : 1'sb1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : 1'sb1) == 12'hfff); + assert (s12bit_packed_struct_t'(y ? L2b00 : 1'sb1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : 1'sb1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : 1'sb1) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : 1'sb1) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : 1'sb1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : 1'sb1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : 1'sb1) == 12'hffe); + assert (s12bit_packed_struct_t'(y ? L2sb11 : 1'sb1) == 12'hfff); + + assert (3'(y ? L1b0 : s1bit_t'(1)) == 3'b000); + assert (3'(y ? L1b1 : s1bit_t'(1)) == 3'b001); + assert (3'(y ? L1sb0 : s1bit_t'(1)) == 3'b000); + assert (3'(y ? L1sb1 : s1bit_t'(1)) == 3'b111); + assert (3'(y ? L2b00 : s1bit_t'(1)) == 3'b000); + assert (3'(y ? L2b01 : s1bit_t'(1)) == 3'b001); + assert (3'(y ? L2b10 : s1bit_t'(1)) == 3'b010); + assert (3'(y ? L2b11 : s1bit_t'(1)) == 3'b011); + assert (3'(y ? L2sb00 : s1bit_t'(1)) == 3'b000); + assert (3'(y ? L2sb01 : s1bit_t'(1)) == 3'b001); + assert (3'(y ? L2sb10 : s1bit_t'(1)) == 3'b110); + assert (3'(y ? L2sb11 : s1bit_t'(1)) == 3'b111); + + assert (u3bit_t'(y ? L1b0 : s1bit_t'(1)) == 3'b000); + assert (u3bit_t'(y ? L1b1 : s1bit_t'(1)) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : s1bit_t'(1)) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : s1bit_t'(1)) == 3'b111); + assert (u3bit_t'(y ? L2b00 : s1bit_t'(1)) == 3'b000); + assert (u3bit_t'(y ? L2b01 : s1bit_t'(1)) == 3'b001); + assert (u3bit_t'(y ? L2b10 : s1bit_t'(1)) == 3'b010); + assert (u3bit_t'(y ? L2b11 : s1bit_t'(1)) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : s1bit_t'(1)) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : s1bit_t'(1)) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : s1bit_t'(1)) == 3'b110); + assert (u3bit_t'(y ? L2sb11 : s1bit_t'(1)) == 3'b111); + + assert (byte'(y ? L1b0 : s1bit_t'(1)) == 8'h00); + assert (byte'(y ? L1b1 : s1bit_t'(1)) == 8'h01); + assert (byte'(y ? L1sb0 : s1bit_t'(1)) == 8'h00); + assert (byte'(y ? L1sb1 : s1bit_t'(1)) == 8'hff); + assert (byte'(y ? L2b00 : s1bit_t'(1)) == 8'h00); + assert (byte'(y ? L2b01 : s1bit_t'(1)) == 8'h01); + assert (byte'(y ? L2b10 : s1bit_t'(1)) == 8'h02); + assert (byte'(y ? L2b11 : s1bit_t'(1)) == 8'h03); + assert (byte'(y ? L2sb00 : s1bit_t'(1)) == 8'h00); + assert (byte'(y ? L2sb01 : s1bit_t'(1)) == 8'h01); + assert (byte'(y ? L2sb10 : s1bit_t'(1)) == 8'hfe); + assert (byte'(y ? L2sb11 : s1bit_t'(1)) == 8'hff); + + assert (int'(y ? L1b0 : s1bit_t'(1)) == 32'h0000_0000); + assert (int'(y ? L1b1 : s1bit_t'(1)) == 32'h0000_0001); + assert (int'(y ? L1sb0 : s1bit_t'(1)) == 32'h0000_0000); + assert (int'(y ? L1sb1 : s1bit_t'(1)) == 32'hffff_ffff); + assert (int'(y ? L2b00 : s1bit_t'(1)) == 32'h0000_0000); + assert (int'(y ? L2b01 : s1bit_t'(1)) == 32'h0000_0001); + assert (int'(y ? L2b10 : s1bit_t'(1)) == 32'h0000_0002); + assert (int'(y ? L2b11 : s1bit_t'(1)) == 32'h0000_0003); + assert (int'(y ? L2sb00 : s1bit_t'(1)) == 32'h0000_0000); + assert (int'(y ? L2sb01 : s1bit_t'(1)) == 32'h0000_0001); + assert (int'(y ? L2sb10 : s1bit_t'(1)) == 32'hffff_fffe); + assert (int'(y ? L2sb11 : s1bit_t'(1)) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(y ? L1b0 : s1bit_t'(1)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : s1bit_t'(1)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : s1bit_t'(1)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : s1bit_t'(1)) == 12'hfff); + assert (s12bit_packed_struct_t'(y ? L2b00 : s1bit_t'(1)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : s1bit_t'(1)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : s1bit_t'(1)) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : s1bit_t'(1)) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : s1bit_t'(1)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : s1bit_t'(1)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : s1bit_t'(1)) == 12'hffe); + assert (s12bit_packed_struct_t'(y ? L2sb11 : s1bit_t'(1)) == 12'hfff); + end endmodule From 59404f8ce55506cfebfe39d1ad404d1ae62e0b0e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 30 Sep 2024 00:21:26 +0000 Subject: [PATCH 039/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 62b4ed459..1e63bdd3f 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+139 +YOSYS_VER := 0.45+145 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 5fca9b867d269ad2ab6e01779f833d7785c53138 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 30 Sep 2024 16:25:22 +0200 Subject: [PATCH 040/240] Add Get vcd2fst step to test-yosys job Co-authored-by: Miodrag Milanovic Co-authored-by: Roland Coeurjoly --- .github/workflows/test-build.yml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 0eb2c65c5..e5aed6af3 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -100,6 +100,16 @@ jobs: cd iverilog echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV + - name: Get vcd2fst + shell: bash + run: | + git clone https://github.com/mmicko/libwave.git + mkdir -p ${{ github.workspace }}/.local/ + cd libwave + cmake . -DCMAKE_INSTALL_PREFIX=${{ github.workspace }}/.local + make -j$procs + make install + - name: Cache iverilog id: cache-iverilog uses: actions/cache@v4 From 35c8ad61ac9baaacf7919359b63b930e37d21b09 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 30 Sep 2024 17:38:43 +0300 Subject: [PATCH 041/240] cli/python: error-checking, python interpreter bugfix * Less brittle method of adding script dirname to sys.path * Check if scriptfp successfully opens before using it * Move `log_error` to after `PyErr_Print()` is called --- kernel/driver.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index d30b19c96..53608c260 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -665,13 +665,19 @@ int main(int argc, char **argv) PyObject_SetAttrString(sys, "argv", new_argv); Py_DECREF(old_argv); - PyRun_SimpleString(("import os;sys.path.insert(0, os.path.dirname(os.path.abspath(\""+scriptfile+"\")))").c_str()); + PyObject *py_path = PyUnicode_FromString(scriptfile.c_str()); + PyObject_SetAttrString(sys, "_yosys_script_path", py_path); + Py_DECREF(py_path); + PyRun_SimpleString("import os, sys; sys.path.insert(0, os.path.dirname(os.path.abspath(sys._yosys_script_path)))"); FILE *scriptfp = fopen(scriptfile.c_str(), "r"); + if (scriptfp == nullptr) { + log_error("Failed to open file '%s' for reading.\n", scriptfile.c_str()); + } if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) { - log_error("Python interpreter encountered an error:\n"); log_flush(); PyErr_Print(); + log_error("Python interpreter encountered an exception."); } #else log_error("Can't execute Python script: this version of yosys is not built with Python support enabled.\n"); From 1bf908dea8e09f29e10b7eb44501151a63c68eb3 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 1 Oct 2024 00:23:05 +0000 Subject: [PATCH 042/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1e63bdd3f..b3b8269c5 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+145 +YOSYS_VER := 0.45+148 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 76c615b2ae45d3015d5fa7c6f7ebc8b772b61847 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 30 Sep 2024 14:08:35 +0200 Subject: [PATCH 043/240] Fix: handle VCD variable references with and without whitespace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Miodrag Milanović Co-authored-by: Roland Coeurjoly --- kernel/fstdata.cc | 10 ++++++- tests/sim/var_reference_with_whitespace.vcd | 28 +++++++++++++++++++ .../sim/var_reference_without_whitespace.vcd | 28 +++++++++++++++++++ tests/sim/vcd_var_reference_whitespace.ys | 3 ++ tests/sim/vector_assign.il | 20 +++++++++++++ 5 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 tests/sim/var_reference_with_whitespace.vcd create mode 100644 tests/sim/var_reference_without_whitespace.vcd create mode 100644 tests/sim/vcd_var_reference_whitespace.ys create mode 100644 tests/sim/vector_assign.il diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index 65ae3426c..4a5b5a466 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -137,14 +137,22 @@ void FstData::extractVarNames() if (!var.is_alias) handle_to_var[h->u.var.handle] = var; std::string clean_name; + bool has_space = false; for(size_t i=0;iu.var.name);i++) { char c = h->u.var.name[i]; - if(c==' ') break; + if(c==' ') { has_space = true; break; } clean_name += c; } if (clean_name[0]=='\\') clean_name = clean_name.substr(1); + if (!has_space) { + size_t pos = clean_name.find_last_of("["); + std::string index_or_range = clean_name.substr(pos+1); + if (index_or_range.find(":") != std::string::npos) { + clean_name = clean_name.substr(0,pos); + } + } size_t pos = clean_name.find_last_of("<"); if (pos != std::string::npos && clean_name.back() == '>') { std::string mem_cell = clean_name.substr(0, pos); diff --git a/tests/sim/var_reference_with_whitespace.vcd b/tests/sim/var_reference_with_whitespace.vcd new file mode 100644 index 000000000..240610b2c --- /dev/null +++ b/tests/sim/var_reference_with_whitespace.vcd @@ -0,0 +1,28 @@ +$date + Fri Sep 27 11:58:46 2024 +$end +$version + GHDL v0 +$end +$timescale + 1 fs +$end +$scope module standard $end +$upscope $end +$scope module std_logic_1164 $end +$upscope $end +$scope module tb $end +$var reg 4 ! a [3:0] $end +$var reg 4 " b [3:0] $end +$scope module uut $end +$var reg 4 # a [3:0] $end +$var reg 4 $ b [3:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +b0001 ! +b0001 " +b0001 # +b0001 $ +#10000000 diff --git a/tests/sim/var_reference_without_whitespace.vcd b/tests/sim/var_reference_without_whitespace.vcd new file mode 100644 index 000000000..43b000752 --- /dev/null +++ b/tests/sim/var_reference_without_whitespace.vcd @@ -0,0 +1,28 @@ +$date + Fri Sep 27 11:58:46 2024 +$end +$version + GHDL v0 +$end +$timescale + 1 fs +$end +$scope module standard $end +$upscope $end +$scope module std_logic_1164 $end +$upscope $end +$scope module tb $end +$var reg 4 ! a[3:0] $end +$var reg 4 " b[3:0] $end +$scope module uut $end +$var reg 4 # a[3:0] $end +$var reg 4 $ b[3:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +b0001 ! +b0001 " +b0001 # +b0001 $ +#10000000 diff --git a/tests/sim/vcd_var_reference_whitespace.ys b/tests/sim/vcd_var_reference_whitespace.ys new file mode 100644 index 000000000..8e17821d2 --- /dev/null +++ b/tests/sim/vcd_var_reference_whitespace.ys @@ -0,0 +1,3 @@ +read_rtlil vector_assign.il +sim -r var_reference_without_whitespace.vcd -scope tb.uut +sim -r var_reference_with_whitespace.vcd -scope tb.uut \ No newline at end of file diff --git a/tests/sim/vector_assign.il b/tests/sim/vector_assign.il new file mode 100644 index 000000000..bc0bc6b6b --- /dev/null +++ b/tests/sim/vector_assign.il @@ -0,0 +1,20 @@ +# Generated by Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3) +autoidx 2 +attribute \architecture "Behavioral" +attribute \library "work" +attribute \hdlname "vector_assign" +attribute \src "tests/verific/vector_assign.vhd:4.8-4.21" +module \vector_assign + attribute \src "tests/verific/vector_assign.vhd:6.9-6.10" + wire width 4 input 2 \a + attribute \src "tests/verific/vector_assign.vhd:7.9-7.10" + wire width 4 output 1 \b + attribute \src "tests/verific/vector_assign.vhd:13.5-13.6" + cell $pos $verific$buf_3$tests/verific/vector_assign.vhd:13$1 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \a + connect \Y \b + end +end From 997cb30f1fe2c14a16463a9e3bad969dd89a52b6 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 1 Oct 2024 13:25:07 +0200 Subject: [PATCH 044/240] cxxrtl: test stream operator --- tests/cxxrtl/test_value.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tests/cxxrtl/test_value.cc b/tests/cxxrtl/test_value.cc index 0750d412e..b6fe3cf4a 100644 --- a/tests/cxxrtl/test_value.cc +++ b/tests/cxxrtl/test_value.cc @@ -49,4 +49,12 @@ int main() cxxrtl::value<1> sel(0u); assert(val.template bmux<4>(sel).get() == 0xfu); } + + { + // stream operator smoke test + cxxrtl::value<8> val(0x1fu); + std::ostringstream oss; + oss << val; + assert(oss.str() == "8'1f"); + } } From ec42b42bd93d08839a0f6315b807042990f093e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Oct 2024 11:26:15 +0200 Subject: [PATCH 045/240] cellmatch: Size the `lut` attribute --- passes/techmap/cellmatch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index a21a4fbad..235599972 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -223,7 +223,7 @@ struct CellmatchPass : Pass { for (auto bit : outputs) { log_assert(bit.is_wire()); bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]); - bit.wire->attributes[ID(lut)] = luts[no++]; + bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size()); } } From 5ea2c6e6e56075b9d6402cf93d3e12da46707db5 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 2 Oct 2024 11:18:19 +0200 Subject: [PATCH 046/240] Assume x values for missing signal data in FST Co-authored-by: Miodrag Milanovic Co-authored-by: Roland Coeurjoly --- kernel/fstdata.cc | 5 +++-- tests/sim/assume_x_first_step.ys | 2 ++ tests/sim/simple_assign.v | 8 ++++++++ tests/sim/simple_assign.vcd | 13 +++++++++++++ 4 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 tests/sim/assume_x_first_step.ys create mode 100644 tests/sim/simple_assign.v create mode 100644 tests/sim/simple_assign.vcd diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index 65ae3426c..309131e01 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -258,7 +258,8 @@ void FstData::reconstructAllAtTimes(std::vector &signal, uint64_t sta std::string FstData::valueOf(fstHandle signal) { - if (past_data.find(signal) == past_data.end()) - log_error("Signal id %d not found\n", (int)signal); + if (past_data.find(signal) == past_data.end()) { + return std::string(handle_to_var[signal].width, 'x'); + } return past_data[signal]; } diff --git a/tests/sim/assume_x_first_step.ys b/tests/sim/assume_x_first_step.ys new file mode 100644 index 000000000..3922e06f6 --- /dev/null +++ b/tests/sim/assume_x_first_step.ys @@ -0,0 +1,2 @@ +read_verilog simple_assign.v +sim -r simple_assign.vcd -scope simple_assign \ No newline at end of file diff --git a/tests/sim/simple_assign.v b/tests/sim/simple_assign.v new file mode 100644 index 000000000..85f3a8bf5 --- /dev/null +++ b/tests/sim/simple_assign.v @@ -0,0 +1,8 @@ +module simple_assign ( + input wire in, + output wire out +); + + assign out = in; + +endmodule diff --git a/tests/sim/simple_assign.vcd b/tests/sim/simple_assign.vcd new file mode 100644 index 000000000..c4494fadf --- /dev/null +++ b/tests/sim/simple_assign.vcd @@ -0,0 +1,13 @@ +$version Yosys $end +$scope module simple_assign $end +$var wire 1 n2 in $end +$var wire 1 n1 out $end +$upscope $end +$enddefinitions $end +#0 +#5 +b1 n1 +b1 n2 +#10 +b0 n1 +b0 n2 \ No newline at end of file From 13ecbd5c76b37b8dc14b945a63d1a54b1fcfeced Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 3 Oct 2024 20:05:28 +0100 Subject: [PATCH 047/240] quicklogic: test that dividing by a constant does not infer carry chains --- tests/arch/quicklogic/qlf_k6n10f/div.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/div.ys diff --git a/tests/arch/quicklogic/qlf_k6n10f/div.ys b/tests/arch/quicklogic/qlf_k6n10f/div.ys new file mode 100644 index 000000000..5ca5b3051 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/div.ys @@ -0,0 +1,14 @@ +# division by constants should not infer carry chains. +read_verilog < Date: Sun, 6 Oct 2024 08:38:16 +0200 Subject: [PATCH 048/240] docs: Simplify images generation to allow parallel build - remove the tidy target from the main target. * aux/log file are already excluded in a .gititgnore file * allow parallel generation as the tidy target imposes sequential build --- docs/source/_images/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/_images/Makefile b/docs/source/_images/Makefile index 26cc47284..cc00050f1 100644 --- a/docs/source/_images/Makefile +++ b/docs/source/_images/Makefile @@ -1,4 +1,4 @@ -all: examples all_tex tidy +all: examples all_tex # set a fake time in pdf generation to prevent unnecessary differences in output FAKETIME := TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' From d8038c11d1f1f4adf7cc5d00c632752e402cd4e2 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 10:07:17 +1300 Subject: [PATCH 049/240] Add -j flag to make docs CI --- .github/workflows/prepare-docs.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index 9233e6295..19680e992 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -32,7 +32,7 @@ jobs: - name: Prepare docs shell: bash run: - make docs/prep TARGETS= EXTRA_TARGETS= + make docs/prep -j${{ env.procs }} TARGETS= EXTRA_TARGETS= - name: Upload artifact uses: actions/upload-artifact@v4 From 571d181fb4bcb7fe63f2b886e5b41f02d2519884 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 10:26:29 +1300 Subject: [PATCH 050/240] Fix top-level make docs prerequisites Add `$(TARGETS)` for gen_examples and gen_images since they need the `yosys` executable. Add guidelines source files as a prerequisite to docs/source/generated while we're at it. --- Makefile | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index b3b8269c5..71e7891d9 100644 --- a/Makefile +++ b/Makefile @@ -979,16 +979,17 @@ docs/source/cmd/abc.rst: $(TARGETS) $(EXTRA_TARGETS) ./$(PROGRAM_PREFIX)yosys -p 'help -write-rst-command-reference-manual' PHONY: docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs -docs/gen_examples: +docs/gen_examples: $(TARGETS) $(Q) $(MAKE) -C docs examples -docs/gen_images: +docs/gen_images: $(TARGETS) $(Q) $(MAKE) -C docs images DOCS_GUIDELINE_FILES := GettingStarted CodingStyle -docs/guidelines docs/source/generated: +DOCS_GUIDELINE_SOURCE := $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) +docs/guidelines docs/source/generated: $(DOCS_GUIDELINE_SOURCE) $(Q) mkdir -p docs/source/generated - $(Q) cp -f $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) docs/source/generated + $(Q) cp -f $(DOCS_GUIDELINE_SOURCE) docs/source/generated # some commands return an error and print the usage text to stderr define DOC_USAGE_STDERR From 6155c59d00125c58b4eb66f419ef6485439c0de2 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 7 Oct 2024 00:21:37 +0000 Subject: [PATCH 051/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 71e7891d9..5b6fc3ff2 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+148 +YOSYS_VER := 0.45+153 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 2e1181a0923c5d2cb596a086d3435ffd1b476fb1 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 21:25:15 +1300 Subject: [PATCH 052/240] ci: Run make docs on PRs --- .github/workflows/prepare-docs.yml | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index 19680e992..e2689d4df 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -1,12 +1,32 @@ name: Build docs artifact with Verific -on: push +on: [push, pull_request] jobs: + check_docs_rebuild: + runs-on: ubuntu-latest + outputs: + skip_check: ${{ steps.skip_check.outputs.should_skip }} + docs_export: ${{ steps.docs_var.outputs.docs_export }} + env: + docs_export: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} + steps: + - id: skip_check + uses: fkirc/skip-duplicate-actions@v5 + with: + paths_ignore: '["**/README.md"]' + # don't cancel in case we're updating docs + cancel_others: 'false' + # only run on push *or* pull_request, not both + concurrent_skipping: ${{ env.docs_export && 'never' || 'same_content_newer'}} + - id: docs_var + run: echo "docs_export=${{ env.docs_export }}" >> $GITHUB_OUTPUT + prepare-docs: # docs builds are needed for anything on main, any tagged versions, and any tag # or branch starting with docs-preview - if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} + needs: check_docs_rebuild + if: ${{ needs.check_docs_rebuild.outputs.should_skip != 'true' }} runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys @@ -45,6 +65,7 @@ jobs: docs/source/code_examples - name: Trigger RTDs build + if: ${{ needs.check_docs_rebuild.outputs.docs_export == 'true' }} uses: dfm/rtds-action@v1.1.0 with: webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }} From 468a019c30381b3cf5877430a934b139f6457a52 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 21:56:23 +1300 Subject: [PATCH 053/240] docs: Makefile tidying examples and dots are now orthogonal. --- docs/Makefile | 2 +- docs/source/code_examples/extensions/Makefile | 5 +++-- docs/source/code_examples/fifo/Makefile | 4 +++- docs/source/code_examples/intro/Makefile | 4 +++- docs/source/code_examples/macc/Makefile | 4 +++- docs/source/code_examples/opt/Makefile | 8 ++++---- docs/source/code_examples/scrambler/Makefile | 5 +++-- docs/source/code_examples/selections/Makefile | 5 +++-- docs/source/code_examples/show/Makefile | 5 +++-- docs/source/code_examples/stubnets/Makefile | 5 +++-- docs/source/code_examples/synth_flow/Makefile | 5 +++-- docs/source/code_examples/techmap/Makefile | 5 +++-- 12 files changed, 35 insertions(+), 22 deletions(-) diff --git a/docs/Makefile b/docs/Makefile index 21fcd9623..6dbf6f490 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -238,7 +238,7 @@ Makefile-%: FORCE $(MAKE) -C $(@D) $(*F) CODE_EXAMPLES := $(wildcard source/code_examples/*/Makefile) -TEST_EXAMPLES := $(addsuffix -all,$(CODE_EXAMPLES)) +TEST_EXAMPLES := $(addsuffix -examples,$(CODE_EXAMPLES)) CLEAN_EXAMPLES := $(addsuffix -clean,$(CODE_EXAMPLES)) test-examples: $(TEST_EXAMPLES) clean-examples: $(CLEAN_EXAMPLES) diff --git a/docs/source/code_examples/extensions/Makefile b/docs/source/code_examples/extensions/Makefile index 8b5fa106a..2e621d70b 100644 --- a/docs/source/code_examples/extensions/Makefile +++ b/docs/source/code_examples/extensions/Makefile @@ -2,9 +2,10 @@ PROGRAM_PREFIX := YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys -.PHONY: all dots -all: dots test0.log test1.log test2.log +.PHONY: all dots examples +all: dots examples dots: test1.dot +examples: test0.log test1.log test2.log CXXFLAGS=$(shell $(YOSYS)-config --cxxflags) DATDIR=$(shell $(YOSYS)-config --datdir) diff --git a/docs/source/code_examples/fifo/Makefile b/docs/source/code_examples/fifo/Makefile index 0a1186a62..de3abfd99 100644 --- a/docs/source/code_examples/fifo/Makefile +++ b/docs/source/code_examples/fifo/Makefile @@ -10,8 +10,10 @@ MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells DOTS := $(addsuffix .dot,$(DOT_NAMES)) MAPDOTS := $(addsuffix .dot,$(MAPDOT_NAMES)) -all: dots fifo.out fifo.stat +.PHONY: all dots examples +all: dots examples dots: $(DOTS) $(MAPDOTS) +examples: fifo.out fifo.stat $(DOTS) fifo.out: fifo.v fifo.ys $(YOSYS) fifo.ys -l fifo.out -Q -T diff --git a/docs/source/code_examples/intro/Makefile b/docs/source/code_examples/intro/Makefile index 009c82c62..31df6b623 100644 --- a/docs/source/code_examples/intro/Makefile +++ b/docs/source/code_examples/intro/Makefile @@ -4,8 +4,10 @@ YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys DOTS = counter_00.dot counter_01.dot counter_02.dot counter_03.dot -all: dots +.PHONY: all dots examples +all: dots examples dots: $(DOTS) +examples: $(DOTS): counter.v counter.ys mycells.lib $(YOSYS) counter.ys diff --git a/docs/source/code_examples/macc/Makefile b/docs/source/code_examples/macc/Makefile index e93fe0657..f06c623a5 100644 --- a/docs/source/code_examples/macc/Makefile +++ b/docs/source/code_examples/macc/Makefile @@ -4,8 +4,10 @@ YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys DOTS = macc_simple_xmap.dot macc_xilinx_xmap.dot -all: dots +.PHONY: all dots examples +all: dots examples dots: $(DOTS) +examples: macc_simple_xmap.dot: macc_simple_*.v macc_simple_test.ys $(YOSYS) macc_simple_test.ys diff --git a/docs/source/code_examples/opt/Makefile b/docs/source/code_examples/opt/Makefile index 12c1c93b1..aa7962ca5 100644 --- a/docs/source/code_examples/opt/Makefile +++ b/docs/source/code_examples/opt/Makefile @@ -6,13 +6,13 @@ DOT_NAMES = opt_share opt_muxtree opt_merge opt_expr DOTS := $(addsuffix .dot,$(DOT_NAMES)) -all: dots +.PHONY: all dots examples +all: dots examples dots: $(DOTS) +examples: -%_full.dot: %.ys +%.dot: %.ys $(YOSYS) $< - -%.dot: %_full.dot gvpack -u -o $@ $*_full.dot .PHONY: clean diff --git a/docs/source/code_examples/scrambler/Makefile b/docs/source/code_examples/scrambler/Makefile index de475b8b1..a9b56f8d3 100644 --- a/docs/source/code_examples/scrambler/Makefile +++ b/docs/source/code_examples/scrambler/Makefile @@ -2,9 +2,10 @@ PROGRAM_PREFIX := YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: scrambler_p01.dot scrambler_p02.dot +examples: scrambler_p01.dot scrambler_p02.dot: scrambler.ys scrambler.v $(YOSYS) scrambler.ys diff --git a/docs/source/code_examples/selections/Makefile b/docs/source/code_examples/selections/Makefile index bb506ff38..3ad1bcf20 100644 --- a/docs/source/code_examples/selections/Makefile +++ b/docs/source/code_examples/selections/Makefile @@ -11,9 +11,10 @@ MEMDEMO_DOTS := $(addsuffix .dot,$(MEMDEMO)) SUBMOD = submod_00 submod_01 submod_02 submod_03 SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD)) -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS) +examples: select.dot: select.v select.ys $(YOSYS) select.ys diff --git a/docs/source/code_examples/show/Makefile b/docs/source/code_examples/show/Makefile index 4b269a4ab..6c1906cce 100644 --- a/docs/source/code_examples/show/Makefile +++ b/docs/source/code_examples/show/Makefile @@ -8,9 +8,10 @@ EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE)) CMOS = cmos_00 cmos_01 CMOS_DOTS := $(addsuffix .dot,$(CMOS)) -.PHONY: all dots -all: dots example.out +.PHONY: all dots examples +all: dots examples dots: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS) +examples: example.out splice.dot: splice.v $(YOSYS) -p 'prep -top splice_demo; show -format dot -prefix splice' splice.v diff --git a/docs/source/code_examples/stubnets/Makefile b/docs/source/code_examples/stubnets/Makefile index ec501f006..17f700c88 100644 --- a/docs/source/code_examples/stubnets/Makefile +++ b/docs/source/code_examples/stubnets/Makefile @@ -1,6 +1,7 @@ -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: +examples: .PHONY: test test: stubnets.so diff --git a/docs/source/code_examples/synth_flow/Makefile b/docs/source/code_examples/synth_flow/Makefile index 7db1c12f4..0dd37ed4d 100644 --- a/docs/source/code_examples/synth_flow/Makefile +++ b/docs/source/code_examples/synth_flow/Makefile @@ -9,9 +9,10 @@ YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys DOTS = $(addsuffix .dot,$(DOT_TARGETS)) -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: $(DOTS) +examples: %.dot: %.v %.ys $(YOSYS) -p 'script $*.ys; show -notitle -prefix $* -format dot' diff --git a/docs/source/code_examples/techmap/Makefile b/docs/source/code_examples/techmap/Makefile index e900fea4c..6736b0f1d 100644 --- a/docs/source/code_examples/techmap/Makefile +++ b/docs/source/code_examples/techmap/Makefile @@ -2,9 +2,10 @@ PROGRAM_PREFIX := YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot +examples: red_or3x1.dot: red_or3x1_* $(YOSYS) red_or3x1_test.ys From 0b1b94d85eebabddd6155ed26e802f8f5927ea87 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:00:28 +1300 Subject: [PATCH 054/240] Docs: Clean example outputs --- docs/source/code_examples/fifo/Makefile | 1 + docs/source/code_examples/fifo/fifo.out | 425 ------------------ docs/source/code_examples/fifo/fifo.stat | 57 --- docs/source/code_examples/selections/Makefile | 5 +- .../code_examples/selections/sumprod.out | 38 -- docs/source/code_examples/show/Makefile | 1 + docs/source/code_examples/show/example.out | 54 --- 7 files changed, 5 insertions(+), 576 deletions(-) delete mode 100644 docs/source/code_examples/fifo/fifo.out delete mode 100644 docs/source/code_examples/fifo/fifo.stat delete mode 100644 docs/source/code_examples/selections/sumprod.out delete mode 100644 docs/source/code_examples/show/example.out diff --git a/docs/source/code_examples/fifo/Makefile b/docs/source/code_examples/fifo/Makefile index de3abfd99..4836dac06 100644 --- a/docs/source/code_examples/fifo/Makefile +++ b/docs/source/code_examples/fifo/Makefile @@ -24,3 +24,4 @@ $(MAPDOTS) fifo.stat: fifo.v fifo_map.ys .PHONY: clean clean: rm -f *.dot + rm -f fifo.out fifo.stat diff --git a/docs/source/code_examples/fifo/fifo.out b/docs/source/code_examples/fifo/fifo.out deleted file mode 100644 index ac132ee6c..000000000 --- a/docs/source/code_examples/fifo/fifo.out +++ /dev/null @@ -1,425 +0,0 @@ - --- Executing script file `fifo.ys' -- -$ yosys fifo.v - --- Parsing `fifo.v' using frontend ` -vlog2k' -- - -1. Executing Verilog-2005 frontend: fifo.v -Parsing Verilog input from `fifo.v' to AST representation. -Storing AST representation for module `$abstract\addr_gen'. -Storing AST representation for module `$abstract\fifo'. -Successfully finished Verilog frontend. -echo on - -yosys> hierarchy -top addr_gen - -2. Executing HIERARCHY pass (managing design hierarchy). - -3. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'. -Generating RTLIL representation for module `\addr_gen'. - -3.1. Analyzing design hierarchy.. -Top module: \addr_gen - -3.2. Analyzing design hierarchy.. -Top module: \addr_gen -Removing unused module `$abstract\fifo'. -Removing unused module `$abstract\addr_gen'. -Removed 2 unused modules. - -yosys> select -module addr_gen - -yosys [addr_gen]> select -list -addr_gen -addr_gen/$1\addr[7:0] -addr_gen/$add$fifo.v:19$3_Y -addr_gen/$eq$fifo.v:16$2_Y -addr_gen/$0\addr[7:0] -addr_gen/addr -addr_gen/rst -addr_gen/clk -addr_gen/en -addr_gen/$add$fifo.v:19$3 -addr_gen/$eq$fifo.v:16$2 -addr_gen/$proc$fifo.v:0$4 -addr_gen/$proc$fifo.v:12$1 - -yosys [addr_gen]> select t:* - -yosys [addr_gen]*> select -list -addr_gen/$add$fifo.v:19$3 -addr_gen/$eq$fifo.v:16$2 - -yosys [addr_gen]*> select -set new_cells % - -yosys [addr_gen]*> select -clear - -yosys> show -format dot -prefix addr_gen_show addr_gen - -4. Generating Graphviz representation of design. -Writing dot description to `addr_gen_show.dot'. -Dumping module addr_gen to page 1. - -yosys> show -format dot -prefix new_cells_show -notitle @new_cells - -5. Generating Graphviz representation of design. -Writing dot description to `new_cells_show.dot'. -Dumping selected parts of module addr_gen to page 1. - -yosys> show -color maroon3 @new_cells -color cornflowerblue p:* -notitle -format dot -prefix addr_gen_hier - -6. Generating Graphviz representation of design. -Writing dot description to `addr_gen_hier.dot'. -Dumping module addr_gen to page 1. - -yosys> proc -noopt - -7. Executing PROC pass (convert processes to netlists). - -yosys> proc_clean - -7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -yosys> proc_rmdead - -7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 2 switch rules as full_case in process $proc$fifo.v:12$1 in module addr_gen. -Removed a total of 0 dead cases. - -yosys> proc_prune - -7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 1 assignment to connection. - -yosys> proc_init - -7.4. Executing PROC_INIT pass (extract init attributes). -Found init rule in `\addr_gen.$proc$fifo.v:0$4'. - Set init value: \addr = 8'00000000 - -yosys> proc_arst - -7.5. Executing PROC_ARST pass (detect async resets in processes). -Found async reset \rst in `\addr_gen.$proc$fifo.v:12$1'. - -yosys> proc_rom - -7.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - - -yosys> proc_mux - -7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\addr_gen.$proc$fifo.v:0$4'. -Creating decoders for process `\addr_gen.$proc$fifo.v:12$1'. - 1/1: $0\addr[7:0] - -yosys> proc_dlatch - -7.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -yosys> proc_dff - -7.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\addr_gen.\addr' using process `\addr_gen.$proc$fifo.v:12$1'. - created $adff cell `$procdff$10' with positive edge clock and positive level reset. - -yosys> proc_memwr - -7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -yosys> proc_clean - -7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `addr_gen.$proc$fifo.v:0$4'. -Found and cleaned up 2 empty switches in `\addr_gen.$proc$fifo.v:12$1'. -Removing empty process `addr_gen.$proc$fifo.v:12$1'. -Cleaned up 2 empty switches. - -yosys> select -set new_cells t:$mux t:*dff - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc - -8. Generating Graphviz representation of design. -Writing dot description to `addr_gen_proc.dot'. -Dumping module addr_gen to page 1. - -yosys> opt_expr - -9. Executing OPT_EXPR pass (perform const folding). -Optimizing module addr_gen. - -yosys> clean -Removed 0 unused cells and 4 unused wires. - -yosys> select -set new_cells t:$eq - -yosys> show -color cornflowerblue @new_cells -notitle -format dot -prefix addr_gen_clean - -10. Generating Graphviz representation of design. -Writing dot description to `addr_gen_clean.dot'. -Dumping module addr_gen to page 1. - -yosys> design -reset - -yosys> read_verilog fifo.v - -11. Executing Verilog-2005 frontend: fifo.v -Parsing Verilog input from `fifo.v' to AST representation. -Generating RTLIL representation for module `\addr_gen'. -Generating RTLIL representation for module `\fifo'. -Successfully finished Verilog frontend. - -yosys> hierarchy -check -top fifo - -12. Executing HIERARCHY pass (managing design hierarchy). - -12.1. Analyzing design hierarchy.. -Top module: \fifo -Used module: \addr_gen -Parameter \MAX_DATA = 256 - -12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'. -Parameter \MAX_DATA = 256 -Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'. -Parameter \MAX_DATA = 256 -Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'. - -12.3. Analyzing design hierarchy.. -Top module: \fifo -Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 - -12.4. Analyzing design hierarchy.. -Top module: \fifo -Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 -Removing unused module `\addr_gen'. -Removed 1 unused modules. - -yosys> proc - -13. Executing PROC pass (convert processes to netlists). - -yosys> proc_clean - -13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -yosys> proc_rmdead - -13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 2 switch rules as full_case in process $proc$fifo.v:62$24 in module fifo. -Marked 1 switch rules as full_case in process $proc$fifo.v:36$16 in module fifo. -Marked 2 switch rules as full_case in process $proc$fifo.v:12$32 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. -Removed a total of 0 dead cases. - -yosys> proc_prune - -13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 6 assignments to connections. - -yosys> proc_init - -13.4. Executing PROC_INIT pass (extract init attributes). -Found init rule in `\fifo.$proc$fifo.v:0$31'. - Set init value: \count = 9'000000000 -Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'. - Set init value: \addr = 8'00000000 - -yosys> proc_arst - -13.5. Executing PROC_ARST pass (detect async resets in processes). -Found async reset \rst in `\fifo.$proc$fifo.v:62$24'. -Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. - -yosys> proc_rom - -13.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - - -yosys> proc_mux - -13.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\fifo.$proc$fifo.v:0$31'. -Creating decoders for process `\fifo.$proc$fifo.v:62$24'. - 1/1: $0\count[8:0] -Creating decoders for process `\fifo.$proc$fifo.v:36$16'. - 1/3: $1$memwr$\data$fifo.v:38$15_EN[7:0]$22 - 2/3: $1$memwr$\data$fifo.v:38$15_DATA[7:0]$21 - 3/3: $1$memwr$\data$fifo.v:38$15_ADDR[7:0]$20 -Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'. -Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. - 1/1: $0\addr[7:0] - -yosys> proc_dlatch - -13.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -yosys> proc_dff - -13.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:62$24'. - created $adff cell `$procdff$55' with positive edge clock and positive level reset. -Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:36$16'. - created $dff cell `$procdff$56' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_ADDR' using process `\fifo.$proc$fifo.v:36$16'. - created $dff cell `$procdff$57' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_DATA' using process `\fifo.$proc$fifo.v:36$16'. - created $dff cell `$procdff$58' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_EN' using process `\fifo.$proc$fifo.v:36$16'. - created $dff cell `$procdff$59' with positive edge clock. -Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. - created $adff cell `$procdff$60' with positive edge clock and positive level reset. - -yosys> proc_memwr - -13.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -yosys> proc_clean - -13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `fifo.$proc$fifo.v:0$31'. -Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:62$24'. -Removing empty process `fifo.$proc$fifo.v:62$24'. -Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:36$16'. -Removing empty process `fifo.$proc$fifo.v:36$16'. -Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'. -Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. -Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. -Cleaned up 5 empty switches. - -yosys> opt_expr -keepdc - -13.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module fifo. -Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. - -yosys> select -set new_cells t:$memrd - -yosys> show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci* - -14. Generating Graphviz representation of design. -Writing dot description to `rdata_proc.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> flatten - -15. Executing FLATTEN pass (flatten design). -Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. - - -yosys> clean -Removed 3 unused cells and 25 unused wires. - -yosys> select -set rdata_path o:rdata %ci* - -yosys> select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path - -16. Generating Graphviz representation of design. -Writing dot description to `rdata_flat.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> opt_dff - -17. Executing OPT_DFF pass (perform DFF optimizations). -Adding EN signal on $procdff$55 ($adff) from module fifo (D = $0\count[8:0], Q = \count). -Adding EN signal on $flatten\fifo_writer.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$51_Y, Q = \fifo_writer.addr). -Adding EN signal on $flatten\fifo_reader.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$51_Y, Q = \fifo_reader.addr). - -yosys> select -set new_cells t:$adffe - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci* - -18. Generating Graphviz representation of design. -Writing dot description to `rdata_adffe.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> wreduce - -19. Executing WREDUCE pass (reducing word size of cells). -Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:66$27 ($add). -Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:66$27 ($add). -Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:68$30 ($sub). -Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:68$30 ($sub). -Removed top 1 bits (of 2) from port B of cell fifo.$auto$opt_dff.cc:195:make_patterns_logic$66 ($ne). -Removed cell fifo.$flatten\fifo_writer.$procmux$53 ($mux). -Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$34 ($add). -Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$34 ($add). -Removed cell fifo.$flatten\fifo_reader.$procmux$53 ($mux). -Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$34 ($add). -Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$34 ($add). -Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:66$27_Y. -Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_reader.$add$fifo.v:19$34_Y. - -yosys> show -notitle -format dot -prefix rdata_wreduce o:rdata %ci* - -20. Generating Graphviz representation of design. -Writing dot description to `rdata_wreduce.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> opt_clean - -21. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \fifo.. -Removed 0 unused cells and 4 unused wires. - - -yosys> memory_dff - -22. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Checking read port `\data'[0] in module `\fifo': merging output FF to cell. - Write port 0: non-transparent. - -yosys> select -set new_cells t:$memrd_v2 - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci* - -23. Generating Graphviz representation of design. -Writing dot description to `rdata_memrdv2.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> alumacc - -24. Executing ALUMACC pass (create $alu and $macc cells). -Extracting $alu and $macc cells in module fifo: - creating $macc model for $add$fifo.v:66$27 ($add). - creating $macc model for $flatten\fifo_reader.$add$fifo.v:19$34 ($add). - creating $macc model for $flatten\fifo_writer.$add$fifo.v:19$34 ($add). - creating $macc model for $sub$fifo.v:68$30 ($sub). - creating $alu model for $macc $sub$fifo.v:68$30. - creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:19$34. - creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:19$34. - creating $alu model for $macc $add$fifo.v:66$27. - creating $alu cell for $add$fifo.v:66$27: $auto$alumacc.cc:485:replace_alu$80 - creating $alu cell for $flatten\fifo_reader.$add$fifo.v:19$34: $auto$alumacc.cc:485:replace_alu$83 - creating $alu cell for $flatten\fifo_writer.$add$fifo.v:19$34: $auto$alumacc.cc:485:replace_alu$86 - creating $alu cell for $sub$fifo.v:68$30: $auto$alumacc.cc:485:replace_alu$89 - created 4 $alu and 0 $macc cells. - -yosys> select -set new_cells t:$alu t:$macc - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci* - -25. Generating Graphviz representation of design. -Writing dot description to `rdata_alumacc.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> memory_collect - -26. Executing MEMORY_COLLECT pass (generating $mem cells). - -yosys> select -set new_cells t:$mem_v2 - -yosys> select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %% - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path - -27. Generating Graphviz representation of design. -Writing dot description to `rdata_coarse.dot'. -Dumping selected parts of module fifo to page 1. diff --git a/docs/source/code_examples/fifo/fifo.stat b/docs/source/code_examples/fifo/fifo.stat deleted file mode 100644 index 263c618e3..000000000 --- a/docs/source/code_examples/fifo/fifo.stat +++ /dev/null @@ -1,57 +0,0 @@ - -yosys> stat - -2. Printing statistics. - -=== fifo === - - Number of wires: 28 - Number of wire bits: 219 - Number of public wires: 9 - Number of public wire bits: 45 - Number of memories: 1 - Number of memory bits: 2048 - Number of processes: 3 - Number of cells: 9 - $add 1 - $logic_and 2 - $logic_not 2 - $memrd 1 - $sub 1 - addr_gen 2 - -=== addr_gen === - - Number of wires: 8 - Number of wire bits: 60 - Number of public wires: 4 - Number of public wire bits: 11 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 2 - Number of cells: 2 - $add 1 - $eq 1 - - -yosys> stat -top fifo - -17. Printing statistics. - -=== fifo === - - Number of wires: 94 - Number of wire bits: 260 - Number of public wires: 94 - Number of public wire bits: 260 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 138 - $scopeinfo 2 - SB_CARRY 26 - SB_DFF 26 - SB_DFFER 25 - SB_LUT4 58 - SB_RAM40_4K 1 - diff --git a/docs/source/code_examples/selections/Makefile b/docs/source/code_examples/selections/Makefile index 3ad1bcf20..46a09060a 100644 --- a/docs/source/code_examples/selections/Makefile +++ b/docs/source/code_examples/selections/Makefile @@ -14,12 +14,12 @@ SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD)) .PHONY: all dots examples all: dots examples dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS) -examples: +examples: sumprod.out select.dot: select.v select.ys $(YOSYS) select.ys -$(SUMPROD_DOTS): sumprod.v sumprod.ys +$(SUMPROD_DOTS) sumprod.out: sumprod.v sumprod.ys $(YOSYS) sumprod.ys $(MEMDEMO_DOTS): memdemo.v memdemo.ys @@ -31,3 +31,4 @@ $(SUBMOD_DOTS): memdemo.v submod.ys .PHONY: clean clean: rm -rf *.dot + rm -f sumprod.out diff --git a/docs/source/code_examples/selections/sumprod.out b/docs/source/code_examples/selections/sumprod.out deleted file mode 100644 index f7c259499..000000000 --- a/docs/source/code_examples/selections/sumprod.out +++ /dev/null @@ -1,38 +0,0 @@ - - - attribute \src "sumprod.v:4.21-4.25" - wire width 8 output 5 \prod - - attribute \src "sumprod.v:10.17-10.26" - cell $mul $mul$sumprod.v:10$4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $mul$sumprod.v:10$3_Y - connect \B \c - connect \Y \prod - end - - - attribute \src "sumprod.v:10.17-10.22" - wire width 8 $mul$sumprod.v:10$3_Y - - attribute \src "sumprod.v:3.21-3.22" - wire width 8 input 3 \c - - attribute \src "sumprod.v:4.21-4.25" - wire width 8 output 5 \prod - - attribute \src "sumprod.v:10.17-10.26" - cell $mul $mul$sumprod.v:10$4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $mul$sumprod.v:10$3_Y - connect \B \c - connect \Y \prod - end diff --git a/docs/source/code_examples/show/Makefile b/docs/source/code_examples/show/Makefile index 6c1906cce..649691299 100644 --- a/docs/source/code_examples/show/Makefile +++ b/docs/source/code_examples/show/Makefile @@ -28,3 +28,4 @@ $(CMOS_DOTS): cmos.v cmos.ys .PHONY: clean clean: rm -rf *.dot + rm -f example.out diff --git a/docs/source/code_examples/show/example.out b/docs/source/code_examples/show/example.out deleted file mode 100644 index b8569e640..000000000 --- a/docs/source/code_examples/show/example.out +++ /dev/null @@ -1,54 +0,0 @@ - --- Executing script file `example_lscd.ys' -- - -1. Executing Verilog-2005 frontend: example.v -Parsing Verilog input from `example.v' to AST representation. -Generating RTLIL representation for module `\example'. -Successfully finished Verilog frontend. -echo on - -yosys> ls - -1 modules: - example - -yosys> cd example - -yosys [example]> ls - -8 wires: - $0\y[1:0] - $add$example.v:5$2_Y - $ternary$example.v:5$3_Y - a - b - c - clk - y - -2 cells: - $add$example.v:5$2 - $ternary$example.v:5$3 - -1 processes: - $proc$example.v:3$1 - -yosys [example]> dump $2 - - - attribute \src "example.v:5.22-5.27" - cell $add $add$example.v:5$2 - parameter \Y_WIDTH 2 - parameter \B_WIDTH 1 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \A_SIGNED 0 - connect \Y $add$example.v:5$2_Y - connect \B \b - connect \A \a - end - -yosys [example]> cd .. - -yosys> echo off -echo off From 13d7b5fd6aab92e1f28900e778bff1c9505f5e34 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:01:01 +1300 Subject: [PATCH 055/240] Docs: Ignore example outputs --- docs/source/code_examples/.gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/source/code_examples/.gitignore b/docs/source/code_examples/.gitignore index b4a858a01..0eca4be80 100644 --- a/docs/source/code_examples/.gitignore +++ b/docs/source/code_examples/.gitignore @@ -1,2 +1,5 @@ *.dot *.pdf +*.out +*.log +*.stat From 3e6e8c892e9f44c933c2ffc4c660cc38370ea69d Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 7 Oct 2024 11:09:02 +0200 Subject: [PATCH 056/240] Bump abc submodule --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 2188bc712..cac8f99ea 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 2188bc71228b0788569d83ad2b7e7b91ca5dcc09 +Subproject commit cac8f99eaa220a5e3db5caeb87cef0a975c953a2 From edf29e725e82a1bf5914089374f4a0e237ae51db Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:20:22 +1300 Subject: [PATCH 057/240] Docs: Add functional_ir to index --- docs/source/yosys_internals/extending_yosys/index.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/source/yosys_internals/extending_yosys/index.rst b/docs/source/yosys_internals/extending_yosys/index.rst index 2a4d2dfef..88f36d526 100644 --- a/docs/source/yosys_internals/extending_yosys/index.rst +++ b/docs/source/yosys_internals/extending_yosys/index.rst @@ -10,5 +10,6 @@ of interest for developers looking to customise Yosys builds. extensions build_verific + functional_ir test_suites From 33930e44ac70313b12fe6945450cceb45b7b1202 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:22:10 +1300 Subject: [PATCH 058/240] ci: Test build docs --- .github/workflows/test-build.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index e5aed6af3..41e197424 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -189,3 +189,8 @@ jobs: shell: bash run: | make -C docs test -j${{ env.procs }} + + - name: Test build docs + shell: bash + run: | + make -C docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= From f72d0219d151183ced4de2fe2be533c102b645b3 Mon Sep 17 00:00:00 2001 From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:52:33 +1300 Subject: [PATCH 059/240] Update test-build.yml Call make docs from root --- .github/workflows/test-build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 41e197424..1502d8aa0 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -193,4 +193,4 @@ jobs: - name: Test build docs shell: bash run: | - make -C docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= + make docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= From d4e009fc2f7152cd3c26f7776c711745a5a90257 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Oct 2024 11:28:19 +0200 Subject: [PATCH 060/240] aiger2: Add TODO --- backends/aiger2/aiger.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 6af7b0948..89ef06a37 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -20,6 +20,7 @@ // TODOs: // - gracefully handling inout ports (an error message probably) // - undriven wires +// - zero-width operands #include "kernel/register.h" #include "kernel/celltypes.h" From e58a9b6ab6cd990a5f2cbe396972a1bdcd7ccb7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 9 Apr 2024 18:30:51 +0200 Subject: [PATCH 061/240] abc9: Understand ASIC options similar to `abc` --- passes/techmap/abc9.cc | 3 ++- passes/techmap/abc9_exe.cc | 43 +++++++++++++++++++++++++++++++------- 2 files changed, 38 insertions(+), 8 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 876917e56..a96a82659 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -220,7 +220,8 @@ struct Abc9Pass : public ScriptPass std::string arg = args[argidx]; if ((arg == "-exe" || arg == "-script" || arg == "-D" || /*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" || - /*arg == "-box" ||*/ arg == "-W") && + /*arg == "-box" ||*/ arg == "-W" || arg == "-genlib" || + arg == "-constr" || arg == "-dont_use" || arg == "-liberty") && argidx+1 < args.size()) { if (arg == "-lut" || arg == "-luts") lut_mode = true; diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 8e02e25a4..e62850aa4 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -166,9 +166,9 @@ struct abc9_output_filter void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe_file, vector lut_costs, bool dff_mode, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, - bool show_tempdir, std::string box_file, std::string lut_file, - std::string wire_delay, std::string tempdir_name -) + bool show_tempdir, std::string box_file, std::string lut_file, std::vector genlib_files, + std::vector liberty_files, std::string wire_delay, std::string tempdir_name, + std::string constr_file, std::vector dont_use_cells) { std::string abc9_script; @@ -176,8 +176,19 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); else if (!lut_file.empty()) abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str()); - else - log_abort(); + else if (!liberty_files.empty() || !genlib_files.empty()) { + std::string dont_use_args; + for (std::string dont_use_cell : dont_use_cells) { + dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str()); + } + for (std::string liberty_file : liberty_files) { + abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str()); + } + for (std::string liberty_file : genlib_files) + abc9_script += stringf("read_library \"%s\"; ", liberty_file.c_str()); + if (!constr_file.empty()) + abc9_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str()); + } log_assert(!box_file.empty()); abc9_script += stringf("read_box \"%s\"; ", box_file.c_str()); @@ -411,7 +422,8 @@ struct Abc9ExePass : public Pass { log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n"); std::string exe_file = yosys_abc_executable; - std::string script_file, clk_str, box_file, lut_file; + std::string script_file, clk_str, box_file, lut_file, constr_file; + std::vector genlib_files, liberty_files, dont_use_cells; std::string delay_target, lutin_shared = "-S 1", wire_delay; std::string tempdir_name; bool fast_mode = false, dff_mode = false; @@ -499,6 +511,22 @@ struct Abc9ExePass : public Pass { tempdir_name = args[++argidx]; continue; } + if (arg == "-genlib" && argidx+1 < args.size()) { + genlib_files.push_back(args[++argidx]); + continue; + } + if (arg == "-liberty" && argidx+1 < args.size()) { + liberty_files.push_back(args[++argidx]); + continue; + } + if (arg == "-dont_use" && argidx+1 < args.size()) { + dont_use_cells.push_back(args[++argidx]); + continue; + } + if (arg == "-constr" && argidx+1 < args.size()) { + constr_file = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -562,7 +590,8 @@ struct Abc9ExePass : public Pass { abc9_module(design, script_file, exe_file, lut_costs, dff_mode, delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, wire_delay, tempdir_name); + box_file, lut_file, genlib_files, liberty_files, wire_delay, tempdir_name, + constr_file, dont_use_cells); } } Abc9ExePass; From 2b1b5652f1106466dfc538d52bffbe336013de85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 4 Oct 2024 10:02:53 +0200 Subject: [PATCH 062/240] Adjust `read_xaiger2` prints --- frontends/aiger2/xaiger.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index b60cd0c88..56fa5a2a6 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -222,10 +222,12 @@ struct Xaiger2Frontend : public Frontend { } else { uint32_t len = read_be32(*f); f->ignore(len); - log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len); } } + log_debug("reading 'M' (second pass)\n"); + f->seekg(extensions_start); bool read_mapping = false; uint32_t no_cells, no_instances; @@ -272,7 +274,6 @@ struct Xaiger2Frontend : public Frontend { auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit))); instance->setPort(cell.out, out_w); bits[out_lit] = out_w; - log_debug("setting %d (driven by %s)\n", out_lit, log_id(cell.type)); for (auto in : cell.ins) { uint32_t in_lit = read_be32(*f); log_assert(out_lit < bits.size()); @@ -285,7 +286,7 @@ struct Xaiger2Frontend : public Frontend { } else { uint32_t len = read_be32(*f); f->ignore(len); - log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len); } } @@ -356,7 +357,7 @@ struct Xaiger2Frontend : public Frontend { } else { uint32_t len = read_be32(*f); f->ignore(len); - log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len); } } @@ -387,7 +388,6 @@ struct Xaiger2Frontend : public Frontend { int lit = outputs[po_idx]; if (lit < 0 || lit >= bits.size()) log_error("Bad map file (5)\n"); - log("output=%d lit=%d\n", po_idx, lit); if (bits[lit] == RTLIL::Sm) log_error("Bad map file (6)\n"); Wire *w = module->wire(name); From 8d12492610e0fdfff84b12fb0fc337daf4e74055 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 4 Oct 2024 10:03:30 +0200 Subject: [PATCH 063/240] read_xaiger2: Fix detecting the end of extensions --- frontends/aiger2/xaiger.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 56fa5a2a6..4c7305876 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -219,6 +219,8 @@ struct Xaiger2Frontend : public Frontend { log_assert(pi_num + ci_counter == ci_num); } else if (c == '\n') { break; + } else if (c == 'c') { + break; } else { uint32_t len = read_be32(*f); f->ignore(len); @@ -283,6 +285,8 @@ struct Xaiger2Frontend : public Frontend { } } else if (c == '\n') { break; + } else if (c == 'c') { + break; } else { uint32_t len = read_be32(*f); f->ignore(len); @@ -354,6 +358,8 @@ struct Xaiger2Frontend : public Frontend { log_assert(po_num + co_counter == co_num); } else if (c == '\n') { break; + } else if (c == 'c') { + break; } else { uint32_t len = read_be32(*f); f->ignore(len); From f7c7371ea9157ef1199c4a76d20364b3699313b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:03:52 +0200 Subject: [PATCH 064/240] aiger2: Fix relative ordering of PI/POs and box I/Os --- backends/aiger2/aiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 89ef06a37..9df9c9b20 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -934,7 +934,7 @@ struct XAigerWriter : AigerWriter { }); for (auto [cursor, box, def] : opaque_boxes) - append_box_ports(box, cursor, true); + append_box_ports(box, cursor, false); holes_module = design->addModule(NEW_ID); std::vector holes_pis; @@ -1024,7 +1024,7 @@ struct XAigerWriter : AigerWriter { } for (auto [cursor, box, def] : opaque_boxes) - append_box_ports(box, cursor, false); + append_box_ports(box, cursor, true); write_be32(h_buffer, 1); write_be32(h_buffer, pis.size()); From 4c0a8a132614ee354913815f3b651f8735a3a730 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:04:45 +0200 Subject: [PATCH 065/240] aiger2: Add analysis step to order boxes --- backends/aiger2/aiger.cc | 122 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 9df9c9b20..b6994c221 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -537,6 +537,11 @@ struct Index { } }; + bool visit_hook(int idx, HierCursor &cursor, SigBit bit) + { + return false; + } + Lit visit(HierCursor &cursor, SigBit bit) { if (!bit.wire) { @@ -554,6 +559,12 @@ struct Index { return lits[idx]; } + // provide means for the derived class to override + // the visit behavior + if ((static_cast(this))->visit_hook(idx, cursor, bit)) { + return lits[idx]; + } + Lit ret; if (!bit.wire->port_input) { // an output of a cell @@ -791,6 +802,102 @@ struct AigerWriter : Index { } }; +struct XAigerAnalysis : Index { + const static int CONST_FALSE = 0; + const static int CONST_TRUE = 0; + const static constexpr int EMPTY_LIT = -1; + + XAigerAnalysis() + { + allow_blackboxes = true; + + // Disable const folding and strashing as literal values are not unique + const_folding = false; + strashing = false; + } + + static int negate(int lit) + { + return lit; + } + + int emit_gate(int a, int b) + { + return max(a, b) + 1; + } + + pool seen; + + bool visit_hook(int idx, HierCursor &cursor, SigBit bit) + { + log_assert(cursor.is_top()); // TOOD: fix analyzer to work with hierarchy + + if (bit.wire->port_input) + return false; + + Cell *driver = bit.wire->driverCell(); + if (!driver->type.isPublic()) + return false; + + Module *mod = design->module(driver->type); + log_assert(mod); + if (!mod->has_attribute(ID::abc9_box_id)) + return false; + + int max = 1; + for (auto wire : mod->wires()) + if (wire->port_input) + for (int i = 0; i < wire->width; i++) { + int ilevel = visit(cursor, driver->getPort(wire->name)[i]); + max = std::max(max, ilevel + 1); + } + lits[idx] = max; + + if (!seen.count(driver)) + seen.insert(driver); + + return true; + } + + void analyze(Module *top) + { + setup(top); + + for (auto id : top->ports) { + Wire *w = top->wire(id); + log_assert(w); + if (w->port_input) + for (int i = 0; i < w->width; i++) + pi_literal(SigBit(w, i)) = 0; + } + + HierCursor cursor; + for (auto box : top_minfo->found_blackboxes) { + Module *def = design->module(box->type); + if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id))) + for (auto &conn : box->connections_) + if (box->output(conn.first)) + for (auto bit : conn.second) + pi_literal(bit, &cursor) = 0; + } + + for (auto w : top->wires()) + if (w->port_output) { + for (auto bit : SigSpec(w)) + (void) eval_po(bit); + } + + for (auto box : top_minfo->found_blackboxes) { + Module *def = design->module(box->type); + if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id))) + for (auto &conn : box->connections_) + if (box->input(conn.first)) + for (auto bit : conn.second) + (void) eval_po(bit); + } + } +}; + struct XAigerWriter : AigerWriter { XAigerWriter() { @@ -897,6 +1004,11 @@ struct XAigerWriter : AigerWriter { void prep_boxes(int pending_pos_num) { + XAigerAnalysis analysis; + log_debug("preforming analysis on '%s'\n", log_id(top)); + analysis.analyze(top); + log_debug("analysis on '%s' done\n", log_id(top)); + // boxes which have timing data, maybe a whitebox model std::vector> nonopaque_boxes; // boxes which are fully opaque @@ -942,6 +1054,16 @@ struct XAigerWriter : AigerWriter { int box_seq = 0; + std::vector boxes_order(analysis.seen.begin(), analysis.seen.end()); + std::reverse(boxes_order.begin(), boxes_order.end()); + + nonopaque_boxes.clear(); + for (auto box : boxes_order) { + HierCursor cursor; + Module *def = design->module(box->type); + nonopaque_boxes.push_back(std::make_tuple(cursor, box, def)); + } + for (auto [cursor, box, def] : nonopaque_boxes) { // use `def->name` not `box->type` as we want the derived type Cell *holes_wb = holes_module->addCell(NEW_ID, def->name); From b8f389370b0fb3ecb520a9a02d0cda744315aea5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:05:44 +0200 Subject: [PATCH 066/240] aiger2: Convert x-states to zeroes --- backends/aiger2/aiger.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index b6994c221..97b506178 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -549,6 +549,8 @@ struct Index { return CTRUE; else if (bit == State::S0) return CFALSE; + else if (bit == State::Sx) + return CFALSE; else log_error("Unhandled state %s\n", log_signal(bit)); } From e0a86d5483804f4c4977c353232e64e70c539582 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:07:25 +0200 Subject: [PATCH 067/240] abc_new: Start new command for aiger2-based round trip --- passes/techmap/Makefile.inc | 2 + passes/techmap/abc_new.cc | 153 ++++++++++++++++++++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 passes/techmap/abc_new.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 6bf40434d..4e1d16744 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -12,10 +12,12 @@ OBJS += passes/techmap/abc.o OBJS += passes/techmap/abc9.o OBJS += passes/techmap/abc9_exe.o OBJS += passes/techmap/abc9_ops.o +OBJS += passes/techmap/abc_new.o ifneq ($(ABCEXTERNAL),) passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' passes/techmap/abc9_exe.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' +passes/techmap/abc_new.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' endif endif diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc new file mode 100644 index 000000000..eefe34f84 --- /dev/null +++ b/passes/techmap/abc_new.cc @@ -0,0 +1,153 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Martin PoviĊĦer + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/rtlil.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct AbcNewPass : public ScriptPass { + AbcNewPass() : ScriptPass("abc_new", "(experimental) use ABC for SC technology mapping (new)") + { + experimental(); + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" abc_new [options] [selection]\n"); + log("\n"); + log("This command uses the ABC tool [1] to optimize the current design and map it to\n"); + log("the target standard cell library.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -exe \n"); + log(" -script \n"); + log(" -D \n"); + log(" -constr \n"); + log(" -dont_use \n"); + log(" -liberty \n"); + log(" these options are passed on to the 'abc9_exe' command which invokes\n"); + log(" the ABC tool on individual modules of the design. please see\n"); + log(" 'help abc9_exe' for more details\n"); + log("\n"); + log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); + log("\n"); + help_script(); + log("\n"); + } + + bool cleanup; + std::string abc_exe_options; + + void execute(std::vector args, RTLIL::Design *d) override + { + std::string run_from, run_to; + cleanup = true; + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-exe" || args[argidx] == "-script" || + args[argidx] == "-D" || + args[argidx] == "-constr" || args[argidx] == "-dont_use" || + args[argidx] == "-liberty") { + abc_exe_options += " " + args[argidx] + " " + args[argidx + 1]; + argidx++; + } else if (args[argidx] == "-run" && argidx + 1 < args.size()) { + size_t pos = args[++argidx].find(':'); + if (pos == std::string::npos) + break; + run_from = args[argidx].substr(0, pos); + run_to = args[argidx].substr(pos + 1); + } else if (args[argidx] == "-nocleanup") { + cleanup = false; + } else { + break; + } + } + extra_args(args, argidx, d); + + log_header(d, "Executing ABC_NEW pass.\n"); + log_push(); + run_script(d, run_from, run_to); + log_pop(); + } + + void script() override + { + if (check_label("check")) { + run("abc9_ops -check"); + } + + if (check_label("prep_boxes")) { + run("box_derive"); + run("abc9_ops -prep_box"); + } + + if (check_label("map")) { + std::vector selected_modules; + + if (!help_mode) { + selected_modules = active_design->selected_whole_modules_warn(); + active_design->selection_stack.emplace_back(false); + } else { + selected_modules = {nullptr}; + run("foreach module in selection"); + } + + for (auto mod : selected_modules) { + std::string tmpdir = ""; + std::string modname = ""; + std::string exe_options = "[options]"; + if (!help_mode) { + tmpdir = cleanup ? (get_base_tmpdir() + "/") : "_tmp_"; + tmpdir += proc_program_prefix() + "yosys-abc-XXXXXX"; + tmpdir = make_temp_dir(tmpdir); + modname = mod->name.str(); + exe_options = abc_exe_options; + log_header(active_design, "Mapping module '%s'.\n", log_id(mod)); + log_push(); + active_design->selection().select(mod); + } + + run(stringf(" abc9_ops -write_box %s/input.box", tmpdir.c_str())); + run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir.c_str(), tmpdir.c_str())); + run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options.c_str(), tmpdir.c_str(), tmpdir.c_str())); + run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig", + modname.c_str(), tmpdir.c_str(), tmpdir.c_str())); + + if (!help_mode) { + active_design->selection().selected_modules.clear(); + log_pop(); + } + } + + if (!help_mode) { + active_design->selection_stack.pop_back(); + } + } + } +} AbcNewPass; + +PRIVATE_NAMESPACE_END From 81688e3ba2fb4a1dba403541512825264281df76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:12:16 +0200 Subject: [PATCH 068/240] aigsize: Remove --- backends/aiger2/aiger.cc | 66 ---------------------------------------- 1 file changed, 66 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 97b506178..336dad7a7 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1434,70 +1434,4 @@ struct XAiger2Backend : Backend { } } XAiger2Backend; -struct AIGCounter : Index { - typedef int Lit; - const static Lit CONST_FALSE = -1; - const static Lit CONST_TRUE = 1; - const static constexpr Lit EMPTY_LIT = 0; - static Lit negate(Lit lit) { return -lit; } - int nvars = 1; - int ngates = 0; - - Lit emit_gate([[maybe_unused]] Lit a, [[maybe_unused]] Lit b) - { - ngates++; - return ++nvars; - } - - void count() { - // populate inputs - for (auto w : top->wires()) - if (w->port_input) - for (int i = 0; i < w->width; i++) - pi_literal(SigBit(w, i)) = ++nvars; - - for (auto w : top->wires()) - if (w->port_output) { - for (auto bit : SigSpec(w)) - (void) eval_po(bit); - } - } -}; - -struct AigsizePass : Pass { - AigsizePass() : Pass("aigsize", "estimate AIG size for design") {} - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing AIGSIZE pass. (size design AIG)\n"); - - size_t argidx; - AIGCounter writer; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-strash") - writer.strashing = true; - else if (args[argidx] == "-flatten") - writer.flatten = true; - else - break; - } - extra_args(args, argidx, design); - - Module *top = design->top_module(); - - if (!top || !design->selected_whole_module(top)) - log_cmd_error("No top module selected\n"); - - design->bufNormalize(true); - writer.setup(top); - writer.count(); - log("Counted %d gates\n", writer.ngates); - - // we are leaving the sacred land, un-bufnormalize - // (if not, this will lead to bugs: the buf-normalized - // flag must not be kept on past the code that can work - // with it) - design->bufNormalize(false); - } -} AigsizePass; - PRIVATE_NAMESPACE_END From ac79a052ba9013580eadc26f4c9032819f162cb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:12:29 +0200 Subject: [PATCH 069/240] aiger2: Adjust help --- backends/aiger2/aiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 336dad7a7..a6a4b841a 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1300,7 +1300,7 @@ struct XAigerWriter : AigerWriter { }; struct Aiger2Backend : Backend { - Aiger2Backend() : Backend("aiger2", "write design to AIGER file (new)") + Aiger2Backend() : Backend("aiger2", "(experimental) write design to AIGER file") { experimental(); } @@ -1384,7 +1384,7 @@ struct Aiger2Backend : Backend { } Aiger2Backend; struct XAiger2Backend : Backend { - XAiger2Backend() : Backend("xaiger2", "write design to XAIGER file (new)") + XAiger2Backend() : Backend("xaiger2", "(experimental) write design to XAIGER file") { experimental(); } From 3b6dcc7bd0370bff5fde16cfa0406bc60356eace Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:30:22 +0200 Subject: [PATCH 070/240] abc9_exe: Remove `-genlib` option --- passes/techmap/abc9_exe.cc | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index e62850aa4..ccfc7a7f8 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -166,7 +166,7 @@ struct abc9_output_filter void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe_file, vector lut_costs, bool dff_mode, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, - bool show_tempdir, std::string box_file, std::string lut_file, std::vector genlib_files, + bool show_tempdir, std::string box_file, std::string lut_file, std::vector liberty_files, std::string wire_delay, std::string tempdir_name, std::string constr_file, std::vector dont_use_cells) { @@ -176,7 +176,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); else if (!lut_file.empty()) abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str()); - else if (!liberty_files.empty() || !genlib_files.empty()) { + else if (!liberty_files.empty()) { std::string dont_use_args; for (std::string dont_use_cell : dont_use_cells) { dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str()); @@ -184,8 +184,6 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe for (std::string liberty_file : liberty_files) { abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str()); } - for (std::string liberty_file : genlib_files) - abc9_script += stringf("read_library \"%s\"; ", liberty_file.c_str()); if (!constr_file.empty()) abc9_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str()); } @@ -423,7 +421,7 @@ struct Abc9ExePass : public Pass { std::string exe_file = yosys_abc_executable; std::string script_file, clk_str, box_file, lut_file, constr_file; - std::vector genlib_files, liberty_files, dont_use_cells; + std::vector liberty_files, dont_use_cells; std::string delay_target, lutin_shared = "-S 1", wire_delay; std::string tempdir_name; bool fast_mode = false, dff_mode = false; @@ -511,10 +509,6 @@ struct Abc9ExePass : public Pass { tempdir_name = args[++argidx]; continue; } - if (arg == "-genlib" && argidx+1 < args.size()) { - genlib_files.push_back(args[++argidx]); - continue; - } if (arg == "-liberty" && argidx+1 < args.size()) { liberty_files.push_back(args[++argidx]); continue; @@ -590,7 +584,7 @@ struct Abc9ExePass : public Pass { abc9_module(design, script_file, exe_file, lut_costs, dff_mode, delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, genlib_files, liberty_files, wire_delay, tempdir_name, + box_file, lut_file, liberty_files, wire_delay, tempdir_name, constr_file, dont_use_cells); } } Abc9ExePass; From 2e587c835fd95eac7ac5114f26f07f9f3f5982e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:30:37 +0200 Subject: [PATCH 071/240] abc9_exe: Document SC mapping options --- passes/techmap/abc9_exe.cc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index ccfc7a7f8..651a8375c 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -368,6 +368,26 @@ struct Abc9ExePass : public Pass { log(" of output quality):\n"); log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str()); log("\n"); + log(" -constr \n"); + log(" pass this file with timing constraints to ABC.\n"); + log(" use with -liberty.\n"); + log("\n"); + log(" a constr file contains two lines:\n"); + log(" set_driving_cell \n"); + log(" set_load \n"); + log("\n"); + log(" the set_driving_cell statement defines which cell type is assumed to\n"); + log(" drive the primary inputs and the set_load statement sets the load in\n"); + log(" femtofarads for each primary output.\n"); + log("\n"); + log(" -liberty \n"); + log(" read the given Liberty file as a description of the target cell library.\n"); + log(" this option can be used multiple times.\n"); + log("\n"); + log(" -dont_use \n"); + log(" avoid usage of the technology cell when mapping the design.\n"); + log(" this option can be used multiple times.\n"); + log("\n"); log(" -D \n"); log(" set delay target. the string {D} in the default scripts above is\n"); log(" replaced by this option when used, and an empty string otherwise\n"); From ebe51e206ea036090d6068a6fa9e26d7b2c769b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:37:53 +0200 Subject: [PATCH 072/240] aiger2: Fix warnings --- backends/aiger2/aiger.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index a6a4b841a..0406ca0ac 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -222,8 +222,8 @@ struct Index { std::vector next; while (lits.size() > 1) { next.clear(); - for (int i = 0; i < lits.size(); i += 2) { - if (i + 1 >= lits.size()) { + for (int i = 0; i < (int) lits.size(); i += 2) { + if (i + 1 >= (int) lits.size()) { next.push_back(lits[i]); } else { Lit a = lits[i], b = lits[i + 1]; @@ -430,7 +430,7 @@ struct Index { for (int i = 0; i < sport.size(); i++) { Lit s = visit(cursor, sport[i]); next.clear(); - for (int j = 0; j < data.size(); j += 2) + for (int j = 0; j < (int) data.size(); j += 2) next.push_back(MUX(data[j], data[j + 1], s)); data.swap(next); } @@ -537,7 +537,7 @@ struct Index { } }; - bool visit_hook(int idx, HierCursor &cursor, SigBit bit) + bool visit_hook(int, HierCursor&, SigBit) { return false; } From 373e7a1485a1e8942429dd6df9fecc4fe687eb5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 19:23:11 +0200 Subject: [PATCH 073/240] aiger2: Fix print --- backends/aiger2/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0406ca0ac..8de482bc0 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1154,7 +1154,7 @@ struct XAigerWriter : AigerWriter { write_be32(h_buffer, pis.size()); log_debug("ciNum = %zu\n", pis.size()); write_be32(h_buffer, pending_pos_num + pos.size()); - log_debug("coNum = %zu\n", boxes_co_num + pos.size()); + log_debug("coNum = %zu\n", pending_pos_num + pos.size()); write_be32(h_buffer, pis.size() - boxes_ci_num); log_debug("piNum = %zu\n", pis.size() - boxes_ci_num); write_be32(h_buffer, pending_pos_num + pos.size() - boxes_co_num); From 47fd2b9debadb877837c81f37bad1fd8da8c0476 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 19:23:30 +0200 Subject: [PATCH 074/240] aiger2: Update help --- backends/aiger2/aiger.cc | 41 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 8de482bc0..29b8ee96b 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1311,8 +1311,15 @@ struct Aiger2Backend : Backend { log("\n"); log(" write_aiger2 [options] [filename]\n"); log("\n"); - log("Write the current design to an AIGER file.\n"); + log("Write the selected module to an AIGER file.\n"); log("\n"); + log(" -strash\n"); + log(" perform structural hashing while writing\n"); + log("\n"); + log(" -flatten\n"); + log(" allow descending into submodules and write a flattened view of the design\n"); + log(" hierarchy starting at the selected top\n"); + log("\n"); log("This command is able to ingest all combinational cells except for:\n"); log("\n"); pool supported = {KNOWN_OPS}; @@ -1384,11 +1391,41 @@ struct Aiger2Backend : Backend { } Aiger2Backend; struct XAiger2Backend : Backend { - XAiger2Backend() : Backend("xaiger2", "(experimental) write design to XAIGER file") + XAiger2Backend() : Backend("xaiger2", "(experimental) write module to XAIGER file") { experimental(); } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" write_xaiger2 [options] [filename]\n"); + log("\n"); + log("Write the selected module to a XAIGER file including the 'h' and 'a' extensions\n"); + log("with box information for ABC.\n"); + log("\n"); + log(" -strash\n"); + log(" perform structural hashing while writing\n"); + log("\n"); + log(" -flatten\n"); + log(" allow descending into submodules and write a flattened view of the design\n"); + log(" hierarchy starting at the selected top\n"); + log("\n"); + log(" -mapping_prep\n"); + log(" after the file is written, prepare the module for reintegration of\n"); + log(" a mapping in a subsequent command. all cells which are not blackboxed nor\n"); + log(" whiteboxed are removed from the design as well as all wires which only\n"); + log(" connect to removed cells\n"); + log(" (conflicts with -flatten)\n"); + log("\n"); + log(" -map2 \n"); + log(" write a map2 file which 'read_xaiger2 -sc_mapping' can read to\n"); + log(" reintegrate a mapping\n"); + log(" (conflicts with -flatten)\n"); + log("\n"); + } + void execute(std::ostream *&f, std::string filename, std::vector args, Design *design) override { log_header(design, "Executing XAIGER2 backend.\n"); From d0a11e26f391a670b73b822671e7b974e112e59a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 11:59:52 +0200 Subject: [PATCH 075/240] aiger2: Add test of writing a flattened view --- tests/various/aiger2.ys | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index e008cdfaf..d2b024d2f 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -193,3 +193,32 @@ select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D equiv_make gold test equiv equiv_induct -undef equiv equiv_status -assert equiv + +design -reset +read_verilog -icells < Date: Mon, 7 Oct 2024 12:27:37 +0200 Subject: [PATCH 076/240] aiger2: Try to fix VS build --- backends/aiger2/aiger.cc | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 29b8ee96b..3fc6ccdba 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -47,11 +47,8 @@ PRIVATE_NAMESPACE_BEGIN #define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, \ ID($pmux), ID($bmux) /*, ARITH_OPS*/ -template +template struct Index { - static constexpr Lit CFALSE = Writer::CONST_FALSE; - static constexpr Lit CTRUE = Writer::CONST_TRUE; - struct HierCursor; struct ModuleInfo { Module *module; @@ -664,7 +661,7 @@ struct Index { } }; -struct AigerWriter : Index { +struct AigerWriter : Index { typedef unsigned int Lit; const static Lit CONST_FALSE = 0; @@ -804,7 +801,7 @@ struct AigerWriter : Index { } }; -struct XAigerAnalysis : Index { +struct XAigerAnalysis : Index { const static int CONST_FALSE = 0; const static int CONST_TRUE = 0; const static constexpr int EMPTY_LIT = -1; From f44a418212c61ae032d1aecbdc3de588ba3a1f5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 12:27:54 +0200 Subject: [PATCH 077/240] read_xaiger2: Add casts to silence warnings --- frontends/aiger2/xaiger.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 4c7305876..18cfe94dd 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -88,7 +88,7 @@ struct Xaiger2Frontend : public Frontend { log_error("Inconsistent header\n"); std::vector outputs; - for (int i = 0; i < O; i++) { + for (int i = 0; i < (int) O; i++) { int po; *f >> po; log_assert(f->get() == '\n'); @@ -110,7 +110,7 @@ struct Xaiger2Frontend : public Frontend { if (!(map_file >> pi_idx >> woffset >> name)) log_error("Bad map file (1)\n"); int lit = (2 * pi_idx) + 2; - if (lit < 0 || lit >= bits.size()) + if (lit < 0 || lit >= (int) bits.size()) log_error("Bad map file (2)\n"); Wire *w = module->wire(name); if (!w || woffset < 0 || woffset >= w->width) @@ -140,7 +140,7 @@ struct Xaiger2Frontend : public Frontend { if (!def) log_error("Bad map file (22)\n"); - if (box_seq >= boxes.size()) { + if (box_seq >= (int) boxes.size()) { boxes.resize(box_seq + 1); retained_boxes.resize(box_seq + 1); } @@ -151,7 +151,7 @@ struct Xaiger2Frontend : public Frontend { } } - for (int i = 0; i < A; i++) { + for (int i = 0; i < (int) A; i++) { while (f->get() & 0x80 && !f->eof()); while (f->get() & 0x80 && !f->eof()); } @@ -185,7 +185,7 @@ struct Xaiger2Frontend : public Frontend { box_id = read_be32(*f); box_seq = read_be32(*f); - log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size()); + log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size()); log_assert(box_seq < boxes.size()); auto [cell, def] = boxes[box_seq]; @@ -213,7 +213,7 @@ struct Xaiger2Frontend : public Frontend { } } - log_assert(box_ci_idx == box_outputs); + log_assert(box_ci_idx == (int) box_outputs); ci_counter += box_ci_idx; } log_assert(pi_num + ci_counter == ci_num); @@ -324,7 +324,7 @@ struct Xaiger2Frontend : public Frontend { box_id = read_be32(*f); box_seq = read_be32(*f); - log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size()); + log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size()); log_assert(box_seq < boxes.size()); auto [cell, def] = boxes[box_seq]; @@ -340,9 +340,9 @@ struct Xaiger2Frontend : public Frontend { SigSpec conn; for (int j = 0; j < port->width; j++) { - log_assert(co_counter + box_co_idx < outputs.size()); + log_assert(co_counter + box_co_idx < (int) outputs.size()); int lit = outputs[co_counter + box_co_idx++]; - log_assert(lit >= 0 && lit < bits.size()); + log_assert(lit >= 0 && lit < (int) bits.size()); SigBit bit = bits[lit]; if (bit == RTLIL::Sm) log_error("Malformed mapping (1)\n"); @@ -352,7 +352,7 @@ struct Xaiger2Frontend : public Frontend { } } - log_assert(box_co_idx == box_inputs); + log_assert(box_co_idx == (int) box_inputs); co_counter += box_co_idx; } log_assert(po_num + co_counter == co_num); @@ -389,10 +389,10 @@ struct Xaiger2Frontend : public Frontend { if (!(map_file >> po_idx >> woffset >> name)) log_error("Bad map file (3)\n"); po_idx += co_counter; - if (po_idx < 0 || po_idx >= outputs.size()) + if (po_idx < 0 || po_idx >= (int) outputs.size()) log_error("Bad map file (4)\n"); int lit = outputs[po_idx]; - if (lit < 0 || lit >= bits.size()) + if (lit < 0 || lit >= (int) bits.size()) log_error("Bad map file (5)\n"); if (bits[lit] == RTLIL::Sm) log_error("Bad map file (6)\n"); @@ -409,10 +409,10 @@ struct Xaiger2Frontend : public Frontend { if (!(map_file >> po_idx >> poffset >> box_name >> box_port)) log_error("Bad map file (7)\n"); po_idx += co_counter; - if (po_idx < 0 || po_idx >= outputs.size()) + if (po_idx < 0 || po_idx >= (int) outputs.size()) log_error("Bad map file (8)\n"); int lit = outputs[po_idx]; - if (lit < 0 || lit >= bits.size()) + if (lit < 0 || lit >= (int) bits.size()) log_error("Bad map file (9)\n"); if (bits[lit] == RTLIL::Sm) log_error("Bad map file (10)\n"); From 7989d53c58d793109dee49404bf17b0871277cd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 14:19:49 +0200 Subject: [PATCH 078/240] read_xaiger2: Add help --- frontends/aiger2/xaiger.cc | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 18cfe94dd..04beee396 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -38,7 +38,26 @@ IdString read_idstring(std::istream &f) } struct Xaiger2Frontend : public Frontend { - Xaiger2Frontend() : Frontend("xaiger2", "read XAIGER file (new)") {} + Xaiger2Frontend() : Frontend("xaiger2", "(experimental) read XAIGER file") + { + experimental(); + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" read_xaiger2 -sc_mapping [options] \n"); + log("\n"); + log("Read a standard cell mapping from a XAIGER file into an existing module.\n"); + log("\n"); + log(" -module_name \n"); + log(" name of the target module\n"); + log("\n"); + log(" -map2 \n"); + log(" read file with symbol information\n"); + log("\n"); + } void read_sc_mapping(std::istream *&f, std::string filename, std::vector args, Design *design) { From b01b17689e919ed09ec80918b6aa23d093f355e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 14:49:17 +0200 Subject: [PATCH 079/240] Add test of error not getting silenced --- tests/various/logger_cmd_error.sh | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100755 tests/various/logger_cmd_error.sh diff --git a/tests/various/logger_cmd_error.sh b/tests/various/logger_cmd_error.sh new file mode 100755 index 000000000..dd0585965 --- /dev/null +++ b/tests/various/logger_cmd_error.sh @@ -0,0 +1,9 @@ +#!/usr/bin/env bash + +trap 'echo "ERROR in logger_cmd_error.sh" >&2; exit 1' ERR + +(../../yosys -v 3 -C <&1 | grep -F "ERROR: Module \`nonexistent' not found!" > /dev/null From ca5c2fdff1d2e1e5bc1fbfb1764e75e934f015a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 15:26:48 +0200 Subject: [PATCH 080/240] quicklogic: Relax the LUT number test --- tests/arch/quicklogic/qlf_k6n10f/div.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/div.ys b/tests/arch/quicklogic/qlf_k6n10f/div.ys index 5ca5b3051..dd5de9d3a 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/div.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/div.ys @@ -10,5 +10,5 @@ EOF equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 26 t:$lut +select -assert-max 100 t:$lut select -assert-none t:$lut %% t:* %D From 407343a7a12385bba40e406f68270b95afabb09b Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 12 Aug 2024 14:21:05 +0300 Subject: [PATCH 081/240] Pyosys Wheels * Created `setup.py`: Python package manifest to build `pyosys` wheels with a custom extension to build and include `libyosys.so` using Make * `.gitignore`: Added byproducts of the Python wheel build process * `Makefile`: Added `-undefined dynamic_lookup` to `libyosys.so` so missing symbols can be resolved by importing into a Python interpreter * `kernel/yosys.cc`: Gated `PyImport_AppendInittab` with `!Py_IsInitialized`; as of Python 3.12, the interpreter is already initialized and `PyImport_AppendInittab` would cause an exception to be raised * Created `wheels.yml`: CI workflow for building wheels for CPython on: * Linux (glibc, musl) and Darwin * x86-64 and arm64 --- .github/workflows/wheels.yml | 111 +++++++++++++++++++++++++++++++++++ .gitignore | 7 ++- Makefile | 2 +- kernel/yosys.cc | 13 ++-- setup.py | 97 ++++++++++++++++++++++++++++++ 5 files changed, 224 insertions(+), 6 deletions(-) create mode 100644 .github/workflows/wheels.yml create mode 100644 setup.py diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml new file mode 100644 index 000000000..9f3394d84 --- /dev/null +++ b/.github/workflows/wheels.yml @@ -0,0 +1,111 @@ +name: Build Wheels for PyPI +on: + workflow_dispatch: + push: + # tags: ["yosys-*"] +jobs: + build_wheels: + strategy: + matrix: + os: [ + # You can't cross-compile on Linux, so might as well do the emulated + # workload on its own + { + name: "Ubuntu 22.04", + family: "linux", + runner: "ubuntu-22.04", + archs: "x86_64", + }, + { + name: "Ubuntu 22.04", + family: "linux", + runner: "ubuntu-22.04", + archs: "aarch64", + }, + # While you can cross-compile on macOS, this is less of a headache + { + name: "macOS 13", + family: "macos", + runner: "macos-13", + archs: "x86_64", + }, + { + name: "macOS 14", + family: "macos", + runner: "macos-14", + archs: "arm64", + }, + # TODO: Make Windows Work + # { + # name: "Windows Server 2019", + # family: "windows", + # runner: "windows-2019", + # archs: "AMD64 ARM64", + # }, + ] + name: Build Wheels | ${{ matrix.os.name }} | ${{ matrix.os.archs }} + runs-on: ${{ matrix.os.runner }} + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + submodules: true + - if: ${{ matrix.os.family == 'linux' }} + name: "[Linux] Set up QEMU" + uses: docker/setup-qemu-action@v2 + - uses: actions/setup-python@v3 + - name: Get Boost Source + run: | + mkdir -p boost + curl -L https://sourceforge.net/projects/boost/files/boost/1.83.0/boost_1_83_0.tar.bz2 | tar --strip-components=1 -xjC boost + - name: Seed Makefile.bak + # For every sed, a .bak is created so it can be copied over Makefile to + # rever the change for the next Python version to be built. + # + # This creates a .bak for the first Python version's cp to consume. + run: | + cp Makefile Makefile.bak + - if: ${{ matrix.os.family == 'macos' }} + name: "[macOS] Flex/Bison" + run: | + brew install flex bison + echo "PATH=$(brew --prefix flex)/bin:$PATH" >> $GITHUB_ENV + echo "PATH=$(brew --prefix bison)/bin:$PATH" >> $GITHUB_ENV + - if: ${{ matrix.os.family == 'macos' && matrix.os.archs == 'arm64' }} + name: "[macOS/arm64] Install Python 3.8 (see: https://cibuildwheel.pypa.io/en/stable/faq/#macos-building-cpython-38-wheels-on-arm64)" + uses: actions/setup-python@v5 + with: + python-version: 3.8 + - name: Build wheels + uses: pypa/cibuildwheel@v2.20.0 + env: + # Explaining the build steps: + # 1. Revert previous seds (if any) + # 2. Delete the libboost static archives from previous builds (if any) + # 3. Navigate to boost source extracted in previous GHA step + # 4-5. Build Boost against current version of Python, only for + # static linkage + # (Boost is statically linked because system boost packages + # wildly vary in versions, including the libboost_python3 + # version) + # 6-7. Return to package directory and sed the Makefile to point at + # the newly compiled libboost_python + CIBW_SKIP: pp* # The Makefile requires python3-config which is not in pypy + CIBW_ARCHS: ${{ matrix.os.archs }} + CIBW_BUILD_VERBOSITY: "1" + CIBW_BEFORE_ALL_LINUX: yum install -y libffi-devel flex bison || apk add libffi-dev flex bison + CIBW_BEFORE_ALL_MAC: brew install libffi + CIBW_BEFORE_BUILD: | + cp Makefile.bak Makefile &&\ + cd ./boost &&\ + rm -rf ./pfx &&\ + ./bootstrap.sh --prefix=./pfx &&\ + ./b2 --prefix=./pfx --with-filesystem --with-system --with-python cxxflags="$(python3-config --includes) -std=c++17 -fPIC" cflags="$(python3-config --includes) -fPIC" link=static variant=release install &&\ + ls ./pfx/lib/libboost_python*.a &&\ + cd {package} &&\ + sed -i'.bak' -e "1i\\ + LINKFLAGS = -L./boost/pfx/lib" -e "1i\\ + CXXFLAGS = -I./boost/pfx/include" -e "s@BOOST_PYTHON_LIB ?=@BOOST_PYTHON_LIB = $(ls ./boost/pfx/lib/libboost_python*.a)\nTrash =@" Makefile + - uses: actions/upload-artifact@v3 + with: + path: ./dist/*.whl diff --git a/.gitignore b/.gitignore index e82343e89..5d6a466db 100644 --- a/.gitignore +++ b/.gitignore @@ -45,4 +45,9 @@ __pycache__ /tests/unit/bintest/ /tests/unit/objtest/ /tests/ystests -/result \ No newline at end of file +/result +/dist +/*.egg-info +/build +/venv +/boost diff --git a/Makefile b/Makefile index 5b6fc3ff2..ebea193cf 100644 --- a/Makefile +++ b/Makefile @@ -742,7 +742,7 @@ $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS) libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) ifeq ($(OS), Darwin) - $(P) $(CXX) -o libyosys.so -shared -Wl,-install_name,$(LIBDIR)/libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC) + $(P) $(CXX) -o libyosys.so -shared -undefined dynamic_lookup -Wl,-install_name,$(LIBDIR)/libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC) else $(P) $(CXX) -o libyosys.so -shared -Wl,-soname,$(LIBDIR)/libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC) endif diff --git a/kernel/yosys.cc b/kernel/yosys.cc index efdc54b79..510151479 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -555,10 +555,15 @@ void yosys_setup() #undef X #ifdef WITH_PYTHON - PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); - Py_Initialize(); - PyRun_SimpleString("import sys"); - signal(SIGINT, SIG_DFL); + // With Python 3.12, calling PyImport_AppendInittab on an already + // initialized platform fails (such as when libyosys is imported + // from a Python interpreter) + if (!Py_IsInitialized()) { + PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); + Py_Initialize(); + PyRun_SimpleString("import sys"); + signal(SIGINT, SIG_DFL); + } #endif Pass::init_register(); diff --git a/setup.py b/setup.py new file mode 100644 index 000000000..02e6e5843 --- /dev/null +++ b/setup.py @@ -0,0 +1,97 @@ +#!/usr/bin/env python3 +# Copyright (C) 2024 Efabless Corporation +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +import os +import re +import shlex +import shutil +from setuptools import setup, Extension +from setuptools.command.build_ext import build_ext + +__dir__ = os.path.dirname(os.path.abspath(__file__)) + +yosys_version_rx = re.compile(r"YOSYS_VER\s*:=\s*([\w\-\+\.]+)") + +version = yosys_version_rx.search( + open(os.path.join(__dir__, "Makefile"), encoding="utf8").read() +)[1] + + +class libyosys_so_ext(Extension): + def __init__( + self, + ) -> None: + super().__init__( + "libyosys.so", + [], + ) + self.args = [ + "ENABLE_PYOSYS=1", + # Wheel meant to be imported from interpreter + "ENABLE_PYTHON_CONFIG_EMBED=0", + # Would need to be installed separately by the user + "ENABLE_TCL=0", + # Would need to be installed separately by the user + "ENABLE_READLINE=0", + # Show compile commands + "PRETTY=0", + ] + + def custom_build(self, bext: build_ext): + bext.spawn( + ["make", f"-j{os.cpu_count() or 1}", self.name] + + shlex.split(os.getenv("makeFlags", "")) + + self.args + ) + build_path = os.path.dirname(os.path.dirname(bext.get_ext_fullpath(self.name))) + pyosys_path = os.path.join(build_path, "pyosys") + target = os.path.join(pyosys_path, os.path.basename(self.name)) + os.makedirs(pyosys_path, exist_ok=True) + shutil.copyfile(self.name, target) + + # I don't know how debug info is getting here. + bext.spawn(["strip", "-S", target]) + + +class custom_build_ext(build_ext): + def build_extension(self, ext) -> None: + if not hasattr(ext, "custom_build"): + return super().build_extension(ext) + return ext.custom_build(self) + + +setup( + name="pyosys", + packages=["pyosys"], + version=version, + description="Python access to libyosys", + long_description=open(os.path.join(__dir__, "README.md")).read(), + long_description_content_type="text/markdown", + author="Claire Xenia Wolf", + author_email="claire@yosyshq.com", + install_requires=["wheel", "setuptools"], + classifiers=[ + "License :: OSI Approved :: MIT License", + "Programming Language :: Python :: 3", + "Intended Audience :: Developers", + "Operating System :: POSIX :: Linux", + "Operating System :: MacOS :: MacOS X", + ], + package_dir={"pyosys": "misc"}, + python_requires=">=3.8", + ext_modules=[libyosys_so_ext()], + cmdclass={ + "build_ext": custom_build_ext, + }, +) From ab4ea84679a9af5fa6172a4b4ce55c86d7a1ac5c Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sat, 28 Sep 2024 21:03:43 +0300 Subject: [PATCH 082/240] wheels: more compatibility * Update manylinux images * FFI now built as a per-platform static library * Explicitly set minimum macOS deployment target, use clang on macOS * Try enabling Windows (as an experiment) * Disable aarch64-linux, aarch64-windows --- .github/workflows/_run_cibw_linux.py | 44 ++++++++++++ .github/workflows/cibw_before_all.sh | 21 ++++++ .github/workflows/cibw_before_build.sh | 23 +++++++ .github/workflows/wheels.yml | 92 +++++++++++++------------- .gitignore | 1 + 5 files changed, 134 insertions(+), 47 deletions(-) create mode 100644 .github/workflows/_run_cibw_linux.py create mode 100644 .github/workflows/cibw_before_all.sh create mode 100644 .github/workflows/cibw_before_build.sh diff --git a/.github/workflows/_run_cibw_linux.py b/.github/workflows/_run_cibw_linux.py new file mode 100644 index 000000000..675817ae0 --- /dev/null +++ b/.github/workflows/_run_cibw_linux.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# Copyright (C) 2024 Efabless Corporation +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +""" +This runs the cibuildwheel step from the wheels workflow locally. +""" + +import os +import yaml +import platform +import subprocess + +__dir__ = os.path.dirname(os.path.abspath(__file__)) + + +workflow = yaml.safe_load(open(os.path.join(__dir__, "wheels.yml"))) + +env = os.environ.copy() + +steps = workflow["jobs"]["build_wheels"]["steps"] +cibw_step = None +for step in steps: + if (step.get("uses") or "").startswith("pypa/cibuildwheel"): + cibw_step = step + break + +for key, value in cibw_step["env"].items(): + if key.endswith("WIN") or key.endswith("MAC"): + continue + env[key] = value + +env["CIBW_ARCHS"] = os.getenv("CIBW_ARCHS") or platform.machine() +subprocess.check_call(["cibuildwheel"], env=env) diff --git a/.github/workflows/cibw_before_all.sh b/.github/workflows/cibw_before_all.sh new file mode 100644 index 000000000..934902380 --- /dev/null +++ b/.github/workflows/cibw_before_all.sh @@ -0,0 +1,21 @@ +set -e +set -x + +# Build-time dependencies +## Linux Docker Images +if command -v yum &> /dev/null; then + yum install -y flex bison +fi + +if command -v apk &> /dev/null; then + apk add flex bison +fi + +## macOS/Windows -- install in GitHub Action itself, not container + +# Build Static FFI (platform-dependent but not Python version dependent) +cd ffi +SHELL=bash CFLAGS=-fPIC CXXFLAGS=-fPIC ./configure --prefix=$PWD/pfx + +make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) +sed -i.bak 's@-L${toolexeclibdir} -lffi@${toolexeclibdir}/libffi.a@' ./pfx/lib/pkgconfig/libffi.pc diff --git a/.github/workflows/cibw_before_build.sh b/.github/workflows/cibw_before_build.sh new file mode 100644 index 000000000..03baf110b --- /dev/null +++ b/.github/workflows/cibw_before_build.sh @@ -0,0 +1,23 @@ +set -e +set -x + +# Build boost +cd ./boost +## Delete the artefacts from previous builds (if any) +rm -rf ./pfx +## Bootstrap bjam +./bootstrap.sh --prefix=./pfx +## Build Boost against current version of Python, only for +## static linkage (Boost is statically linked because system boost packages +## wildly vary in versions, including the libboost_python3 version) +./b2\ + -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu)\ + --prefix=./pfx\ + --with-filesystem\ + --with-system\ + --with-python\ + cxxflags="$(python3-config --includes) -std=c++17 -fPIC"\ + cflags="$(python3-config --includes) -fPIC"\ + link=static\ + variant=release\ + install diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index 9f3394d84..5961f364a 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -6,23 +6,25 @@ on: jobs: build_wheels: strategy: + fail-fast: false matrix: os: [ - # You can't cross-compile on Linux, so might as well do the emulated - # workload on its own { name: "Ubuntu 22.04", family: "linux", runner: "ubuntu-22.04", archs: "x86_64", }, - { - name: "Ubuntu 22.04", - family: "linux", - runner: "ubuntu-22.04", - archs: "aarch64", - }, - # While you can cross-compile on macOS, this is less of a headache + ## Aarch64 is disabled for now: GitHub is committing to EOY + ## for free aarch64 runners for open-source projects and + ## emulation times out: + ## https://github.com/orgs/community/discussions/19197#discussioncomment-10550689 + # { + # name: "Ubuntu 22.04", + # family: "linux", + # runner: "ubuntu-22.04", + # archs: "aarch64", + # }, { name: "macOS 13", family: "macos", @@ -35,13 +37,12 @@ jobs: runner: "macos-14", archs: "arm64", }, - # TODO: Make Windows Work - # { - # name: "Windows Server 2019", - # family: "windows", - # runner: "windows-2019", - # archs: "AMD64 ARM64", - # }, + { + name: "Windows Server 2019", + family: "windows", + runner: "windows-2019", + archs: "AMD64", + }, ] name: Build Wheels | ${{ matrix.os.name }} | ${{ matrix.os.archs }} runs-on: ${{ matrix.os.runner }} @@ -55,22 +56,27 @@ jobs: uses: docker/setup-qemu-action@v2 - uses: actions/setup-python@v3 - name: Get Boost Source + shell: bash run: | mkdir -p boost - curl -L https://sourceforge.net/projects/boost/files/boost/1.83.0/boost_1_83_0.tar.bz2 | tar --strip-components=1 -xjC boost - - name: Seed Makefile.bak - # For every sed, a .bak is created so it can be copied over Makefile to - # rever the change for the next Python version to be built. - # - # This creates a .bak for the first Python version's cp to consume. + curl -L https://github.com/boostorg/boost/releases/download/boost-1.86.0/boost-1.86.0-b2-nodocs.tar.gz | tar --strip-components=1 -xzC boost + - name: Get FFI + shell: bash run: | - cp Makefile Makefile.bak + mkdir -p ffi + curl -L https://github.com/libffi/libffi/releases/download/v3.4.6/libffi-3.4.6.tar.gz | tar --strip-components=1 -xzC ffi + ## Software installed by default in GitHub Action Runner VMs: + ## https://github.com/actions/runner-images - if: ${{ matrix.os.family == 'macos' }} name: "[macOS] Flex/Bison" run: | brew install flex bison echo "PATH=$(brew --prefix flex)/bin:$PATH" >> $GITHUB_ENV echo "PATH=$(brew --prefix bison)/bin:$PATH" >> $GITHUB_ENV + - if : ${{ matrix.os.family == 'windows' }} + name: "[Windows] Flex/Bison" + run: | + choco install winflexbison3 - if: ${{ matrix.os.family == 'macos' && matrix.os.archs == 'arm64' }} name: "[macOS/arm64] Install Python 3.8 (see: https://cibuildwheel.pypa.io/en/stable/faq/#macos-building-cpython-38-wheels-on-arm64)" uses: actions/setup-python@v5 @@ -79,33 +85,25 @@ jobs: - name: Build wheels uses: pypa/cibuildwheel@v2.20.0 env: - # Explaining the build steps: - # 1. Revert previous seds (if any) - # 2. Delete the libboost static archives from previous builds (if any) - # 3. Navigate to boost source extracted in previous GHA step - # 4-5. Build Boost against current version of Python, only for - # static linkage - # (Boost is statically linked because system boost packages - # wildly vary in versions, including the libboost_python3 - # version) - # 6-7. Return to package directory and sed the Makefile to point at - # the newly compiled libboost_python CIBW_SKIP: pp* # The Makefile requires python3-config which is not in pypy CIBW_ARCHS: ${{ matrix.os.archs }} CIBW_BUILD_VERBOSITY: "1" - CIBW_BEFORE_ALL_LINUX: yum install -y libffi-devel flex bison || apk add libffi-dev flex bison - CIBW_BEFORE_ALL_MAC: brew install libffi - CIBW_BEFORE_BUILD: | - cp Makefile.bak Makefile &&\ - cd ./boost &&\ - rm -rf ./pfx &&\ - ./bootstrap.sh --prefix=./pfx &&\ - ./b2 --prefix=./pfx --with-filesystem --with-system --with-python cxxflags="$(python3-config --includes) -std=c++17 -fPIC" cflags="$(python3-config --includes) -fPIC" link=static variant=release install &&\ - ls ./pfx/lib/libboost_python*.a &&\ - cd {package} &&\ - sed -i'.bak' -e "1i\\ - LINKFLAGS = -L./boost/pfx/lib" -e "1i\\ - CXXFLAGS = -I./boost/pfx/include" -e "s@BOOST_PYTHON_LIB ?=@BOOST_PYTHON_LIB = $(ls ./boost/pfx/lib/libboost_python*.a)\nTrash =@" Makefile + # manylinux2014 (default) does not have a modern enough C++ compiler for Yosys + CIBW_MANYLINUX_X86_64_IMAGE: manylinux_2_28 + CIBW_MANYLINUX_AARCH64_IMAGE: manylinux_2_28 + CIBW_BEFORE_ALL: bash ./.github/workflows/cibw_before_all.sh + CIBW_ENVIRONMENT: > + CXXFLAGS=-I./boost/pfx/include + LINKFLAGS=-L./boost/pfx/lib + PKG_CONFIG_PATH=./ffi/pfx/lib/pkgconfig + makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a' + CIBW_ENVIRONMENT_MACOS: > + CXXFLAGS=-I./boost/pfx/include + LINKFLAGS=-L./boost/pfx/lib + PKG_CONFIG_PATH=./ffi/pfx/lib/pkgconfig + MACOSX_DEPLOYMENT_TARGET=11 + makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' + CIBW_BEFORE_BUILD: bash ./.github/workflows/cibw_before_build.sh - uses: actions/upload-artifact@v3 with: path: ./dist/*.whl diff --git a/.gitignore b/.gitignore index 5d6a466db..5c3d8f4e9 100644 --- a/.gitignore +++ b/.gitignore @@ -51,3 +51,4 @@ __pycache__ /build /venv /boost +/ffi From ab84c105c14bfca00a6b87828cb665b40740b35b Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sat, 28 Sep 2024 23:11:45 +0300 Subject: [PATCH 083/240] Add test, shell for windows --- .github/workflows/wheels.yml | 5 +++-- .github/workflows/{ => wheels}/_run_cibw_linux.py | 2 +- .github/workflows/{ => wheels}/cibw_before_all.sh | 10 ++++++---- .github/workflows/{ => wheels}/cibw_before_build.sh | 7 +++++++ 4 files changed, 17 insertions(+), 7 deletions(-) rename .github/workflows/{ => wheels}/_run_cibw_linux.py (94%) rename .github/workflows/{ => wheels}/cibw_before_all.sh (55%) rename .github/workflows/{ => wheels}/cibw_before_build.sh (80%) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index 5961f364a..c6af2c8b2 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -91,7 +91,7 @@ jobs: # manylinux2014 (default) does not have a modern enough C++ compiler for Yosys CIBW_MANYLINUX_X86_64_IMAGE: manylinux_2_28 CIBW_MANYLINUX_AARCH64_IMAGE: manylinux_2_28 - CIBW_BEFORE_ALL: bash ./.github/workflows/cibw_before_all.sh + CIBW_BEFORE_ALL: bash ./.github/workflows/wheels/cibw_before_all.sh CIBW_ENVIRONMENT: > CXXFLAGS=-I./boost/pfx/include LINKFLAGS=-L./boost/pfx/lib @@ -103,7 +103,8 @@ jobs: PKG_CONFIG_PATH=./ffi/pfx/lib/pkgconfig MACOSX_DEPLOYMENT_TARGET=11 makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' - CIBW_BEFORE_BUILD: bash ./.github/workflows/cibw_before_build.sh + CIBW_BEFORE_BUILD: bash ./.github/workflows/wheels/cibw_before_build.sh + CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" - uses: actions/upload-artifact@v3 with: path: ./dist/*.whl diff --git a/.github/workflows/_run_cibw_linux.py b/.github/workflows/wheels/_run_cibw_linux.py similarity index 94% rename from .github/workflows/_run_cibw_linux.py rename to .github/workflows/wheels/_run_cibw_linux.py index 675817ae0..894470a5a 100644 --- a/.github/workflows/_run_cibw_linux.py +++ b/.github/workflows/wheels/_run_cibw_linux.py @@ -24,7 +24,7 @@ import subprocess __dir__ = os.path.dirname(os.path.abspath(__file__)) -workflow = yaml.safe_load(open(os.path.join(__dir__, "wheels.yml"))) +workflow = yaml.safe_load(open(os.path.join(os.path.dirname(__dir__), "wheels.yml"))) env = os.environ.copy() diff --git a/.github/workflows/cibw_before_all.sh b/.github/workflows/wheels/cibw_before_all.sh similarity index 55% rename from .github/workflows/cibw_before_all.sh rename to .github/workflows/wheels/cibw_before_all.sh index 934902380..28aae85ac 100644 --- a/.github/workflows/cibw_before_all.sh +++ b/.github/workflows/wheels/cibw_before_all.sh @@ -11,11 +11,13 @@ if command -v apk &> /dev/null; then apk add flex bison fi -## macOS/Windows -- install in GitHub Action itself, not container +## macOS/Windows -- installed in GitHub Action itself, not container # Build Static FFI (platform-dependent but not Python version dependent) cd ffi -SHELL=bash CFLAGS=-fPIC CXXFLAGS=-fPIC ./configure --prefix=$PWD/pfx - -make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) +## Ultimate libyosys.so will be shared, so we need fPIC for the static libraries +CFLAGS=-fPIC CXXFLAGS=-fPIC ./configure --prefix=$PWD/pfx +## Without this, SHELL has a space in its path which breaks the makefile +make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) SHELL=bash +## Forces static library to be used in all situations sed -i.bak 's@-L${toolexeclibdir} -lffi@${toolexeclibdir}/libffi.a@' ./pfx/lib/pkgconfig/libffi.pc diff --git a/.github/workflows/cibw_before_build.sh b/.github/workflows/wheels/cibw_before_build.sh similarity index 80% rename from .github/workflows/cibw_before_build.sh rename to .github/workflows/wheels/cibw_before_build.sh index 03baf110b..29fffe090 100644 --- a/.github/workflows/cibw_before_build.sh +++ b/.github/workflows/wheels/cibw_before_build.sh @@ -1,6 +1,13 @@ set -e set -x +# Don't use objects from previous compiles on Windows/macOS +make clean + +# DEBUG: show python3 and python3-config outputs +python3 --version +python3-config --includes + # Build boost cd ./boost ## Delete the artefacts from previous builds (if any) From 67f17a1c97a097eb59d8a7d1b81fc5aff66f0da8 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sun, 29 Sep 2024 12:28:18 +0300 Subject: [PATCH 084/240] wheels: symlink python3-config --- .github/workflows/wheels.yml | 2 +- .github/workflows/wheels/cibw_before_build.sh | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index c6af2c8b2..eafaa957f 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -83,7 +83,7 @@ jobs: with: python-version: 3.8 - name: Build wheels - uses: pypa/cibuildwheel@v2.20.0 + uses: pypa/cibuildwheel@v2.21.1 env: CIBW_SKIP: pp* # The Makefile requires python3-config which is not in pypy CIBW_ARCHS: ${{ matrix.os.archs }} diff --git a/.github/workflows/wheels/cibw_before_build.sh b/.github/workflows/wheels/cibw_before_build.sh index 29fffe090..018b0e0df 100644 --- a/.github/workflows/wheels/cibw_before_build.sh +++ b/.github/workflows/wheels/cibw_before_build.sh @@ -5,6 +5,10 @@ set -x make clean # DEBUG: show python3 and python3-config outputs +if [ "$(uname)" != "Linux" ]; then + # https://github.com/pypa/cibuildwheel/issues/2021 + ln -s $(dirname $(readlink -f $(which python3)))/python3-config $(dirname $(which python3))/python3-config +fi python3 --version python3-config --includes From 08c23b7632a744c1bf3a42f035611757cb64a1ea Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sun, 29 Sep 2024 16:02:37 +0300 Subject: [PATCH 085/240] wheels: skip musllinux for now --- .github/workflows/wheels.yml | 8 ++++++-- .github/workflows/wheels/cibw_before_all.sh | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index eafaa957f..a91c873fb 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -85,7 +85,11 @@ jobs: - name: Build wheels uses: pypa/cibuildwheel@v2.21.1 env: - CIBW_SKIP: pp* # The Makefile requires python3-config which is not in pypy + # * APIs not supported by PyPy + # * Musllinux temporarily disabled because it takes too much time + CIBW_SKIP: > + pp* + *musllinux* CIBW_ARCHS: ${{ matrix.os.archs }} CIBW_BUILD_VERBOSITY: "1" # manylinux2014 (default) does not have a modern enough C++ compiler for Yosys @@ -107,4 +111,4 @@ jobs: CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" - uses: actions/upload-artifact@v3 with: - path: ./dist/*.whl + path: ./wheelhouse/*.whl diff --git a/.github/workflows/wheels/cibw_before_all.sh b/.github/workflows/wheels/cibw_before_all.sh index 28aae85ac..fbb8dcad8 100644 --- a/.github/workflows/wheels/cibw_before_all.sh +++ b/.github/workflows/wheels/cibw_before_all.sh @@ -18,6 +18,6 @@ cd ffi ## Ultimate libyosys.so will be shared, so we need fPIC for the static libraries CFLAGS=-fPIC CXXFLAGS=-fPIC ./configure --prefix=$PWD/pfx ## Without this, SHELL has a space in its path which breaks the makefile -make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) SHELL=bash +make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) ## Forces static library to be used in all situations sed -i.bak 's@-L${toolexeclibdir} -lffi@${toolexeclibdir}/libffi.a@' ./pfx/lib/pkgconfig/libffi.pc From 0bb1f899e84f97b53a765581a5e91450a8074215 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Fri, 4 Oct 2024 16:14:26 +0300 Subject: [PATCH 086/240] wheels: convert versions to match pypa spec, add uploading * wheel versions now replace `+` with `.post` to match spec at https://packaging.python.org/en/latest/specifications/version-specifiers/ * CI updates: * Bump action versions * Disabled Windows for now and documented why * Added a new job to upload all wheels * Added new variable, `PYPI_INDEX`: fallback 'https://pypi.org/' if unset * Added new secret, `PYPI_TOKEN` * .editorconfig now uses 2 spaces for YML (it kept setting mine to tabs and GitHub Actions doesn't like that) --- .editorconfig | 4 +++ .github/workflows/wheels.yml | 49 +++++++++++++++++++++++++----------- setup.py | 2 +- 3 files changed, 40 insertions(+), 15 deletions(-) diff --git a/.editorconfig b/.editorconfig index f5444d81a..572b73bd2 100644 --- a/.editorconfig +++ b/.editorconfig @@ -10,3 +10,7 @@ insert_final_newline = true indent_style = space indent_size = 2 trim_trailing_whitespace = false + +[*.yml] +indent_style = space +indent_size = 2 diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index a91c873fb..c6132685b 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -1,8 +1,7 @@ name: Build Wheels for PyPI on: workflow_dispatch: - push: - # tags: ["yosys-*"] + jobs: build_wheels: strategy: @@ -37,24 +36,27 @@ jobs: runner: "macos-14", archs: "arm64", }, - { - name: "Windows Server 2019", - family: "windows", - runner: "windows-2019", - archs: "AMD64", - }, + ## Windows is disabled because of an issue with compiling FFI as + ## under MinGW in the GitHub Actions environment (SHELL variable has + ## whitespace.) + # { + # name: "Windows Server 2019", + # family: "windows", + # runner: "windows-2019", + # archs: "AMD64", + # }, ] name: Build Wheels | ${{ matrix.os.name }} | ${{ matrix.os.archs }} runs-on: ${{ matrix.os.runner }} steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 with: fetch-depth: 0 submodules: true - if: ${{ matrix.os.family == 'linux' }} name: "[Linux] Set up QEMU" - uses: docker/setup-qemu-action@v2 - - uses: actions/setup-python@v3 + uses: docker/setup-qemu-action@v3 + - uses: actions/setup-python@v5 - name: Get Boost Source shell: bash run: | @@ -73,7 +75,7 @@ jobs: brew install flex bison echo "PATH=$(brew --prefix flex)/bin:$PATH" >> $GITHUB_ENV echo "PATH=$(brew --prefix bison)/bin:$PATH" >> $GITHUB_ENV - - if : ${{ matrix.os.family == 'windows' }} + - if: ${{ matrix.os.family == 'windows' }} name: "[Windows] Flex/Bison" run: | choco install winflexbison3 @@ -86,7 +88,7 @@ jobs: uses: pypa/cibuildwheel@v2.21.1 env: # * APIs not supported by PyPy - # * Musllinux temporarily disabled because it takes too much time + # * Musllinux disabled because it increases build time from 48m to ~3h CIBW_SKIP: > pp* *musllinux* @@ -109,6 +111,25 @@ jobs: makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' CIBW_BEFORE_BUILD: bash ./.github/workflows/wheels/cibw_before_build.sh CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" - - uses: actions/upload-artifact@v3 + - uses: actions/upload-artifact@v4 with: + name: python-wheels path: ./wheelhouse/*.whl + upload_wheels: + name: Upload Wheels + runs-on: ubuntu-latest + needs: build_wheels + steps: + - uses: actions/download-artifact@v4 + with: + name: python-wheels + path: "." + - run: | + ls + mkdir -p ./dist + mv *.whl ./dist + - name: Publish + uses: pypa/gh-action-pypi-publish@release/v1 + with: + password: ${{ secrets.PYPI_TOKEN }} + repository-url: ${{ vars.PYPI_INDEX || 'https://upload.pypi.org/legacy/' }} diff --git a/setup.py b/setup.py index 02e6e5843..f9d455f0b 100644 --- a/setup.py +++ b/setup.py @@ -25,7 +25,7 @@ yosys_version_rx = re.compile(r"YOSYS_VER\s*:=\s*([\w\-\+\.]+)") version = yosys_version_rx.search( open(os.path.join(__dir__, "Makefile"), encoding="utf8").read() -)[1] +)[1].replace("+", ".post") class libyosys_so_ext(Extension): From 43128f628311e7dd69fc5aab802b9a0242efef87 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 7 Oct 2024 16:51:17 +0300 Subject: [PATCH 087/240] wheels: move from postreleases to minor versions, remove authors --- setup.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/setup.py b/setup.py index f9d455f0b..221965971 100644 --- a/setup.py +++ b/setup.py @@ -25,7 +25,9 @@ yosys_version_rx = re.compile(r"YOSYS_VER\s*:=\s*([\w\-\+\.]+)") version = yosys_version_rx.search( open(os.path.join(__dir__, "Makefile"), encoding="utf8").read() -)[1].replace("+", ".post") +)[1].replace( + "+", "." +) # Convert to patch version class libyosys_so_ext(Extension): @@ -78,8 +80,6 @@ setup( description="Python access to libyosys", long_description=open(os.path.join(__dir__, "README.md")).read(), long_description_content_type="text/markdown", - author="Claire Xenia Wolf", - author_email="claire@yosyshq.com", install_requires=["wheel", "setuptools"], classifiers=[ "License :: OSI Approved :: MIT License", From a76bcdc58fd22ba9441cdcc2b80c565966034c6e Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 7 Oct 2024 17:58:48 +0200 Subject: [PATCH 088/240] bufnorm: avoid remove warning. NFC --- passes/techmap/bufnorm.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index 75060673e..3c2cd9230 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -70,9 +70,9 @@ struct BufnormPass : public Pass { log(" to chain 'keep' wires first, then ports in declaration order,\n"); log(" and then the other wires in alphanumeric sort order.)\n"); log("\n"); - log(" -noinit\n"); - log(" Do not move 'init' attributes to the wires on FF output ports.\n"); - log("\n"); + // log(" -noinit\n"); + // log(" Do not move 'init' attributes to the wires on FF output ports.\n"); + // log("\n"); log("Run 'bufnorm' with -pos, -bits, or -conn on the whole design to remove all\n"); log("$buf buffer cells and exit 'buffered-normalized mode' again.\n"); log("\n"); @@ -108,7 +108,7 @@ struct BufnormPass : public Pass { bool nokeep_mode = false; bool nosticky_mode = false; bool alphasort_mode = false; - bool noinit_mode = false; // FIXME: Actually move init attributes + // bool noinit_mode = false; // FIXME: Actually move init attributes bool nomode_mode = false; bool pos_mode = false; @@ -169,11 +169,11 @@ struct BufnormPass : public Pass { got_non_update_reset_opt = true; continue; } - if (arg == "-noinit") { - noinit_mode = true; - got_non_update_reset_opt = true; - continue; - } + // if (arg == "-noinit") { + // noinit_mode = true; + // got_non_update_reset_opt = true; + // continue; + // } if (arg == "-pos") { pos_mode = true; got_non_update_reset_opt = true; From d7cf0238fda76e6a7f565dc4b521828e164c00f6 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 7 Oct 2024 20:17:05 +0300 Subject: [PATCH 089/240] wheels: properly migrate to artifact@v4 --- .github/workflows/wheels.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index c6132685b..d59f8e1ec 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -113,7 +113,7 @@ jobs: CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" - uses: actions/upload-artifact@v4 with: - name: python-wheels + name: python-wheels-${{ matrix.os.runner }} path: ./wheelhouse/*.whl upload_wheels: name: Upload Wheels @@ -122,8 +122,9 @@ jobs: steps: - uses: actions/download-artifact@v4 with: - name: python-wheels path: "." + pattern: python-wheels-* + merge-multiple: true - run: | ls mkdir -p ./dist From b15103625b4161f41c9c468c1e71c58df24f4884 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 8 Oct 2024 07:49:14 +1300 Subject: [PATCH 090/240] ci: Switch test build docs to our runner --- .github/workflows/prepare-docs.yml | 5 +++++ .github/workflows/test-build.yml | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index e2689d4df..6d3f4ecea 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -64,6 +64,11 @@ jobs: docs/source/_images docs/source/code_examples + - name: Test build docs + shell: bash + run: | + make docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= + - name: Trigger RTDs build if: ${{ needs.check_docs_rebuild.outputs.docs_export == 'true' }} uses: dfm/rtds-action@v1.1.0 diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 1502d8aa0..e5aed6af3 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -189,8 +189,3 @@ jobs: shell: bash run: | make -C docs test -j${{ env.procs }} - - - name: Test build docs - shell: bash - run: | - make docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= From c1604424aad3116c435bfb08c12f92447e140f6b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 8 Oct 2024 08:11:35 +1300 Subject: [PATCH 091/240] ci: Call make html directly Since `docs/prep` is a prerequisite of `docs`, and should be the *only* prerequisite, calling `make docs` could end up hiding a problem with files missing from the uploaded artifact. Instead, call `make` from the docs directory which should be closer to what will run on RTDs. --- .github/workflows/prepare-docs.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index 6d3f4ecea..e0388c7a3 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -67,7 +67,7 @@ jobs: - name: Test build docs shell: bash run: | - make docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= + make -C docs html -j${{ env.procs }} TARGETS= EXTRA_TARGETS= - name: Trigger RTDs build if: ${{ needs.check_docs_rebuild.outputs.docs_export == 'true' }} From 1e3973c5cb009944ed65eb6117d548fc17c78639 Mon Sep 17 00:00:00 2001 From: Mike Inouye Date: Mon, 7 Oct 2024 21:57:30 +0000 Subject: [PATCH 092/240] Explictly #include for std::variant usage. Signed-off-by: Mike Inouye --- kernel/hashlib.h | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 157ccf4ce..859115829 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include From 408597b478f884681254f07a25c14f9485a7b5e6 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 8 Oct 2024 00:20:07 +0000 Subject: [PATCH 093/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5b6fc3ff2..92274a56d 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+153 +YOSYS_VER := 0.45+217 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From f079772ade52cedb30f056fa5819cd9df92d8356 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 8 Oct 2024 08:47:51 +0200 Subject: [PATCH 094/240] Add TODO for missing help messages --- backends/functional/cxx.cc | 2 ++ backends/functional/test_generic.cc | 2 ++ passes/cmds/example_dt.cc | 2 ++ 3 files changed, 6 insertions(+) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index b8b25df8b..1f677120a 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -246,6 +246,8 @@ struct FunctionalCxxBackend : public Backend { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); + log("TODO: add help message\n"); + log("\n"); } void printCxx(std::ostream &stream, std::string, Module *module) diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 10a7a50f0..dc235d79a 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -122,6 +122,8 @@ struct FunctionalTestGeneric : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); + log("TODO: add help message\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index aaf07dadd..1912d7da1 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -27,6 +27,8 @@ struct ExampleDtPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); + log("TODO: add help message\n"); + log("\n"); } From 268926cb5be57c43cbefd3cd0e67e40770e521a5 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Tue, 8 Oct 2024 14:34:17 +0200 Subject: [PATCH 095/240] write_btor: don't emit undriven bits multiple times * Fixes #4640 --- backends/btor/btor.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 9cfd967e5..81402fa49 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1077,6 +1077,7 @@ struct BtorWorker btorf("%d input %d\n", nid, sid); ywmap_input(s); nid_width[nid] = GetSize(s); + add_nid_sig(nid, s); for (int j = 0; j < GetSize(s); j++) nidbits.push_back(make_pair(nid, j)); From b4fd8e7ed837a86ee205cdf8766387239880743a Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 9 Oct 2024 00:20:28 +0000 Subject: [PATCH 096/240] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f4276b94d..4985bbade 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+217 +YOSYS_VER := 0.45+240 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From e97731b9dda91fa5fa53ed87df7c34163ba59a41 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Oct 2024 08:08:00 +0200 Subject: [PATCH 097/240] Release version 0.46 --- CHANGELOG | 22 +++++++++++++++++++++- Makefile | 4 ++-- docs/source/conf.py | 2 +- 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 03bf5ac57..ab7690b4b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,28 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.45 .. Yosys 0.46-dev +Yosys 0.45 .. Yosys 0.46 -------------------------- + * Various + - Added new "functional backend" infrastructure with three example + backends (C++, SMTLIB and Rosette). + - Added new coarse-grain buffer cell type "$buf" to RTLIL. + - Added "-y" command line option to execute a Python script with + libyosys available as a built-in module. + - Added support for casting to type in Verilog frontend. + + * New commands and options + - Added "clockgate" pass for automatic clock gating cell insertion. + - Added "bufnorm" experimental pass to convert design into + buffered-normalized form. + - Added experimental "aiger2" and "xaiger2" backends, and an + experimental "abc_new" command + - Added "-force-detailed-loop-check" option to "check" pass. + - Added "-unit_delay" option to "read_liberty" pass. + + * Verific support + - Added left and right bound properties to wires when using + specific VHDL types. Yosys 0.44 .. Yosys 0.45 -------------------------- diff --git a/Makefile b/Makefile index 4985bbade..fe07074eb 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+240 +YOSYS_VER := 0.46 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -170,7 +170,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/conf.py b/docs/source/conf.py index 4371b79f1..8e30fcc7c 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -5,7 +5,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2024 YosysHQ GmbH' -yosys_ver = "0.45" +yosys_ver = "0.46" # select HTML theme html_theme = 'furo' From 8893dadc4b6be686f84870292f3182290325f7ad Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Oct 2024 08:12:44 +0200 Subject: [PATCH 098/240] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index ab7690b4b..4106885fa 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.46 .. Yosys 0.47-dev +-------------------------- + Yosys 0.45 .. Yosys 0.46 -------------------------- * Various diff --git a/Makefile b/Makefile index fe07074eb..f81e1fea2 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.46 +YOSYS_VER := 0.46+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -170,7 +170,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline e97731b.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) From c93c7f8307f1d8ec81b71aabe9c761280752338d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Oct 2024 09:50:36 +0200 Subject: [PATCH 099/240] CI: lld is now separate brew package --- .github/actions/setup-build-env/action.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index c5a0d14ab..12ae883bd 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -14,7 +14,7 @@ runs: if: runner.os == 'macOS' shell: bash run: | - HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm + HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm lld - name: Linux runtime environment if: runner.os == 'Linux' From 3d6b8b8e1a350ae1ec688d41b8d8eae0109e5119 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Wed, 9 Oct 2024 12:44:52 +0300 Subject: [PATCH 100/240] wheels: fix missing yosys-abc/share directory * `misc/__init__.py`: * checks if there's a `yosys-abc` in the same directory - if yes, sets the variable `sys._pyosys_abc` * checks if there's a `share` in the same directory - if yes, sets the variable `sys._pyosys_share_dirname` * `yosys.cc::init_share_dirname`: check for `sys._pyosys_share_dirname`, use it at the highest priority if Python is enabled * `yosys.cc::init_abc_executable_name`: check for `sys._pyosys_abc`, use it at at the highest priority if Python is enabled * `Makefile`: add new target, `share`, to only create the extra targets * `setup.py`: compile libyosys.so, yosys-abc and share, and copy them all as part of the pyosys build * `test/arch/ecp5/add_sub.py`: ported `add_sub.ys` to Python to act as a test for the share directory and abc with Python wheels, used in CI --- .github/workflows/wheels.yml | 2 +- Makefile | 6 +++++ kernel/yosys.cc | 52 ++++++++++++++++++++++++------------ misc/__init__.py | 14 ++++++++++ setup.py | 34 +++++++++++++++++++---- tests/arch/ecp5/add_sub.py | 20 ++++++++++++++ 6 files changed, 105 insertions(+), 23 deletions(-) create mode 100644 tests/arch/ecp5/add_sub.py diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index d59f8e1ec..d66239a16 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -110,7 +110,7 @@ jobs: MACOSX_DEPLOYMENT_TARGET=11 makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' CIBW_BEFORE_BUILD: bash ./.github/workflows/wheels/cibw_before_build.sh - CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" + CIBW_TEST_COMMAND: python3 {project}/tests/arch/ecp5/add_sub.py - uses: actions/upload-artifact@v4 with: name: python-wheels-${{ matrix.os.runner }} diff --git a/Makefile b/Makefile index f81e1fea2..0be664b9a 100644 --- a/Makefile +++ b/Makefile @@ -737,6 +737,12 @@ compile-only: $(OBJS) $(GENFILES) $(EXTRA_TARGETS) @echo " Compile successful." @echo "" +.PHONY: share +share: $(EXTRA_TARGETS) + @echo "" + @echo " Share directory created." + @echo "" + $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS) $(P) $(CXX) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LINKFLAGS) $(LINKFLAGS) $(OBJS) $(LIBS) $(LIBS_VERIFIC) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 510151479..374b07d06 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -554,17 +554,17 @@ void yosys_setup() #include "kernel/constids.inc" #undef X - #ifdef WITH_PYTHON - // With Python 3.12, calling PyImport_AppendInittab on an already - // initialized platform fails (such as when libyosys is imported - // from a Python interpreter) - if (!Py_IsInitialized()) { - PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); - Py_Initialize(); - PyRun_SimpleString("import sys"); - signal(SIGINT, SIG_DFL); - } - #endif +#ifdef WITH_PYTHON + // With Python 3.12, calling PyImport_AppendInittab on an already + // initialized platform fails (such as when libyosys is imported + // from a Python interpreter) + if (!Py_IsInitialized()) { + PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); + Py_Initialize(); + PyRun_SimpleString("import sys"); + signal(SIGINT, SIG_DFL); + } +#endif Pass::init_register(); yosys_design = new RTLIL::Design; @@ -1013,6 +1013,16 @@ void init_share_dirname() #else void init_share_dirname() { +# ifdef WITH_PYTHON + PyObject *sys_obj = PyImport_ImportModule("sys"); + + if (PyObject_HasAttrString(sys_obj, "_pyosys_share_dirname")) { + PyObject *share_path_obj = PyObject_GetAttrString(sys_obj, "_pyosys_share_dirname"); + const char *share_path = PyUnicode_AsUTF8(share_path_obj); + yosys_share_dirname = std::string(share_path); + return; + } +# endif std::string proc_self_path = proc_self_dirname(); # if defined(_WIN32) && !defined(YOSYS_WIN32_UNIX_DIR) std::string proc_share_path = proc_self_path + "share\\"; @@ -1058,12 +1068,20 @@ void init_abc_executable_name() } #else yosys_abc_executable = proc_self_dirname() + proc_program_prefix()+ "yosys-abc"; -#endif -#ifdef _WIN32 -#ifndef ABCEXTERNAL +# ifdef _WIN32 if (!check_file_exists(yosys_abc_executable + ".exe") && check_file_exists(proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc.exe")) yosys_abc_executable = proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc"; -#endif +# endif + +# ifdef WITH_PYTHON + PyObject *sys_obj = PyImport_ImportModule("sys"); + + if (PyObject_HasAttrString(sys_obj, "_pyosys_abc")) { + PyObject *abc_path_obj = PyObject_GetAttrString(sys_obj, "_pyosys_abc"); + const char *abc_path = PyUnicode_AsUTF8(abc_path_obj); + yosys_abc_executable = std::string(abc_path); + } +# endif #endif } @@ -1132,7 +1150,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi if (command == "auto") { std::string filename_trim = filename; - + auto has_extension = [](const std::string& filename, const std::string& extension) { if (filename.size() >= extension.size()) { return filename.compare(filename.size() - extension.size(), extension.size(), extension) == 0; @@ -1143,7 +1161,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi if (has_extension(filename_trim, ".gz")) { filename_trim.erase(filename_trim.size() - 3); } - + if (has_extension(filename_trim, ".v")) { command = " -vlog2k"; } else if (has_extension(filename_trim, ".sv")) { diff --git a/misc/__init__.py b/misc/__init__.py index 330fd6d86..d74e3f5bd 100644 --- a/misc/__init__.py +++ b/misc/__init__.py @@ -1,5 +1,19 @@ import os import sys + sys.setdlopenflags(os.RTLD_NOW | os.RTLD_GLOBAL) +__dir__ = os.path.abspath(os.path.dirname(__file__)) +sys._pyosys_dir = os.path.abspath(__dir__) + +bin_ext = ".exe" if os.name == "nt" else "" + +_share_candidate = os.path.join(__dir__, "share") +if os.path.isdir(_share_candidate): + sys._pyosys_share_dirname = _share_candidate + os.path.sep + +_abc_candidate = os.path.join(__dir__, f"yosys-abc{bin_ext}") +if os.path.isfile(_abc_candidate): + sys._pyosys_abc = _abc_candidate + __all__ = ["libyosys"] diff --git a/setup.py b/setup.py index 221965971..b3a6a9280 100644 --- a/setup.py +++ b/setup.py @@ -44,26 +44,50 @@ class libyosys_so_ext(Extension): "ENABLE_PYTHON_CONFIG_EMBED=0", # Would need to be installed separately by the user "ENABLE_TCL=0", - # Would need to be installed separately by the user "ENABLE_READLINE=0", + "ENABLE_EDITLINE=0", + # Always compile and include ABC in wheel + "ABCEXTERNAL=", # Show compile commands "PRETTY=0", ] def custom_build(self, bext: build_ext): bext.spawn( - ["make", f"-j{os.cpu_count() or 1}", self.name] + [ + "make", + f"-j{os.cpu_count() or 1}", + self.name, + "yosys-abc", + "share", + ] + shlex.split(os.getenv("makeFlags", "")) + self.args ) build_path = os.path.dirname(os.path.dirname(bext.get_ext_fullpath(self.name))) pyosys_path = os.path.join(build_path, "pyosys") - target = os.path.join(pyosys_path, os.path.basename(self.name)) os.makedirs(pyosys_path, exist_ok=True) - shutil.copyfile(self.name, target) + + # libyosys.so + target = os.path.join(pyosys_path, os.path.basename(self.name)) + shutil.copy(self.name, target) + bext.spawn(["strip", "-S", target]) + + # yosys-abc + yosys_abc_target = os.path.join(pyosys_path, "yosys-abc") + shutil.copy("yosys-abc", yosys_abc_target) + bext.spawn(["strip", "-S", "yosys-abc"]) + + # share directory + share_target = os.path.join(pyosys_path, "share") + try: + shutil.rmtree(share_target) + except FileNotFoundError: + pass + + shutil.copytree("share", share_target) # I don't know how debug info is getting here. - bext.spawn(["strip", "-S", target]) class custom_build_ext(build_ext): diff --git a/tests/arch/ecp5/add_sub.py b/tests/arch/ecp5/add_sub.py new file mode 100644 index 000000000..0232ac1db --- /dev/null +++ b/tests/arch/ecp5/add_sub.py @@ -0,0 +1,20 @@ +import os +from pyosys import libyosys as ys + +__dir__ = os.path.dirname(os.path.abspath(__file__)) +add_sub = os.path.join(__dir__, "..", "common", "add_sub.v") + +base = ys.Design() +ys.run_pass(f"read_verilog {add_sub}", base) +ys.run_pass("hierarchy -top top", base) +ys.run_pass("proc", base) +ys.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5", base) + +postopt = ys.Design() +ys.run_pass("design -load postopt", postopt) +ys.run_pass("cd top", postopt) +ys.run_pass("select -assert-min 25 t:LUT4", postopt) +ys.run_pass("select -assert-max 26 t:LUT4", postopt) +ys.run_pass("select -assert-count 10 t:PFUMX", postopt) +ys.run_pass("select -assert-count 6 t:L6MUX21", postopt) +ys.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D", postopt) From a6ccf2204787fb264dbd8cc23b998939ac5e41f6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Oct 2024 14:09:10 +0200 Subject: [PATCH 101/240] force brew formula update --- .github/actions/setup-build-env/action.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index 12ae883bd..0c8cd281c 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -14,6 +14,7 @@ runs: if: runner.os == 'macOS' shell: bash run: | + HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew update HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm lld - name: Linux runtime environment From 6ab39319647009def8926da4c82ca340790fa4b9 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 9 Oct 2024 13:48:26 +0200 Subject: [PATCH 102/240] write_btor: only initialize array with const value when it is fully def * If all addresses of an array have the same initial value, they can be initialized in one go in btor with the constraint that the initial value must be fully const and thus can't have undef bits in --- backends/btor/btor.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 9cfd967e5..1c2d5132e 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -832,7 +832,10 @@ struct BtorWorker } } - if (constword) + // If not fully defined, undef bits should be able to take a + // different value for each address so we can't initialise from + // one value (and btor2parser doesn't like it) + if (constword && firstword.is_fully_def()) { if (verbose) btorf("; initval = %s\n", log_signal(firstword)); From 575415ade2d8877b26944cf08ac3f6dd2ad3d035 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 9 Oct 2024 15:07:56 +0200 Subject: [PATCH 103/240] driver: switch to cxxopts, replace -B --- .gitmodules | 3 + kernel/driver.cc | 538 +++++++++++++++++++---------------------------- libs/cxxopts | 1 + 3 files changed, 219 insertions(+), 323 deletions(-) create mode 160000 libs/cxxopts diff --git a/.gitmodules b/.gitmodules index d88d4b1e5..de3bb2e74 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "abc"] path = abc url = https://github.com/YosysHQ/abc +[submodule "libs/cxxopts"] + path = libs/cxxopts + url = git@github.com:jarro2783/cxxopts.git diff --git a/kernel/driver.cc b/kernel/driver.cc index 53608c260..0c0dc9023 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -19,6 +19,8 @@ #include "kernel/yosys.h" #include "libs/sha1/sha1.h" +#include "libs/cxxopts/include/cxxopts.hpp" +#include #ifdef YOSYS_ENABLE_READLINE # include @@ -55,55 +57,6 @@ USING_YOSYS_NAMESPACE -char *optarg; -int optind = 1, optcur = 1, optopt = 0; -int getopt(int argc, char **argv, const char *optstring) -{ - if (optind >= argc) - return -1; - - if (argv[optind][0] != '-' || argv[optind][1] == 0) { - optopt = 1; - optarg = argv[optind++]; - return optopt; - } - - bool takes_arg = false; - optopt = argv[optind][optcur]; - - if (optopt == '-') { - ++optind; - return -1; - } - - for (int i = 0; optstring[i]; i++) - if (optopt == optstring[i] && optstring[i + 1] == ':') - takes_arg = true; - - if (!takes_arg) { - if (argv[optind][++optcur] == 0) - optind++, optcur = 1; - return optopt; - } - - if (argv[optind][++optcur]) { - optarg = argv[optind++] + optcur; - optcur = 1; - return optopt; - } - - if (++optind >= argc) { - fprintf(stderr, "%s: option '-%c' expects an argument\n", argv[0], optopt); - optopt = '?'; - return optopt; - } - - optarg = argv[optind]; - optind++, optcur = 1; - - return optopt; -} - #ifdef EMSCRIPTEN # include # include @@ -235,6 +188,7 @@ int main(int argc, char **argv) std::vector passes_commands; std::vector frontend_files; std::vector plugin_filenames; + std::vector special_args; std::string output_filename = ""; std::string scriptfile = ""; std::string depsfile = ""; @@ -251,305 +205,243 @@ int main(int argc, char **argv) bool mode_v = false; bool mode_q = false; - if (argc == 2 && (!strcmp(argv[1], "-h") || !strcmp(argv[1], "-help") || !strcmp(argv[1], "--help"))) - { - printf("\n"); - printf("Usage: %s [options] [ [..]]\n", argv[0]); - printf("\n"); - printf(" -Q\n"); - printf(" suppress printing of banner (copyright, disclaimer, version)\n"); - printf("\n"); - printf(" -T\n"); - printf(" suppress printing of footer (log hash, version, timing statistics)\n"); - printf("\n"); - printf(" -q\n"); - printf(" quiet operation. only write warnings and error messages to console\n"); - printf(" use this option twice to also quiet warning messages\n"); - printf("\n"); - printf(" -v \n"); - printf(" print log headers up to level to the console. (this\n"); - printf(" implies -q for everything except the 'End of script.' message.)\n"); - printf("\n"); - printf(" -t\n"); - printf(" annotate all log messages with a time stamp\n"); - printf("\n"); - printf(" -d\n"); - printf(" print more detailed timing stats at exit\n"); - printf("\n"); - printf(" -l logfile\n"); - printf(" write log messages to the specified file\n"); - printf("\n"); - printf(" -L logfile\n"); - printf(" like -l but open log file in line buffered mode\n"); - printf("\n"); - printf(" -o outfile\n"); - printf(" write the design to the specified file on exit\n"); - printf("\n"); - printf(" -b backend\n"); - printf(" use this backend for the output file specified on the command line\n"); - printf("\n"); - printf(" -f frontend\n"); - printf(" use the specified frontend for the input files on the command line\n"); - printf("\n"); - printf(" -H\n"); - printf(" print the command list\n"); - printf("\n"); - printf(" -h command\n"); - printf(" print the help message for the specified command\n"); - printf("\n"); - printf(" -s scriptfile\n"); - printf(" execute the commands in the script file\n"); + cxxopts::Options options(argv[0], "Yosys Open SYnthesis Suite"); + options.set_width(SIZE_MAX); + + options.add_options("operation") + ("b,backend", "use for the output file specified on the command line", + cxxopts::value(), "") + ("f,frontend", "use for the input files on the command line", + cxxopts::value(), "") + ("s,scriptfile", "execute the commands in ", + cxxopts::value(), "") #ifdef YOSYS_ENABLE_TCL - printf("\n"); - printf(" -c tcl_scriptfile\n"); - printf(" execute the commands in the tcl script file (see 'help tcl' for details)\n"); - printf("\n"); - printf(" -C\n"); - printf(" enters TCL interactive shell mode\n"); -#endif + ("c,tcl-scriptfile", "execute the commands in the TCL (see 'help tcl' for details)", + cxxopts::value(),"") + ("C,tcl-interactive", "enters TCL interactive shell mode") +#endif // YOSYS_ENABLE_TCL #ifdef WITH_PYTHON - printf("\n"); - printf(" -y python_scriptfile\n"); - printf(" execute a python script with libyosys available as a built-in module\n"); -#endif - printf("\n"); - printf(" -p command\n"); - printf(" execute the commands (to chain commands, separate them with semicolon + whitespace: 'cmd1; cmd2')\n"); - printf("\n"); - printf(" -m module_file\n"); - printf(" load the specified module (aka plugin)\n"); - printf("\n"); - printf(" -X\n"); - printf(" enable tracing of core data structure changes. for debugging\n"); - printf("\n"); - printf(" -M\n"); - printf(" will slightly randomize allocated pointer addresses. for debugging\n"); - printf("\n"); - printf(" -A\n"); - printf(" will call abort() at the end of the script. for debugging\n"); - printf("\n"); - printf(" -r \n"); - printf(" elaborate command line arguments using the specified top module\n"); - printf("\n"); - printf(" -D [=]\n"); - printf(" set the specified Verilog define (via \"read -define\")\n"); - printf("\n"); - printf(" -P [:]\n"); - printf(" dump the design when printing the specified log header to a file.\n"); - printf(" yosys_dump_.il is used as filename if none is specified.\n"); - printf(" Use 'ALL' as to dump at every header.\n"); - printf("\n"); - printf(" -W regex\n"); - printf(" print a warning for all log messages matching the regex.\n"); - printf("\n"); - printf(" -w regex\n"); - printf(" if a warning message matches the regex, it is printed as regular\n"); - printf(" message instead.\n"); - printf("\n"); - printf(" -e regex\n"); - printf(" if a warning message matches the regex, it is printed as error\n"); - printf(" message instead and the tool terminates with a nonzero return code.\n"); - printf("\n"); - printf(" -E \n"); - printf(" write a Makefile dependencies file with in- and output file names\n"); - printf("\n"); - printf(" -x \n"); - printf(" do not print warnings for the specified experimental feature\n"); - printf("\n"); - printf(" -g\n"); - printf(" globally enable debug log messages\n"); - printf("\n"); - printf(" -V\n"); - printf(" print version information and exit\n"); - printf("\n"); - printf("The option -S is a shortcut for calling the \"synth\" command, a default\n"); - printf("script for transforming the Verilog input to a gate-level netlist. For example:\n"); - printf("\n"); - printf(" yosys -o output.blif -S input.v\n"); - printf("\n"); - printf("For more complex synthesis jobs it is recommended to use the read_* and write_*\n"); - printf("commands in a script file instead of specifying input and output files on the\n"); - printf("command line.\n"); - printf("\n"); - printf("When no commands, script files or input files are specified on the command\n"); - printf("line, yosys automatically enters the interactive command mode. Use the 'help'\n"); - printf("command to get information on the individual commands.\n"); - printf("\n"); + ("y,py-scriptfile", "execute the Python