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tests: avoid interleaving lines in test output

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This commit is contained in:
Emil J. Tywoniak 2025-09-19 18:09:47 +02:00
parent 8371adf6b5
commit 3dd3079095
13 changed files with 14 additions and 19 deletions
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6
tests/various/hierarchy.sh
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@ -3,7 +3,7 @@
set -e
echo -n " TOP first - "
echo " TOP first - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module TOP(a, y);
@ -22,7 +22,7 @@ echo -n " TOP first - "
hierarchy -auto-top
EOY
echo -n " TOP last - "
echo " TOP last - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module aoi12(a, y);
@ -41,7 +41,7 @@ echo -n " TOP last - "
hierarchy -auto-top
EOY
echo -n " no explicit top - "
echo " no explicit top - "
../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
read_verilog << EOV
module aoi12(a, y);