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This commit is contained in:
Alain Dargelas 2025-02-27 10:48:01 -08:00
parent 4089c1b358
commit 3d1fb7a093
1 changed files with 4 additions and 8 deletions
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12
passes/silimate/obs_clean.cc
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@ -122,10 +122,8 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSp
RTLIL::SigSpec po = elt.first; RTLIL::SigSpec po = elt.first;
if ((!po.size()) || (!po[0].is_wire())) { if ((!po.size()) || (!po[0].is_wire())) {
// Can't perform the analysis correctly. // Can't perform the analysis correctly.
if (debug) { log_warning("Module %s contains some logic that prevents obs_clean analysis\n", module->name.c_str());
log("Module contains some logic that prevents obs_clean analysis\n"); log_flush();
log_flush();
}
return; return;
} }
RTLIL::Wire *w = po[0].wire; RTLIL::Wire *w = po[0].wire;
@ -150,10 +148,8 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSp
RTLIL::SigSpec po = elt.first; RTLIL::SigSpec po = elt.first;
if ((!po.size()) || (!po[0].is_wire())) { if ((!po.size()) || (!po[0].is_wire())) {
// Can't perform the analysis correctly. // Can't perform the analysis correctly.
if (debug) { log_warning("Module %s contains some logic that prevents obs_clean analysis\n", module->name.c_str());
log("Module contains some logic that prevents obs_clean analysis\n"); log_flush();
log_flush();
}
return; return;
} }
RTLIL::Wire *w = po[0].wire; RTLIL::Wire *w = po[0].wire;