From 3d1fb7a09341c47225418ef28ef1d673f9fc3108 Mon Sep 17 00:00:00 2001
From: Alain Dargelas <alain@silimate.com>
Date: Thu, 27 Feb 2025 10:48:01 -0800
Subject: [PATCH] warning

---
 passes/silimate/obs_clean.cc | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/passes/silimate/obs_clean.cc b/passes/silimate/obs_clean.cc
index 685bd1b89..759e8eaf0 100644
--- a/passes/silimate/obs_clean.cc
+++ b/passes/silimate/obs_clean.cc
@@ -122,10 +122,8 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSp
 		RTLIL::SigSpec po = elt.first;
 		if ((!po.size()) || (!po[0].is_wire())) {
 			// Can't perform the analysis correctly.
-			if (debug) {
-				log("Module contains some logic that prevents obs_clean analysis\n");
-				log_flush();
-			}
+			log_warning("Module %s contains some logic that prevents obs_clean analysis\n", module->name.c_str());
+			log_flush();
 			return;
 		}
 		RTLIL::Wire *w = po[0].wire;
@@ -150,10 +148,8 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSp
 		RTLIL::SigSpec po = elt.first;
 		if ((!po.size()) || (!po[0].is_wire())) {
 			// Can't perform the analysis correctly.
-			if (debug) {
-				log("Module contains some logic that prevents obs_clean analysis\n");
-				log_flush();
-			}
+			log_warning("Module %s contains some logic that prevents obs_clean analysis\n", module->name.c_str());
+			log_flush();
 			return;
 		}
 		RTLIL::Wire *w = po[0].wire;