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@ -122,10 +122,8 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSp
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RTLIL::SigSpec po = elt.first;
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if ((!po.size()) || (!po[0].is_wire())) {
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// Can't perform the analysis correctly.
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if (debug) {
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log("Module contains some logic that prevents obs_clean analysis\n");
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log_flush();
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}
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log_warning("Module %s contains some logic that prevents obs_clean analysis\n", module->name.c_str());
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log_flush();
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return;
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}
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RTLIL::Wire *w = po[0].wire;
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@ -150,10 +148,8 @@ void observabilityClean(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSp
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RTLIL::SigSpec po = elt.first;
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if ((!po.size()) || (!po[0].is_wire())) {
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// Can't perform the analysis correctly.
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if (debug) {
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log("Module contains some logic that prevents obs_clean analysis\n");
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log_flush();
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}
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log_warning("Module %s contains some logic that prevents obs_clean analysis\n", module->name.c_str());
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log_flush();
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return;
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}
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RTLIL::Wire *w = po[0].wire;
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