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abstract: test -slice for all modes, -rtlilslice for -init

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Emil J. Tywoniak 2025-02-25 00:18:16 +01:00
parent 5bd18613bb
commit 3cb7054e53
3 changed files with 133 additions and 8 deletions
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40
tests/various/abstract_state.ys
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@ -62,6 +62,39 @@ select -assert-count 1 @not %x:+[A] o:Q %i
# -----------------------------------------------------------------------------
design -reset
read_verilog <<EOT
module wide_flop_no_q (CLK, DDD, QQQ, magic);
input CLK;
input [2:0] DDD;
output reg [2:0] QQQ;
input magic;
always @(posedge CLK)
QQQ <= DDD;
endmodule
EOT
proc
opt_expr
opt_dff
dump
abstract -state -enablen magic -slice 0 w:QQQ
check -assert
# Connections to dff D input port
select -set conn_to_d t:$dff %x:+[D] t:$dff %d
# The D input port is partially fed with a mux
select -set mux @conn_to_d %ci t:$mux %i
select -assert-count 1 @mux
# and also the DDD input
select -assert-count 1 @conn_to_d w:DDD %i
# The S input port is fed with the magic wire
select -assert-count 1 @mux %x:+[S] w:magic %i
# The A input port is fed with an anyseq
select -assert-count 1 @mux %x:+[A] %ci t:$anyseq %i
# The B input port is fed with DDD
select -assert-count 1 @mux %x:+[B] %ci w:DDD %i
# -----------------------------------------------------------------------------
# Selecting wire Q connected to bit 0 of QQQ is the same as specifying
# QQQ with the -slice 0 argument
design -reset
read_verilog <<EOT
module wide_flop (CLK, DDD, QQQ, Q, magic);
input CLK;
input [2:0] DDD;
@ -78,18 +111,13 @@ design -save wide_flop
# Test that abstracting an output slice muxes an input slice
abstract -state -enablen magic w:Q
check -assert
# Connections to dff D input port
# Same testing as previous case
select -set conn_to_d t:$dff %x:+[D] t:$dff %d
# The D input port is partially fed with a mux
select -set mux @conn_to_d %ci t:$mux %i
select -assert-count 1 @mux
# and also the DDD input
select -assert-count 1 @conn_to_d w:DDD %i
# The S input port is fed with the magic wire
select -assert-count 1 @mux %x:+[S] w:magic %i
# The A input port is fed with an anyseq
select -assert-count 1 @mux %x:+[A] %ci t:$anyseq %i
# The B input port is fed with DDD
select -assert-count 1 @mux %x:+[B] %ci w:DDD %i
# -----------------------------------------------------------------------------
design -reset