mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-15 07:15:28 +00:00
Code Activity

abstract: test -slice for all modes, -rtlilslice for -init

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-02-25 00:18:16 +01:00
parent 5bd18613bb
commit 3cb7054e53
3 changed files with 133 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

76
tests/various/abstract_init.ys
View file

@ -37,3 +37,79 @@ select -assert-count 1 w:Q a:init=2'b01 %i
abstract -init w:QQQ
check -assert
select -assert-count 1 w:Q a:init=2'b0x %i
design -reset
read_verilog <<EOT
module foo (CLK, Q);
input CLK;
// downto
output reg [1:0] Q = 1'b1;
always @(posedge CLK)
Q <= ~Q;
endmodule
EOT
proc
opt_expr
opt_dff
select -assert-count 1 w:Q a:init=2'b01 %i
abstract -init -slice 0 w:Q
check -assert
select -assert-count 1 w:Q a:init=2'b0x %i
design -reset
read_verilog <<EOT
module foo (CLK, Q);
input CLK;
// downto
output reg [1:0] Q = 1'b1;
always @(posedge CLK)
Q <= ~Q;
endmodule
EOT
proc
opt_expr
opt_dff
select -assert-count 1 w:Q a:init=2'b01 %i
abstract -init -rtlilslice 0 w:Q
check -assert
select -assert-count 1 w:Q a:init=2'b0x %i
design -reset
read_verilog <<EOT
module foo (CLK, Q);
input CLK;
// upto
output reg [0:1] Q = 1'b1;
always @(posedge CLK)
Q <= ~Q;
endmodule
EOT
proc
opt_expr
opt_dff
select -assert-count 1 w:Q a:init=2'b01 %i
abstract -init -slice 0 w:Q
check -assert
select -assert-count 1 w:Q a:init=2'bx1 %i
design -reset
read_verilog <<EOT
module foo (CLK, Q);
input CLK;
// upto
output reg [0:1] Q = 1'b1;
always @(posedge CLK)
Q <= ~Q;
endmodule
EOT
proc
opt_expr
opt_dff
select -assert-count 1 w:Q a:init=2'b01 %i
abstract -init -rtlilslice 0 w:Q
check -assert
select -assert-count 1 w:Q a:init=2'b0x %i