mirror of
https://github.com/YosysHQ/yosys
synced 2025-05-29 18:29:13 +00:00
Add +/xilinx/cells_box.v containing models for ABC boxes
This commit is contained in:
parent
b89bb74452
commit
3ac4977b70
2 changed files with 11 additions and 0 deletions
10
techlibs/xilinx/cells_box.v
Normal file
10
techlibs/xilinx/cells_box.v
Normal file
|
@ -0,0 +1,10 @@
|
|||
(* abc_box_id = 1 *)
|
||||
module MUXF7(output O, input I0, I1, S);
|
||||
assign O = S ? I1 : I0;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 2 *)
|
||||
module MUXF8(output O, input I0, I1, S);
|
||||
assign O = S ? I1 : I0;
|
||||
endmodule
|
||||
|
Loading…
Add table
Add a link
Reference in a new issue