mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 04:28:18 +00:00
11 lines
198 B
Verilog
11 lines
198 B
Verilog
(* abc_box_id = 1 *)
|
|
module MUXF7(output O, input I0, I1, S);
|
|
assign O = S ? I1 : I0;
|
|
endmodule
|
|
|
|
(* abc_box_id = 2 *)
|
|
module MUXF8(output O, input I0, I1, S);
|
|
assign O = S ? I1 : I0;
|
|
endmodule
|
|
|