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Add sub-assign and and-assign tests

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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2020-06-25 14:20:47 +02:00
parent 470df03f3d
commit 39c39848a2
1 changed files with 34 additions and 0 deletions
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34
tests/opt/opt_expr_combined_assign.ys
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@ -47,3 +47,37 @@ equiv_opt -assert opt_expr -fine
design -load postopt design -load postopt
select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a -= i;
a -= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b11111111;
initial begin
a &= i;
a &= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$and r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i