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Use Nexus DSP pipelined registers.
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nella
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5 changed files with 479 additions and 15 deletions
156
tests/arch/nexus/pipe_mul.sv
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156
tests/arch/nexus/pipe_mul.sv
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// https://github.com/YosysHQ/yosys/issues/5917
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module mul18_pipe(
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input logic clk,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul18_pipe_signed (
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input logic clk,
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input logic signed [17:0] a,
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input logic signed [17:0] b,
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output logic signed [35:0] y
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);
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logic signed [17:0] a_r;
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logic signed [17:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul18_pipe_in_only (
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input logic clk,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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end
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assign y = a_r * b_r;
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endmodule
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module mul18_pipe_out_only (
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input logic clk,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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always_ff @(posedge clk)
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y <= a * b;
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endmodule
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module mul18_pipe_io_rst (
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input logic clk,
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input logic rst,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk)
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if (rst) begin a_r <= 0; b_r <= 0; y <= 0; end
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else begin a_r <= a; b_r <= b; y <= a_r * b_r; end
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endmodule
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module mul24_io (
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input logic clk,
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input logic [23:0] a,
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input logic [23:0] b,
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output logic [47:0] y
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);
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logic [23:0] a_r;
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logic [23:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul32_io (
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input logic clk,
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input logic [31:0] a,
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input logic [31:0] b,
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output logic [63:0] y
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);
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logic [31:0] a_r;
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logic [31:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul18_negedge (
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input logic clk,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(negedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul18_rst_nonzero (
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input logic clk,
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input logic rst,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk)
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if (rst) begin a_r <= 18'h3; b_r <= 18'h7; end
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else begin a_r <= a; b_r <= b; end
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always_ff @(posedge clk)
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y <= a_r * b_r;
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endmodule
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module mul18_two_clock (
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input logic clk0,
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input logic clk1,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk0) a_r <= a;
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always_ff @(posedge clk1) b_r <= b;
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assign y = a_r * b_r;
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endmodule
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73
tests/arch/nexus/pipe_mul.ys
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73
tests/arch/nexus/pipe_mul.ys
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@ -0,0 +1,73 @@
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read_verilog -sv pipe_mul.sv
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design -save pristine
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# 18x18 MULT
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design -load pristine
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hierarchy -top mul18_pipe
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synth_nexus -family lifcl -top mul18_pipe
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select -assert-count 1 t:MULT18X18
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select -assert-count 0 t:FD1P3*
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# 18x18 MULT (signed)
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design -load pristine
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hierarchy -top mul18_pipe_signed
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synth_nexus -family lifcl -top mul18_pipe_signed
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select -assert-count 1 t:MULT18X18
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select -assert-count 0 t:FD1P3*
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# 18x18 MULT (input only)
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design -load pristine
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hierarchy -top mul18_pipe_in_only
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synth_nexus -family lifcl -top mul18_pipe_in_only
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select -assert-count 1 t:MULT18X18
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select -assert-count 0 t:FD1P3*
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# 18x18 MULT (output only)
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design -load pristine
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hierarchy -top mul18_pipe_out_only
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synth_nexus -family lifcl -top mul18_pipe_out_only
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select -assert-count 1 t:MULT18X18
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select -assert-count 0 t:FD1P3*
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# 18x18 MULT (reset)
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design -load pristine
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hierarchy -top mul18_pipe_io_rst
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synth_nexus -family lifcl -top mul18_pipe_io_rst
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select -assert-count 1 t:MULT18X18
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select -assert-count 0 t:FD1P3*
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# 24x24 MUL -> pipelined 36X36 MULT
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design -load pristine
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hierarchy -top mul24_io
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synth_nexus -family lifcl -top mul24_io
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select -assert-count 1 t:MULT36X36
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select -assert-count 0 t:FD1P3*
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# 32x32 MUL -> pipelined 36X36 MULT
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design -load pristine
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hierarchy -top mul32_io
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synth_nexus -family lifcl -top mul32_io
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select -assert-count 1 t:MULT36X36
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select -assert-count 0 t:FD1P3*
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# DSP reg is rising-edge
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design -load pristine
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hierarchy -top mul18_negedge
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synth_nexus -family lifcl -top mul18_negedge
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select -assert-count 1 t:MULT18X18
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select -assert-min 1 t:FD1P3*
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# DSP reg only resets to 0
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design -load pristine
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hierarchy -top mul18_rst_nonzero
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synth_nexus -family lifcl -top mul18_rst_nonzero
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select -assert-count 1 t:MULT18X18
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select -assert-min 1 t:FD1P3*
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# two clocks feeding input regs -> can't share one CLK pin
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design -load pristine
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hierarchy -top mul18_two_clock
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synth_nexus -family lifcl -top mul18_two_clock
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select -assert-count 1 t:MULT18X18
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select -assert-min 1 t:FD1P3*
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